NS_ASS(VI)

NAME
ns_as - National Semiconductor 16032 assembler/linker

SYNOPSIS
..../lib/ns/as [options] argument ...

DESCRIPTION
The assembler for the National Semiconductor 16032 is based on the universal assembler uni_ass(VI). The mnemonics for the instructions are taken from the NS-16000 Programmers Reference Manual. The syntax of the instruction operands is similar to the syntax used in that manual, although the meaning is sometimes quite different. The cross assembler issued by National Semiconductor associates a type (sb,..) with each symbol and automatically generates sb offset mode for symbols of type sb. This assembler does not record the types, each symbol simply produces an untyped value.

The possible operands are:

general registers
    These are called r0, r1, r2, r3, r4, r5, r6 and r7. The symbol REG is used to indicate use of any of these 8 registers in other operands.

floating point registers
    These are called f0, f1, f2, f3, f4, f5, f6 and f7.

dedicated registers
    All types of dedicated registers can be used with the appropriate instructions. Examples: sb, fp, intbase, ptb1.

expr(REG)
    register relative

expr(fp)
    frame pointer relative

expr(sb)
    static base relative

expr(sp)
    stack pointer relative

expr(pc)
    program counter relative, the expression indicates a location in memory from which the current value of '.' is subtracted by the assembler. E.g. "movw label(pc),r0; label: .word ..." moves the contents of the word at label to r0.

expr(expr(fb))

expr(expr(sb))

expr(expr(sp))
    memory relative

@expr
    absolute

external(expr)+expr
    The external mode is provided, although this assembler does not build a module table.

tos top of stack.

Usage of the scaled index operands is allowed.
The convention used to indicate offset length by appending :B, :W or :D to offsets is not implemented. The assembler tries to find out the minimal size needed for any constant in an operand of the instruction placed in the text segment. Offsets in instructions outside .text are always four bytes.
All special operands, e.g. register list, configuration list, have the same format as in the Programmers Reference Manual.
Whenever possible the assembler automatically uses the short(quick) opcodes for jsr(jsb), jump(br), add(addq), cmp(cmpq) and mov(movq).

BUGS
The data types floating and packed-decimal are not supported.
Initialization of floating-point numbers is not possible.
The mnemonics of the slave processor instructions are poorly documented, the format of the NS-16032S-6 data sheet is used.
The documentation gave contradictory information on the format of a few instructions.
-   Three different schemes are presented for the encoding of the last operand of the block instructions.
-   Two different values are specified for the encoding of the msr register in smr and lmr instructions.
-   Two different possibilities are given for the encoding of the instructions movsu and movus.

EXAMPLE
00000000 0E0B02		setcfg	[ m ]
		label:
00000003 EC3E		lprb	psr,r7
00000005 2D37		sprw	intbase,r6
00000007 EA7C		br	label
00000009 02803B		bsr	rout1
0000000C 228044		cxp	rout1
0000000F 1204		ret	4
00000011 4204		rett	4
00000013 328044		rxp	rout1
00000016 1E0300		rdval	r0
00000019 163028		scsr	r5
0000001C 3F32		shid	r6
0000001E 7F0B		bispsrd	r1
00000020 7C17		caseb	r2
00000022 7FA806		cxpd	@6
00000025 021F		jsr	@rout1
00000027 BEB529		absf	f5,f6
0000002A EE0538		movusw	r7,r0
0000002D 3E40A101		movbl	1,f5
00000031 CE440003		cmpmb	r0,r1,4
00000035 CE4F0800		extsd	r1,r1,0,1
00000039 62A0		save	[ r5, r7 ]
0000003B 1E0B00		lmr	bpr0,r0
0000003E 0E8C04		skpst	w
00000041 CC0042		acbb	1,r0,label
00000044 B2		rout1:	wait
00000045 7F950C0B		adjspd	11(12(sb))
00000049 7CA50D		adjspb	13
0000004C 7DB50102		adjspw	external(1)+2
00000050 7FBD		adjspd	tos
00000052 7CED860807		adjspb	7(8(fp))[r6:w]

SEE ALSO
uni_ass(VI)
NS 16000 Programmers Reference Manual. Publ. no. 420306565-001PB
NS16032S-6, NS16032S-4 High Performance Microprocessors, november 1982
publ. no. 420306619-002A.

AUTHOR
Ed Keizer, Vrije Universiteit