1984-12-14 15:41:14 +00:00
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.define .mlu
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1985-06-04 10:57:42 +00:00
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.sect .text
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.sect .rom
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.sect .data
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.sect .bss
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1984-12-14 15:41:14 +00:00
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1991-02-01 15:09:58 +00:00
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! unsigned long mulitply
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!-----------------------------------------------------------------------------
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! rewritten by Kai-Uwe Bloem (i5110401@dbstu1.bitnet) for speed.
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! #1 01/12/90 initial revision
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!-----------------------------------------------------------------------------
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! 3 cases worth to recognize :
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! 1) both the upper word of u and v are zero
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! => 1 mult : Low*Low
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! 2) only one of the upper words is zero
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! => 2 mult : Low*HighLow
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! 3) both upper words are not zero
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! => 4 mult : HighLow*HighLow
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! there are other cases (e.g. lower word is zero but high word is not, or
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! one operand is all zero). However, this seems not to be very common, so
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! they are ignored for the price of superfluous multiplications in these
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! cases.
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!-----------------------------------------------------------------------------
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1984-12-14 15:41:14 +00:00
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! entry : d0 multiplicand
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! d1 multiplier
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! exit : d0 high order result
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! d1 low order result
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1991-02-01 15:09:58 +00:00
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! d2,a0,a1 : destroyed
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1984-12-14 15:41:14 +00:00
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1985-06-04 10:57:42 +00:00
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.sect .text
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1984-12-14 15:41:14 +00:00
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.mlu:
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1991-02-01 15:09:58 +00:00
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move.l (sp)+,a1 ! return address
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move.l d3,a0 ! save register
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movem.w (sp)+,d0-d3 ! get v and u
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tst.w d0
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bne 1f ! case 2) or 3)
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tst.w d2
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bne 2f ! case 2)
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! === case 1: _l x _l ===
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mulu d3,d1 ! r.l = u.l x v.l
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move.l a0,d3 ! (r.h is already zero)
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jmp (a1) ! return
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! === possibly case 2) or case 3) ===
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1:
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tst.w d2
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bne 3f ! case 3)
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! === case 2: _l x hl ===
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exg d0,d2 ! exchange u and v
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exg d1,d3 ! (minimizes number of distinct cases)
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2:
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mulu d1,d2 ! a = v.l x u.h
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mulu d3,d1 ! r.l = v.l x u.l
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swap d2 ! a = a << 16
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clr.l d3
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move.w d2,d3
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clr.w d2
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add.l d2,d1 ! r += a
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addx.l d3,d0
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move.l a0,d3 ! return
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jmp (a1)
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! === case 3: hl x hl ===
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3:
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move.l d4,-(sp) ! need more registers
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move.w d2,d4
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mulu d1,d4 ! a = v.l x u.h
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mulu d3,d1 ! r.l = u.l x v.l
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mulu d0,d3 ! b = v.h x u.l
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mulu d2,d0 ! r.h = u.h x v.h
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swap d1 ! (just for simplicity)
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add.w d4,d1 ! r += a << 16
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clr.w d4
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swap d4
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addx.l d4,d0
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add.w d3,d1 ! r += b << 16
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clr.w d3
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1984-12-14 15:41:14 +00:00
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swap d3
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1991-02-01 15:09:58 +00:00
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addx.l d3,d0
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swap d1
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move.l (sp)+,d4 ! return
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move.l a0,d3
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1984-12-14 15:41:14 +00:00
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jmp (a1)
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