1984-12-14 15:41:14 +00:00
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.define .dvi
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1985-06-04 10:57:42 +00:00
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.sect .text
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.sect .rom
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.sect .data
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.sect .bss
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1984-12-14 15:41:14 +00:00
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! signed long divide
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1991-02-01 15:09:58 +00:00
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!-----------------------------------------------------------------------------
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! rewritten by Kai-Uwe Bloem (i5110401@dbstu1.bitnet) for speed.
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! #1 01/12/90 initial revision. Minor reduce of shift operations.
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! #2 03/07/90 use 68000 divu instruction whereever possible. This change
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! makes #1 superflous. (derived from my GNU division routine)
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!-----------------------------------------------------------------------------
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! Some common cases can be handled in a special, much faster way :
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! 1) divisor = 0
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! => cause trap, then return to user. Result is undefined
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! 2) dividend < divisor
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! => quotient = 0, remainder = dividend
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! 3) divisor < 0x10000 ( i.e. divisor is only 16 bits wide )
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! => quotient and remainder can be calculated quite fast by repeated
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! application of 68000 divu operations (ca. 400 cycles)
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! 4) otherwise (due to #2, #3 dividend, divisor both wider then 16 bits)
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! => do slow division by shift and subtract
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!-----------------------------------------------------------------------------
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! register usage:
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! : d0 divisor
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! d1 dividend
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! exit : d1 quotient
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! d2 remainder
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1985-06-04 10:57:42 +00:00
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.sect .text
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1984-12-14 15:41:14 +00:00
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.dvi:
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1991-02-01 15:09:58 +00:00
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move.l (sp)+,a1 ! return address
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move.l (sp)+,d0 ! divisor
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move.l (sp)+,d2 ! dividend
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move.l d3,a0 ! save d3
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move.l d4,-(sp) ! save result sign register
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1984-12-14 15:41:14 +00:00
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clr.l d4
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1991-02-01 15:09:58 +00:00
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tst.l d2
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bpl 0f ! dividend is negative ?
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neg.l d2 ! yes - negate
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not.l d4 ! and note negation in d4
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0:
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tst.l d0
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bpl 0f ! divisor is negative ?
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neg.l d0 ! yes - negate
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not.w d4 ! note negation
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0:
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clr.l d1 ! prepare quotient
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! === case 1: divisor = 0
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tst.l d0 ! divisor = 0 ?
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beq 9f ! yes - divide by zero trap
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! === case 2: dividend < divisor
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cmp.l d0,d2 ! dividend < divisor ?
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bcs 8f ! yes - division already finished
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! === case 3: divisor <= 0x0ffff
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cmp.l #0x0ffff,d0 ! is divisor only 16 bits wide ?
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bhi 2f
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move.w d2,d3 ! save dividend.l
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clr.w d2 ! prepare dividend.h for divu operation
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swap d2
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beq 0f ! dividend.h is all zero, no divu necessary
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divu d0,d2
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0: move.w d2,d1 ! save quotient.h
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swap d1
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move.w d3,d2 ! divide dividend.l
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divu d0,d2 ! (d2.h = remainder of prev divu)
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move.w d2,d1 ! save qoutient.l
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clr.w d2 ! get remainder
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swap d2
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bra 8f
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! === case 4: divisor and dividend both > 0x0ffff
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1984-12-14 15:41:14 +00:00
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2:
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1991-02-01 15:09:58 +00:00
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move #32-1,d3 ! loop count
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4:
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lsl.l #1,d2 ! shift dividend ...
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roxl.l #1,d1 ! ... into d1
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cmp.l d0,d1 ! compare with divisor
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bcs 5f
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sub.l d0,d1 ! bigger, subtract divisor
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add #1,d2 ! note subtraction in result
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1984-12-14 15:41:14 +00:00
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5:
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1991-02-01 15:09:58 +00:00
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dbra d3,4b
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exg d1,d2 ! get results in the correct registers
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8:
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tst.w d4 ! quotient < 0 ?
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bpl 0f
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neg.l d1 ! yes - negate
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0: tst.l d4 ! remainder < 0 ?
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bpl 0f
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neg.l d2
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0: move.l (sp)+,d4 ! restore d4
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move.l a0,d3 ! restore d3
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jmp (a1)
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EIDIVZ = 6
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9: move.w #EIDIVZ,-(sp)
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jsr .trp
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