1990-11-12 15:36:03 +00:00
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/****************************************************************************
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* ACK backend for Acorn Risc Machine *
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* First version: A.N.Other, Vrije Universiteit, Amsterdam *
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* Completed by: Albert Koelmans, University of Newcastle *
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* Register variables by Jonathan Hardwick *
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* With help from: Andy Michael and Ceriel Jacobs *
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****************************************************************************/
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#define legal(a) ((a&~0xFF)==0||(a&~0x3FC)==0||(a&~0xFF0)==0||\
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(a&~0x3FC0)==0||(a&~0xFF00)==0||(a&~0x3FC00)==0||\
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(a&~0xFF000)==0||(a&~0x3FC000)==0||(a&~0xFF0000)==0||\
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(a&~0x3FC0000)==0||(a&~0xFF00000)==0||(a&~0x3FC00000)==0||\
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(a&~0xFF000000)==0||(a&~0xFC000003)==0||(a&~0xF000000F)==0||\
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(a&~0xC000003F)==0||(~a&~0xFF)==0)
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#define neglegal(a) (((0-a)&~0xFF)==0||((0-a)&~0x3FC)==0||((0-a)&~0xFF0)==0||\
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((0-a)&~0x3FC0)==0||((0-a)&~0xFF00)==0||((0-a)&~0x3FC00)==0||\
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((0-a)&~0xFF000)==0||((0-a)&~0x3FC000)==0||((0-a)&~0xFF0000)==0||\
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((0-a)&~0x3FC0000)==0||((0-a)&~0xFF00000)==0||((0-a)&~0x3FC00000)==0||\
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((0-a)&~0xFF000000)==0||((0-a)&~0xFC000003)==0||((0-a)&~0xF000000F)==0||\
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((0-a)&~0xC000003F)==0||(~(0-a)&~0xFF)==0)
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#define illegal(a) !legal(a)
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1990-11-13 14:52:51 +00:00
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#define minlegal(a) (a < 0) && neglegal(a)
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#define minillegal(a) (a < 0) && !neglegal(a)
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1990-11-12 15:36:03 +00:00
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1988-02-17 15:44:54 +00:00
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EM_WSIZE=4
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EM_PSIZE=4
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EM_BSIZE=8
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PROPERTIES
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GENREG /* All 16 user registers */
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REG /* Allocatable registers */
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PCPSR /* PSW and PC */
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SREG
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STACKPOINTER
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LOCALBASE
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LINKREGISTER
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REGISTERS
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1990-11-12 15:36:03 +00:00
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R0,R1,R2,R3,R8,R9,R10 :GENREG, REG .
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R4,R5,R6,R7 :GENREG regvar(reg_any).
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1988-02-17 15:44:54 +00:00
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R11 :GENREG, SREG .
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1990-11-12 15:36:03 +00:00
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SP("R12") :STACKPOINTER .
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LB("R13") :LOCALBASE .
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LR("R14") :LINKREGISTER .
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PC("R15") :PCPSR .
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1988-02-17 15:44:54 +00:00
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TOKENS
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1990-11-12 15:36:03 +00:00
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const4 = { INT num; } 4 cost(0,4) "#" num .
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fitcon = { INT num; } 4 cost(0,4) "#" num .
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lb_local = { INT ind; } 4 "[R13,#" ind "]" .
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1988-02-17 15:44:54 +00:00
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addr_local = { INT ind; } 4 .
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1990-11-12 15:36:03 +00:00
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naddr_local = { INT ind; } 4 .
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1988-02-17 15:44:54 +00:00
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absolute = { ADDR add; } 4 add .
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1990-11-12 15:36:03 +00:00
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addr_external = { ADDR add; } 4 add .
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label = { ADDR add; } 4 add .
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autoid = { STACKPOINTER reg; } 4 reg "<" .
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regexp = { INT exp;} 4 exp .
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register = { GENREG exp;} 4 exp .
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imS = { GENREG reg; ADDR S; INT shift;} 4
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reg "," S "#" shift .
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regS = { GENREG reg; ADDR S; GENREG sreg;} 4
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reg "," S " "sreg .
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regind = { GENREG reg; } 4
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"[" reg "]" .
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REGrel = { REG reg; ADDR ind; } 4
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"[" reg ",#" ind "]" .
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regrel = { GENREG reg; ADDR ind; } 4
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"[" reg ",#" ind "]" .
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st_regrel = { STACKPOINTER reg; ADDR ind; } 4
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"[" reg ",#" ind "]" .
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lb_regrel = { LOCALBASE reg; ADDR ind; } 4
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"[" reg ",#" ind "]" .
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regregrel = { GENREG reg1; GENREG reg2; } 4
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"[" reg1 "," reg2 "]" .
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st_regregrel = { STACKPOINTER reg1; GENREG reg2; } 4
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"[" reg1 "," reg2 "]" .
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lb_regregrel = { LOCALBASE reg1; GENREG reg2; } 4
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"[" reg1 "," reg2 "]" .
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regminregrel = { GENREG reg1; GENREG reg2; } 4
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"[" reg1 ",-" reg2 "]" .
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regiSregrel = { GENREG reg1; ADDR S; INT shift; GENREG reg2; } 4
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"[" reg1 "," reg2 "," S "#" shift "]" .
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st_regiSregrel = { STACKPOINTER reg1; ADDR S; INT shift; GENREG reg2; } 4
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1988-02-17 15:44:54 +00:00
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"[" reg1 "," reg2 "," S "#" shift "]" .
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1990-11-12 15:36:03 +00:00
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regminiSregrel = { GENREG reg1; ADDR S; INT shift; GENREG reg2; } 4
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1988-02-17 15:44:54 +00:00
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"[" reg1 ",-" reg2 "," S "#" shift "]" .
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1990-11-12 15:36:03 +00:00
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regminrSregrel = { GENREG reg1; ADDR S; GENREG sreg; GENREG reg2; } 4
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"[" reg1 ",-" reg2 "," S " " sreg "]" .
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regrelpi = { GENREG reg; ADDR ind; } 4
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"[" reg "],#" ind .
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regconst = { GENREG reg; INT ind; } 4
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reg ",#" ind .
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regplusreg = {GENREG reg1; GENREG reg2;} 4
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reg1 "," reg2 .
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regplusiSreg = {GENREG reg1; ADDR S; INT shift; GENREG reg2;} 4
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reg1 "," reg2 "," S "#" shift .
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regplusrSreg = {GENREG reg1; ADDR S; GENREG sreg; GENREG reg2;} 4
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reg1 "," reg2 "," S "," sreg .
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regminreg = {GENREG reg1; GENREG reg2;} 4
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reg1 "," reg2 .
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regminiSreg = {GENREG reg1; ADDR S; INT shift; GENREG reg2;} 4
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reg1 "," reg2 "," S "#" shift .
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regminrSreg = {GENREG reg1; ADDR S; GENREG sreg; GENREG reg2;} 4
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reg1 "," reg2 "," S "," sreg .
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REGlist1 = {REG reg1; } 4
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"{" reg1 "}" .
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reglist1 = {GENREG reg1; } 4
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"{" reg1 "}" .
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lb_reglist1 = {LOCALBASE reg1; } 4
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"{" reg1 "}" .
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sp_reglist1 = {STACKPOINTER reg1; } 4
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"{" reg1 "}" .
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reglist2 = {GENREG reg1; GENREG reg2; } 8
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"{" reg1 "," reg2 "}" .
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lb_pc_reglist2 = {LOCALBASE reg1; PCPSR reg2; } 8
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"{" reg1 "," reg2 "}" .
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reglist3 = {GENREG reg1; GENREG reg2; GENREG reg3; } 12
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"{" reg1 "," reg2 "," reg3 "}" .
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reglist4 = {GENREG reg1; GENREG reg2; GENREG reg3; GENREG reg4; } 16
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"{" reg1 "," reg2 "," reg3 "," reg4 "}" .
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/* the next 5 are not currently used - perhaps later */
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regrelwb = { GENREG reg; ADDR ind; } 4 "[" reg ",#" ind "]<" .
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1988-02-17 15:44:54 +00:00
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regregrelwb = { GENREG reg1; GENREG reg2; } 4 "[" reg1 "," reg2 "]<" .
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1990-11-12 15:36:03 +00:00
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regiSregrelwb = { GENREG reg1; ADDR S; INT shift; GENREG reg2; } 4
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1988-02-17 15:44:54 +00:00
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"[" reg1 "," reg2 "," S "#" shift "]<" .
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1990-11-12 15:36:03 +00:00
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regrSregrelwb = { GENREG reg1; ADDR S; GENREG sreg; GENREG reg2; } 4
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"[" reg1 "," reg2 "," S " " sreg "]<" .
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1988-02-17 15:44:54 +00:00
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regregrelpi = { GENREG reg1; GENREG reg2; } 4 "[" reg1 "]," reg2 .
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1990-11-12 15:36:03 +00:00
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LOCAL = { INT ind;} 4 ">>> BUG IN LOCAL".
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stack = { GENREG r;} 4 "R12<,{" r "}".
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1988-02-17 15:44:54 +00:00
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1990-11-12 15:36:03 +00:00
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/* tokens to put shifts and rotates into opcodes */
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reglslcon = {GENREG target; INT shift;} 4 target ",LSL#" shift.
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reglsrcon = {GENREG target; INT shift;} 4 target ",LSR#" shift.
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regasrcon = {GENREG target; INT shift;} 4 target ",ASR#" shift.
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regrorcon = {GENREG target; INT shift;} 4 target ",ROR#" shift.
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reglslreg = {GENREG target; GENREG shift;} 4 cost(0,1) target ",LSL " shift.
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reglsrreg = {GENREG target; GENREG shift;} 4 cost(0,1) target ",LSR " shift.
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regasrreg = {GENREG target; GENREG shift;} 4 cost(0,1) target ",ASR " shift.
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regrorreg = {GENREG target; GENREG shift;} 4 cost(0,1) target ",ROR " shift.
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regrorregr = {GENREG target; GENREG shift;} 4 cost(0,1) target ",ROR " shift.
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1988-02-17 15:44:54 +00:00
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SETS
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address = absolute + regind + regrel + regrelwb + regregrel +
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1990-11-12 15:36:03 +00:00
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st_regrel + st_regregrel + st_regiSregrel +
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lb_regrel + lb_regregrel +
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regiSregrel + regiSregrelwb + regrSregrelwb +
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1988-02-17 15:44:54 +00:00
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regminregrel + regminiSregrel + regminrSregrel +
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1990-11-12 15:36:03 +00:00
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regregrelwb + regrelpi + regregrelpi + lb_local .
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1988-02-17 15:44:54 +00:00
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REGcon = GENREG + imS + regS + fitcon .
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1990-11-12 15:36:03 +00:00
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reglist = reglist1 + reglist2 + reglist3 + reglist4 +
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lb_reglist1 + sp_reglist1 + lb_pc_reglist2 +
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regexp + REGlist1 .
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constant = fitcon + const4 .
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local = lb_local + LOCAL.
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regshift = reglslreg + reglsrreg + regasrreg + regrorreg + regrorregr +
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reglslcon + reglsrcon + regasrcon + regrorcon.
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rhs = GENREG + constant + regshift + LOCAL.
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mem4 = regregrel + regrel + lb_local.
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extern = addr_external + absolute + label.
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all_except_con = mem4 + extern + local.
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any_data = all_except_con + rhs.
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any_data_except_local = any_data - LOCAL.
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posshifts = regplusiSreg+regplusrSreg.
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negshifts = regminiSreg+regminrSreg.
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shifts = posshifts+negshifts.
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1988-02-17 15:44:54 +00:00
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INSTRUCTIONS
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1990-11-12 15:36:03 +00:00
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BAL label cost(4,4) .
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BAL_L "BAL.L" label cost(4,4) .
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BAL_LEQ "BAL.L.EQ" label cost(4,4) .
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BNV label cost(4,4) .
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BNE label cost(4,4) .
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BEQ label cost(4,4) .
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BMI label cost(4,4) .
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BGT label cost(4,4) .
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BLT label cost(4,4) .
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BLE label cost(4,4) .
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BGE label cost(4,4) .
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LDR REG+LOCALBASE+GENREG+address:wo, address:rw cost(4,4) .
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LDR LOCAL+GENREG:rw,
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mem4+absolute+addr_external:ro cost(4,4) .
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STR GENREG+REG:ro, REGrel+address:rw cost(4,4) .
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LDR_B "LDR.B" REG+GENREG:wo, address:rw cost(4,4) .
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LDR_B LOCAL:rw, rhs+mem4:ro cost(4,4) .
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STR_B "STR.B" GENREG+REG:ro, address:rw cost(4,4) .
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LDMFD autoid:rw, reglist:wo cost(4,7) .
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STMFD autoid:rw, reglist:ro cost(4,7) .
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STMFD stack cost(4,4) .
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LDMIA GENREG:rw, reglist:wo cost(4,7) .
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ADC REG+GENREG:wo, REG+GENREG:ro, REGcon:ro cost(4,1) .
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ADD GENREG+REG:wo, GENREG:ro, REGcon+const4:ro cost(4,1) .
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ADD GENREG+STACKPOINTER:wo, GENREG+STACKPOINTER:ro,
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STACKPOINTER+REGcon+const4:ro cost(4,1) .
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ADD LOCAL+GENREG+REG:wo,
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regconst+shifts+regminreg+regplusreg:ro cost(4,1) .
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ADD LOCAL+GENREG:rw, LOCALBASE+GENREG+LOCAL:ro,
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rhs:ro cost(4,1).
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ADD_NE "ADD.NE" GENREG+REG:wo, GENREG:ro, REGcon+const4:ro cost(4,1) .
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AND REG+GENREG:wo, GENREG:ro, GENREG+REGcon:ro cost(4,1) .
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AND_S "AND.S" GENREG+REG:wo, GENREG:ro, REGcon:ro cost(4,1) .
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BIC REG+GENREG:wo, GENREG:ro, REGcon:ro cost(4,1) .
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CMN GENREG+REG:ro, REGcon:ro kills :cc cost(4,1) .
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CMP REG+GENREG:ro, REGcon:ro kills :cc cost(4,1) .
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EOR GENREG+REG:wo, GENREG:ro, GENREG+REGcon:ro cost(4,1) .
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EOR_S "EOR.S" REG+GENREG:wo:cc, GENREG:ro, REGcon:ro cost(4,1) .
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MOV REG:wo, REGcon+const4:ro cost(4,1) .
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MOV REG:rw, LOCAL:ro cost(4,1).
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MOV LOCALBASE+PCPSR+STACKPOINTER+GENREG:rw,
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REGcon+address+LOCALBASE+PCPSR+
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STACKPOINTER+GENREG+LOCAL:ro cost(4,1).
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MOV LOCAL+GENREG:rw, GENREG+rhs+register+REG:ro cost(4,1).
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MOV LOCALBASE+GENREG:wo, REGcon+const4:ro cost(4,1) .
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MOV_MI "MOV.MI" REG+GENREG:wo, REGcon+const4:ro cost(4,1) .
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MOV_HI "MOV.HI" GENREG+REG:wo, REGcon+const4:ro cost(4,1) .
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MOV_LS "MOV.LS" REG+GENREG:wo, REGcon+const4:ro cost(4,1) .
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MOV_LT "MOV.LT" GENREG+REG:wo, REGcon+const4:ro cost(4,1) .
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MOV_LE "MOV.LE" REG+GENREG:wo, REGcon+const4:ro cost(4,1) .
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MOV_EQ "MOV.EQ" GENREG+REG:wo, REGcon+const4:ro cost(4,1) .
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MOV_NE "MOV.NE" REG+GENREG:wo, REGcon+const4:ro cost(4,1) .
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MOV_GE "MOV.GE" REG+GENREG:wo, REGcon+const4:ro cost(4,1) .
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MOV_GT "MOV.GT" REG+GENREG:wo, REGcon+const4:ro cost(4,1) .
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MOV_NV "MOV.NV" GENREG+REG:wo, REGcon+const4:ro cost(4,1) .
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MOV_S "MOV.S" GENREG+REG:wo, REGcon+const4+regind:ro
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kills :cc cost(4,1) .
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MVN LOCAL+GENREG+REG:wo, REGcon:ro cost(4,1) .
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ORR REG+GENREG:wo, GENREG:ro, GENREG+REGcon:ro cost(4,1) .
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ORR REG+GENREG+LOCAL:wo, imS:ro cost(4,1) .
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RSB REG+GENREG+LOCAL:rw, REG+GENREG+LOCAL:ro,
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rhs:ro cost(4,1).
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RSB GENREG+REG:wo, GENREG:ro, REGcon:ro cost(4,1) .
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RSB_S "RSB.S" REG+GENREG:wo:cc, GENREG:ro, REGcon:ro cost(4,1) .
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RSC GENREG+REG:wo, GENREG:ro, REGcon:ro cost(4,1) .
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SBC REG+GENREG:wo, GENREG:ro, REGcon:ro cost(4,1) .
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SUB LOCAL+GENREG:rw,
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regconst+shifts+regplusreg+regminreg:ro cost(4,1).
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SUB LOCAL:rw, LOCAL:ro, rhs:ro cost(4,1).
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SUB LOCAL+REG+GENREG:wo, LOCALBASE+GENREG:ro,
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constant+REGcon:ro cost(4,1) .
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SUB_S "SUB.S" REG+GENREG:wo:cc, GENREG:ro, REGcon:ro cost(4,1) .
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TEQ GENREG+REG:ro, REGcon:ro kills :cc cost(4,1) .
|
|
|
|
TST REG+GENREG:ro, REGcon:ro kills :cc cost(4,1) .
|
|
|
|
ADR REG+LINKREGISTER+GENREG:wo,
|
|
|
|
addr_external+label:ro cost(4,1) .
|
|
|
|
LABEL "" label kills :cc cost(4,1) .
|
|
|
|
|
|
|
|
/* Dummy instructions for ncgg procedures : lxx is logical operator, */
|
|
|
|
/* mxx is conditional move, bxx is conditional branch, rxx is arith- */
|
|
|
|
/* metical operator on register variable (LOCAL). */
|
|
|
|
|
|
|
|
lxx "lxx : bug in cg" REG:rw, REG:ro, rhs:ro cost(4,1).
|
|
|
|
mxx "mxx : bug in cg" REG:rw, rhs:ro cost(4,1).
|
|
|
|
bxx "bxx : bug in cg" addr_external cost(4,4).
|
|
|
|
rxx "rxx : bug in cg" LOCAL:rw, LOCAL:ro, rhs:ro cost(4,1).
|
|
|
|
rrx "rrx : bug in cg" LOCAL:rw, LOCAL:ro, LOCAL:ro cost(4,1).
|
|
|
|
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
MOVES
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
from GENREG+STACKPOINTER+LOCALBASE+PCPSR to
|
|
|
|
GENREG+STACKPOINTER+LOCALBASE+PCPSR
|
|
|
|
gen MOV %2, %1
|
|
|
|
|
|
|
|
from fitcon+GENREG+REG to LOCAL inreg(%ind)==reg_any
|
|
|
|
gen MOV %2, %1
|
|
|
|
|
|
|
|
from LOCAL inreg(%ind)==reg_any to REG+GENREG
|
|
|
|
gen MOV %2, %1
|
|
|
|
|
|
|
|
/* illegal immediate operands */
|
|
|
|
|
|
|
|
from const4 minlegal(%num+1) to GENREG+LOCAL
|
|
|
|
gen MVN %2, {fitcon, 0-%1.num-1}
|
|
|
|
|
|
|
|
from const4 (minlegal(%num)) to GENREG+LOCAL
|
|
|
|
gen MOV %2, {fitcon, 0-%1.num}
|
|
|
|
RSB %2, %2, {fitcon, 0}
|
|
|
|
|
|
|
|
from const4 to GENREG+LOCAL /* general case */
|
|
|
|
gen MOV %2, { fitcon, %1.num & 0xFF}
|
|
|
|
ADD %2, %2, { fitcon, %1.num & 0xFF00}
|
|
|
|
ADD %2, %2, { fitcon, %1.num & 0xFF0000}
|
|
|
|
ADD %2, %2, { fitcon, %1.num & 0xFF000000}
|
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from regconst (%ind > 0) && legal(%ind) to LOCAL inreg(%ind)==reg_any
|
1990-11-12 15:36:03 +00:00
|
|
|
gen ADD %2, %1
|
|
|
|
|
|
|
|
from regconst minlegal(%ind) to LOCAL inreg(%ind)==reg_any
|
|
|
|
gen SUB %2, %1.reg, {fitcon, 0-%1.ind}
|
|
|
|
|
|
|
|
from lb_local legal(%ind) to GENREG
|
|
|
|
gen LDR %2, {lb_regrel, LB, %1.ind}
|
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from lb_local to GENREG
|
|
|
|
gen move {const4, %1.ind}, R11
|
|
|
|
LDR %2, {lb_regregrel, LB, R11}
|
1990-11-12 15:36:03 +00:00
|
|
|
|
|
|
|
from GENREG to lb_local legal(%ind)
|
|
|
|
gen STR %1, {lb_regrel, LB, %2.ind}
|
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from GENREG to lb_local
|
|
|
|
gen move {const4, %2.ind}, R11
|
|
|
|
STR %1, {lb_regregrel, LB, R11}
|
|
|
|
|
1988-02-17 15:44:54 +00:00
|
|
|
from GENREG to address
|
|
|
|
gen STR %1, %2
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
from address to GENREG+LOCALBASE
|
1988-02-17 15:44:54 +00:00
|
|
|
gen LDR %2, %1
|
|
|
|
|
|
|
|
from GENREG to autoid
|
|
|
|
gen STMFD %2, {reglist1, %1}
|
|
|
|
|
|
|
|
from autoid to GENREG
|
|
|
|
gen LDMFD %1, {reglist1, %2}
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
from REGcon to GENREG+LOCALBASE
|
1988-02-17 15:44:54 +00:00
|
|
|
gen MOV %2, %1
|
|
|
|
|
|
|
|
|
|
|
|
from addr_external to GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
gen ADR %2, %1
|
|
|
|
|
|
|
|
/* strictly speaking, the following move is impossible.
|
|
|
|
* what it really means is: move from reg to address!
|
|
|
|
*/
|
|
|
|
from GENREG to addr_external
|
|
|
|
gen ADR R11,%2
|
|
|
|
STR %1,{regind,R11}
|
|
|
|
|
|
|
|
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
TESTS
|
|
|
|
|
|
|
|
to test GENREG
|
|
|
|
gen CMP %1, {fitcon, 0}
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
|
1988-02-17 15:44:54 +00:00
|
|
|
STACKINGRULES
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
from LOCAL to STACK
|
|
|
|
gen STMFD {stack, regvar(%1.ind)}
|
|
|
|
|
|
|
|
from REG to STACK
|
|
|
|
gen STMFD {autoid, SP}, {REGlist1, %1}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
from GENREG to STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
gen STMFD {autoid, SP}, {reglist1, %1}
|
|
|
|
|
|
|
|
from LOCALBASE to STACK
|
|
|
|
gen STMFD {autoid, SP}, {lb_reglist1, %1}
|
|
|
|
|
|
|
|
from STACKPOINTER to STACK
|
|
|
|
gen STMFD {autoid, SP}, {sp_reglist1, %1}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
from REGcon to STACK
|
|
|
|
gen move %1, R11
|
1990-11-12 15:36:03 +00:00
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
from const4 to STACK
|
|
|
|
gen move %1, R11
|
1990-11-12 15:36:03 +00:00
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from addr_local legal(%ind) to STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
gen ADD R11, LB, {fitcon, %1.ind}
|
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
from addr_local to STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
gen move {const4, %1.ind}, R11
|
|
|
|
ADD R11, LB, R11
|
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from naddr_local legal(%ind) to STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
gen SUB R11, LB, {fitcon, %1.ind}
|
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
|
|
|
|
|
|
|
from naddr_local to STACK
|
|
|
|
gen move {const4, %1.ind}, R11
|
|
|
|
SUB R11, LB, R11
|
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
|
|
|
|
1988-02-17 15:44:54 +00:00
|
|
|
from addr_external to STACK
|
|
|
|
gen ADR R11, %1
|
1990-11-12 15:36:03 +00:00
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from regconst (%ind > 0) && legal(%ind) to STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
gen ADD R11, %1.reg, {fitcon,%1.ind}
|
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
from regconst to STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
gen move {const4, %1.ind}, R11
|
|
|
|
ADD R11, R11, %1.reg
|
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
from regplusreg to STACK
|
|
|
|
gen ADD R11, %1.reg1, %1.reg2
|
1990-11-12 15:36:03 +00:00
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
from regminreg to STACK
|
|
|
|
gen SUB R11, %1.reg1, %1.reg2
|
1990-11-12 15:36:03 +00:00
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
from regplusiSreg to STACK
|
|
|
|
gen ADD R11, %1.reg1, {imS, %1.reg2, %1.S, %1.shift}
|
1990-11-12 15:36:03 +00:00
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
from regminiSreg to STACK
|
|
|
|
gen SUB R11, %1.reg1, {imS, %1.reg2, %1.S, %1.shift}
|
1990-11-12 15:36:03 +00:00
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
from regplusrSreg to STACK
|
|
|
|
gen ADD R11, %1.reg1, {regS, %1.reg2, %1.S, %1.sreg}
|
1990-11-12 15:36:03 +00:00
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
from regminrSreg to STACK
|
|
|
|
gen SUB R11, %1.reg1, {regS, %1.reg2, %1.S, %1.sreg}
|
1990-11-12 15:36:03 +00:00
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
|
|
|
|
|
|
|
from address to STACK
|
|
|
|
gen move %1, R11
|
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
COERCIONS
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
from LOCAL
|
|
|
|
uses GENREG
|
|
|
|
gen MOV %a, %1 yields %a
|
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from lb_local legal(%ind)
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
|
|
|
gen LDR %a, {lb_regrel, LB, %ind} yields %a
|
1990-11-12 15:36:03 +00:00
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from lb_local
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
|
|
|
gen move {const4, %ind}, R11
|
|
|
|
LDR %a, {lb_regregrel, LB, R11} yields %a
|
1990-11-12 15:36:03 +00:00
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from const4 %num < 0
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
|
|
|
gen move {const4, 0-%num}, %a
|
1990-11-12 15:36:03 +00:00
|
|
|
RSB %a, %a, {fitcon, 0} yields %a
|
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from const4 illegal(%num)
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
gen move %1, %a yields %a
|
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from const4 yields {fitcon, %num}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
from STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen LDMFD {autoid, SP}, {reglist1, %a} yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
from address
|
|
|
|
uses GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
gen move %1, %a yields %a
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
from REGcon
|
|
|
|
uses GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
gen move %1, %a yields %a
|
1990-11-12 15:36:03 +00:00
|
|
|
|
1988-02-17 15:44:54 +00:00
|
|
|
from addr_external
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
gen move %1, %a
|
|
|
|
yields %a
|
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from addr_local legal(%ind)
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
|
|
|
gen ADD %a, LB, {fitcon, %ind} yields %a
|
1990-11-12 15:36:03 +00:00
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from addr_local
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
|
|
|
gen move {const4, %ind}, %a
|
1990-11-12 15:36:03 +00:00
|
|
|
ADD %a, LB, %a yields %a
|
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from naddr_local legal(%ind)
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
|
|
|
gen SUB %a, LB, {fitcon, %ind} yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from naddr_local
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
|
|
|
gen move {const4, %ind}, %a
|
1990-11-12 15:36:03 +00:00
|
|
|
SUB %a, LB, %a yields %a
|
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from regconst (%ind > 0) && legal(%ind)
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
gen ADD %a, %1 yields %a
|
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from regconst minlegal(%ind)
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
|
|
|
gen SUB %a, %reg, {fitcon, 0-%ind} yields %a
|
1990-11-12 15:36:03 +00:00
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from regconst minillegal(%ind)
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
|
|
|
gen move {const4, 0-%ind}, %a
|
|
|
|
SUB %a, %a, %reg yields %a
|
1990-11-12 15:36:03 +00:00
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
from regconst
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
|
|
|
gen move {const4, %ind}, %a
|
|
|
|
ADD %a, %a, %reg yields %a
|
1990-11-12 15:36:03 +00:00
|
|
|
|
|
|
|
from regplusreg
|
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
|
|
|
gen ADD %a, %reg1, %reg2
|
1988-02-17 15:44:54 +00:00
|
|
|
yields %a
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
from regminreg
|
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
|
|
|
gen SUB %a, %reg1, %reg2
|
1988-02-17 15:44:54 +00:00
|
|
|
yields %a
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
from regplusiSreg
|
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
|
|
|
gen ADD %a, %reg1, {imS, %reg2, %S, %shift}
|
1988-02-17 15:44:54 +00:00
|
|
|
yields %a
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
from regminiSreg
|
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
|
|
|
gen SUB %a, %reg1, {imS, %reg2, %S, %shift}
|
1988-02-17 15:44:54 +00:00
|
|
|
yields %a
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
from regplusrSreg
|
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
|
|
|
gen ADD %a, %reg1, {regS, %reg2, %S, %sreg}
|
1988-02-17 15:44:54 +00:00
|
|
|
yields %a
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
from regminrSreg
|
|
|
|
uses GENREG
|
1990-11-13 14:52:51 +00:00
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gen SUB %a, %reg1, {regS, %reg2, %S, %sreg}
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1988-02-17 15:44:54 +00:00
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yields %a
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PATTERNS
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1990-11-12 15:36:03 +00:00
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/************************************************************************
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* *
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* GROUP 0 : Register variables *
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* *
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************************************************************************/
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/* Simple load and store */
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pat lol inreg($1)==reg_any
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yields {LOCAL, $1}
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pat lil inreg($1)==reg_any
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yields {regind, regvar($1)}
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pat stl inreg($1)==reg_any
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with exact const4
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kills local %ind==$1
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gen move %1, {LOCAL, $1}
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with exact fitcon
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kills local %ind==$1
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gen MOV {LOCAL, $1}, %1
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with rhs-constant
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kills local %ind==$1
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gen MOV {LOCAL, $1}, %1
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with mem4+absolute
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kills local %ind==$1
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gen LDR {LOCAL, $1}, %1
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with regminreg
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kills local %ind == $1
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gen SUB {LOCAL, $1}, %1
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with regplusreg+posshifts
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kills local %ind == $1
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gen ADD {LOCAL, $1}, %1
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with negshifts
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kills local %ind == $1
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gen SUB {LOCAL, $1}, %1
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pat stl $1==1 && inreg($1)==reg_any
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with rhs
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kills local %ind==$1
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gen LDR_B {LOCAL, $1}, %1
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pat sil inreg($1)==reg_any
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with GENREG
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kills /*all_except_con*/ address
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gen move %1, {regind, regvar($1)}
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/* Increment, decrement, zero */
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pat inl inreg($1)==reg_any
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kills local %ind==$1
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gen ADD {LOCAL, $1}, {LOCAL, $1}, {fitcon, 1}
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pat del inreg($1)==reg_any
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kills local %ind==$1
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gen SUB {LOCAL, $1}, {LOCAL, $1}, {fitcon, 1}
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pat zrl inreg($1)==reg_any
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kills local %ind==$1
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gen MOV {LOCAL, $1}, {fitcon, 0}
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pat lol inc stl inreg($1)==reg_any && inreg($3)==reg_any
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kills local %ind==$3
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gen ADD {LOCAL, $3}, {LOCAL, $1}, {fitcon, 1}
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pat lol dec stl inreg($1)==reg_any && inreg($3)==reg_any
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kills local %ind==$3
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gen SUB {LOCAL, $3}, {LOCAL, $1}, {fitcon, 1}
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pat lol ngi stl inreg($1)==reg_any && inreg($3)==reg_any
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kills local %ind==$3
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gen RSB {LOCAL, $3}, {LOCAL, $1}, {fitcon, 0}
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/* Procedure : load register, op xx, store register */
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proc lol_op_stl example lol adi stl
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with rhs
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kills local %ind==$3
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gen rxx* {LOCAL, $3}, {LOCAL, $1}, %1
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pat lol adi stl inreg($1)==reg_any && inreg($3)==reg_any && $2==4
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call lol_op_stl("ADD")
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pat lol adu stl leaving lol $1 adi $2 stl $3
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pat lol sbi stl inreg($1)==reg_any && inreg($3)==reg_any && $2==4
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call lol_op_stl("RSB")
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pat lol sbu stl leaving lol $1 sbi $2 stl $3
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pat lol and stl inreg($1)==reg_any && inreg($3)==reg_any && $2==4
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call lol_op_stl("AND")
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pat lol ior stl inreg($1)==reg_any && inreg($3)==reg_any && $2==4
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call lol_op_stl("ORR")
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pat lol xor stl inreg($1)==reg_any && inreg($3)==reg_any && $2==4
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call lol_op_stl("EOR")
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/* Procedure : load register, load constant, op xx, store register */
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proc lol_loc_op_stl example lol loc adi stl
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kills local %ind==$4
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gen rxx* {LOCAL, $4}, {LOCAL, $1}, {const4, $2}
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pat lol loc adi stl inreg($1)==reg_any && inreg($4)==reg_any && $3==4
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call lol_loc_op_stl("ADD")
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pat lol loc adu stl leaving lol $1 loc $2 adi $3 stl $4
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pat lol loc sbi stl inreg($1)==reg_any && inreg($4)==reg_any && $3==4
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call lol_loc_op_stl("SUB")
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pat lol loc sbu stl leaving lol $1 loc $2 sbi $3 stl $4
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pat lol loc and stl inreg($1)==reg_any && inreg($4)==reg_any && $3==4
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call lol_loc_op_stl("AND")
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pat lol loc ior stl inreg($1)==reg_any && inreg($4)==reg_any && $3==4
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call lol_loc_op_stl("ORR")
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pat lol loc xor stl inreg($1)==reg_any && inreg($4)==reg_any && $3==4
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call lol_loc_op_stl("EOR")
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/* Procedure : load register, load register, op xx, store register */
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proc lol_lol_op_stl example lol lol adi stl
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kills local %ind==$4
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gen rrx* {LOCAL, $4}, {LOCAL, $1}, {LOCAL, $2}
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pat lol lol adi stl inreg($1)==reg_any && inreg($2)==reg_any &&
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inreg($4)==reg_any && $3==4
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call lol_lol_op_stl("ADD")
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pat lol lol adu stl leaving lol $1 lol $2 adi $3 stl $4
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pat lol lol sbi stl inreg($1)==reg_any && inreg($2)==reg_any &&
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inreg($4)==reg_any && $3==4
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call lol_lol_op_stl("SUB")
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pat lol lol sbu stl leaving lol $1 lol $2 sbi $3 stl $4
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pat lol lol and stl inreg($1)==reg_any && inreg($2)==reg_any &&
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inreg($4)==reg_any && $3==4
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call lol_lol_op_stl("AND")
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pat lol lol ior stl inreg($1)==reg_any && inreg($2)==reg_any &&
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inreg($4)==reg_any && $3==4
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call lol_lol_op_stl("ORR")
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pat lol lol xor stl inreg($1)==reg_any && inreg($2)==reg_any &&
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inreg($4)==reg_any && $3==4
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call lol_lol_op_stl("EOR")
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/* Shifts */
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pat lol loc sli stl inreg($1)==reg_any && inreg($4)==reg_any && $3==4
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kills local %ind==$4
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gen MOV {LOCAL, $4}, {reglslcon, regvar($1), $2}
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pat lol loc slu stl leaving lol $1 loc $2 sli $3 stl $4
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pat lol loc sri stl inreg($1)==reg_any && inreg($4)==reg_any && $3==4
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kills local %ind==$4
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gen MOV {LOCAL, $4}, {regasrcon, regvar($1), $2}
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pat lol loc sru stl inreg($1)==reg_any && inreg($4)==reg_any && $3==4
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kills local %ind==$4
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gen MOV {LOCAL, $4}, {reglsrcon, regvar($1), $2}
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pat lol lol sli stl inreg($1)==reg_any && inreg($2)==reg_any &&
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inreg($4)==reg_any && $3==4
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kills local %ind==$4
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gen MOV {LOCAL, $4}, {reglslreg, regvar($1), regvar($2)}
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pat lol lol slu stl leaving lol $1 lol $2 sli $3 stl $4
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pat lol lol sri stl inreg($1)==reg_any && inreg($2)==reg_any &&
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inreg($4)==reg_any && $3==4
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kills local %ind==$4
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gen MOV {LOCAL, $4}, {regasrreg, regvar($1), regvar($2)}
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pat lol lol sru stl inreg($1)==reg_any && inreg($2)==reg_any &&
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inreg($4)==reg_any && $3==4
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kills local %ind==$4
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gen MOV {LOCAL, $4}, {reglsrreg, regvar($1), regvar($2)}
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/* Rotates */
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pat lol loc ror stl inreg($1)==reg_any && inreg($4)==reg_any && $3==4
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kills local %ind==$4
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gen MOV {LOCAL, $4}, {regrorcon, regvar($1), $2}
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pat lol lol ror stl inreg($1)==reg_any && inreg($2)==reg_any &&
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inreg($4)==reg_any && $3==4
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kills local %ind==$4
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gen MOV {LOCAL, $4}, {regrorreg, regvar($1), regvar($2)}
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pat lol loc rol stl inreg($1)==reg_any && inreg($4)==reg_any && $3==4
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kills local %ind==$4
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gen MOV {LOCAL, $4}, {regrorcon, regvar($1), 32-$2}
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pat lol lol ror stl inreg($1)==reg_any && inreg($2)==reg_any &&
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inreg($4)==reg_any && $3==4
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kills local %ind==$4
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gen RSB R11, {LOCAL, $2}, {fitcon, 32}
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MOV {LOCAL, $4}, {regrorregr, regvar($1), R11}
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/* code for *p++ and *p-- (integers) */
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pat lol lol adp stl loi $1==$2 && $2==$4 && $5==4 && inreg($1)==reg_any
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kills GENREG
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uses GENREG
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gen LDR %a, {regrelpi, regvar($1), $5} yields %a
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pat lol lol adp stl sti $1==$2 && $2==$4 && $5==4 && inreg($1)==reg_any
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with GENREG
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kills GENREG
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gen STR %1, {regrelpi, regvar($1), $5}
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/* code for *p++ and *p-- (bytes)*/
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pat lol lol adp stl loi $1==$2 && $2==$4 && $5==1 && inreg($1)==reg_any
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kills GENREG
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uses GENREG
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gen LDR_B %a, {regrelpi, regvar($1), $5} yields %a
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pat lol lol adp stl sti $1==$2 && $2==$4 && $5==1 && inreg($1)==reg_any
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with GENREG
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kills GENREG
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gen STR_B %1, {regrelpi, regvar($1), $5}
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/* code for *pp->p++ and *pp->p-- (integers) */
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pat lil lil adp sil loi $1==$2 && $2==$4 && $5==4 && inreg($1)==reg_any
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kills GENREG
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uses GENREG,GENREG
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gen LDR %a, {regind, regvar($1)}
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ADD %b, %a, {fitcon, $3}
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STR %b, {regind, regvar($1)}
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LDR %b, {regind, %a} yields %b
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pat lil lil adp sil sti $1==$2 && $2==$4 && $5==4 && inreg($1)==reg_any
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with GENREG
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kills GENREG
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uses GENREG,GENREG
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gen LDR %a, {regind, regvar($1)}
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ADD %b, %a, {fitcon, $3}
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STR %b, {regind, regvar($1)}
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STR %1, {regind, %a}
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/* code for *pp->p++ and *pp->p-- (bytes) */
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pat lil lil adp sil loi $1==$2 && $2==$4 && $5==1 && inreg($1)==reg_any
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kills GENREG
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uses GENREG,GENREG
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gen LDR %a, {regind, regvar($1)}
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ADD %b, %a, {fitcon, $3}
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STR %b, {regind, regvar($1)}
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LDR_B %b, {regind, %a} yields %b
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pat lil lil adp sil sti $1==$2 && $2==$4 && $5==1 && inreg($1)==reg_any
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with GENREG
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kills GENREG
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uses GENREG,GENREG
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gen LDR %a, {regind, regvar($1)}
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ADD %b, %a, {fitcon, $3}
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STR %b, {regind, regvar($1)}
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STR_B %1, {regind, %a}
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1988-02-17 15:44:54 +00:00
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/************************************************************************
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* *
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* GROUP I : Load Instructions *
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* *
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************************************************************************/
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1990-11-12 15:36:03 +00:00
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pat loc $1 < 0 yields {const4, $1}
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pat loc legal($1) yields {fitcon, $1}
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1988-02-17 15:44:54 +00:00
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1990-11-13 14:52:51 +00:00
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pat loc yields {const4, $1}
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1990-11-12 15:36:03 +00:00
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pat ldc leaving loc 18 trp
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1988-02-17 15:44:54 +00:00
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1990-11-12 15:36:03 +00:00
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pat lol yields {lb_local, $1}
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1988-02-17 15:44:54 +00:00
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1990-11-12 15:36:03 +00:00
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pat loe yields {absolute, $1}
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1988-02-17 15:44:54 +00:00
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1990-11-12 15:36:03 +00:00
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pat lil leaving lol $1 loi 4
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1988-02-17 15:44:54 +00:00
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pat lof
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with GENREG yields {regrel, %1, $1}
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1990-11-12 15:36:03 +00:00
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with exact addr_local yields {lb_local, %1.ind+$1}
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1988-02-17 15:44:54 +00:00
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with exact addr_external yields {absolute, %1.add+$1}
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with exact regconst yields {regrel, %1.reg, $1+%1.ind}
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1990-11-12 15:36:03 +00:00
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pat lal $1 > 0 yields {addr_local, $1}
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pat lal $1 < 0 yields {naddr_local, 0-$1}
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pat lal $1 == 0 yields LB
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1988-02-17 15:44:54 +00:00
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pat lae yields {addr_external, $1}
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1990-11-12 15:36:03 +00:00
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pat lae loi lae sti $2==$4 leaving lae $1 lae $3 blm $2
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1988-02-17 15:44:54 +00:00
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pat lxl $1==0 yields LB
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1990-11-12 15:36:03 +00:00
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pat lxl $1==1 yields {lb_local,8}
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1988-02-17 15:44:54 +00:00
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pat lxl $1>1
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1990-11-12 15:36:03 +00:00
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uses GENREG={const4, $1}, GENREG=LB
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gen LABEL {label, "1:"}
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move {regrel, %b, 8}, %b
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1988-02-17 15:44:54 +00:00
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SUB_S %a, %a, {fitcon,1}
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BNE {label,"1B"} yields %b
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pat lxa $1==0 yields {addr_local,8}
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pat lxa $1==1
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1990-11-12 15:36:03 +00:00
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uses GENREG={lb_local,8} yields {regconst,%a,8}
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1988-02-17 15:44:54 +00:00
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|
pat lxa $1>1
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG={const4, $1}, GENREG=LB
|
|
|
|
gen LABEL {label, "1:"}
|
|
|
|
move {regrel, %b, 8}, %b
|
1988-02-17 15:44:54 +00:00
|
|
|
SUB_S %a, %a, {fitcon,1}
|
|
|
|
BNE {label,"1B"} yields {regconst, %b, 8}
|
|
|
|
|
|
|
|
pat loi $1==1
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen LDR_B %a, {regind, %1} yields %a
|
|
|
|
with exact naddr_local
|
|
|
|
uses GENREG
|
|
|
|
gen LDR_B %a, {lb_local, 0-%1.ind} yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
with exact addr_local
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen LDR_B %a, {lb_local, %1.ind} yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
with exact addr_external
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen LDR_B %a, {absolute, %1.add} yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
with exact regconst
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen LDR_B %a, {regrel, %1.reg, %1.ind} yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
with exact regplusreg
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen LDR_B %a, {regregrel, %1.reg1, %1.reg2} yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
with exact regminreg
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen LDR_B %a, {regminregrel, %1.reg1, %1.reg2} yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
with exact regplusiSreg
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
gen LDR_B %a, {regiSregrel, %1.reg1, %1.S, %1.shift, %1.reg2} yields %a
|
|
|
|
with exact regminiSreg
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen LDR_B %a, {regminiSregrel,%1.reg1,%1.S,%1.shift,%1.reg2} yields %a
|
|
|
|
|
1988-02-17 15:44:54 +00:00
|
|
|
with exact regplusrSreg
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG,GENREG
|
|
|
|
gen move {regS,%1.reg2,%1.S,%1.sreg}, %b
|
|
|
|
LDR_B %a, {regregrel, %1.reg1, %b} yields %a
|
|
|
|
|
1988-02-17 15:44:54 +00:00
|
|
|
with exact regminrSreg
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen LDR_B %a, {regminrSregrel,%1.reg1,%1.S,%1.sreg,%1.reg2} yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat loi $1==2
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG, GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
gen LDR_B %a, {regind, %1}
|
|
|
|
LDR_B %b, {regrel, %1, 1}
|
1990-11-12 15:36:03 +00:00
|
|
|
ADD %a,%a,{imS,%b,"LSL",8} yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat loi $1==4
|
|
|
|
with GENREG yields {regind, %1}
|
1990-11-12 15:36:03 +00:00
|
|
|
with exact addr_local yields {lb_local, %1.ind}
|
|
|
|
with exact naddr_local yields {lb_local, 0-%1.ind}
|
1988-02-17 15:44:54 +00:00
|
|
|
with exact addr_external yields {absolute, %1.add}
|
|
|
|
with exact regconst yields {regrel, %1.reg, %1.ind}
|
1990-11-12 15:36:03 +00:00
|
|
|
with exact regplusreg yields {regregrel, %1.reg1, %1.reg2}
|
|
|
|
with exact regminreg yields {regminregrel, %1.reg1, %1.reg2}
|
|
|
|
with exact regplusiSreg yields {regiSregrel,%1.reg1,%1.S,
|
|
|
|
%1.shift,%1.reg2}
|
|
|
|
with exact regminiSreg yields {regminiSregrel,%1.reg1,%1.S,
|
|
|
|
%1.shift,%1.reg2}
|
|
|
|
with exact regplusrSreg
|
|
|
|
uses GENREG,GENREG
|
|
|
|
gen move {regS,%1.reg2,%1.S,%1.sreg}, %b
|
|
|
|
LDR %a, {regregrel, %1.reg1, %b} yields %a
|
|
|
|
|
|
|
|
with exact regminrSreg yields {regminrSregrel,%1.reg1,
|
|
|
|
%1.S,%1.sreg,%1.reg2}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat loi $1==8
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG, GENREG
|
|
|
|
gen LDMIA %1, {reglist2, %a, %b} yields %b %a
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat loi defined($1)
|
|
|
|
with GENREG STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG = {const4, $1}
|
1988-02-17 15:44:54 +00:00
|
|
|
gen LABEL {label, "1:"}
|
|
|
|
SUB_S %a, %a, {fitcon, 4}
|
|
|
|
move {regregrel, %1, %a}, R11
|
1990-11-12 15:36:03 +00:00
|
|
|
STMFD {autoid, SP}, {reglist1, R11}
|
|
|
|
BGT {label, "1b"}
|
|
|
|
|
|
|
|
pat loi loc and $1==2 && $2>0 && $2<256 leaving loi 1 loc $2 and $3
|
1988-02-17 15:44:54 +00:00
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat loi loc loc cii $1==2 && $2==2 && $3==4
|
|
|
|
with GENREG
|
|
|
|
uses GENREG,GENREG
|
|
|
|
gen LDR_B %a, {regind, %1}
|
|
|
|
LDR_B %b, {regrel, %1, 1}
|
|
|
|
MOV %b, {imS, %b, "LSL", 24}
|
|
|
|
ORR %a, %a, {imS, %b, "ASR", 16} yields %a
|
|
|
|
|
|
|
|
pat los
|
1988-02-17 15:44:54 +00:00
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
gen BAL_L {label, ".los"}
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat ldl yields {lb_local, $1+4}
|
|
|
|
{lb_local, $1}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat lde yields {absolute, $1+4}
|
|
|
|
{absolute, $1}
|
|
|
|
|
|
|
|
pat ldf
|
|
|
|
with GENREG yields {regrel, %1, $1+4}
|
|
|
|
{regrel, %1, $1}
|
1990-11-12 15:36:03 +00:00
|
|
|
with exact addr_local yields {lb_local, %1.ind+$1+4}
|
|
|
|
{lb_local, %1.ind+$1}
|
1988-02-17 15:44:54 +00:00
|
|
|
with exact addr_external yields {absolute, %1.add+$1+4}
|
|
|
|
{absolute, %1.add+$1}
|
|
|
|
with exact regconst yields {regrel, %1.reg, $1+%1.ind+4}
|
|
|
|
{regrel, %1.reg, $1+%1.ind}
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat lpi yields {addr_external,$1}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* *
|
|
|
|
* GROUP II : Store Instructions *
|
|
|
|
* *
|
|
|
|
************************************************************************/
|
|
|
|
|
|
|
|
pat stl
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
kills address-(absolute+lb_local), lb_local %ind-4 < $1 && %ind+4 > $1
|
|
|
|
gen move %1, {lb_local, $1}
|
|
|
|
|
|
|
|
pat stl lol $1==$2 leaving dup 4 stl $1
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat ste
|
|
|
|
with GENREG
|
|
|
|
kills address
|
|
|
|
gen move %1, {absolute, $1}
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat ste loe $1==$2
|
|
|
|
leaving dup 4 ste $1
|
|
|
|
|
|
|
|
pat sil leaving lol $1 sti 4
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat stf
|
|
|
|
with GENREG GENREG
|
|
|
|
kills address
|
|
|
|
gen move %2, {regrel, %1, $1}
|
|
|
|
with addr_local GENREG
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
gen move %2, {lb_local, %1.ind + $1}
|
1988-02-17 15:44:54 +00:00
|
|
|
with addr_external GENREG
|
|
|
|
kills address
|
|
|
|
gen move %2, {absolute, %1.add + $1}
|
|
|
|
with regconst GENREG
|
|
|
|
kills address
|
|
|
|
gen move %2, {regrel, %1.reg, $1+%1.ind}
|
|
|
|
|
|
|
|
pat sti $1==1
|
|
|
|
with GENREG GENREG
|
|
|
|
kills address
|
|
|
|
gen STR_B %2, {regind, %1}
|
|
|
|
with addr_local GENREG
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
gen STR_B %2, {lb_local, %1.ind}
|
1988-02-17 15:44:54 +00:00
|
|
|
with addr_external GENREG
|
|
|
|
kills address
|
|
|
|
gen STR_B %2, {absolute, %1.add}
|
|
|
|
with regconst GENREG
|
|
|
|
kills address
|
|
|
|
gen STR_B %2, {regrel, %1.reg, %1.ind}
|
|
|
|
with regplusreg GENREG
|
|
|
|
kills address
|
|
|
|
gen STR_B %2, {regregrel, %1.reg1, %1.reg2}
|
1990-11-12 15:36:03 +00:00
|
|
|
with regminreg GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
gen STR_B %2, {regminregrel, %1.reg1, %1.reg2}
|
1988-02-17 15:44:54 +00:00
|
|
|
with regplusiSreg GENREG
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
gen STR_B %2, {regiSregrel, %1.reg1, %1.S, %1.shift, %1.reg2}
|
1988-02-17 15:44:54 +00:00
|
|
|
with regminiSreg GENREG
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
gen STR_B %2, {regminiSregrel, %1.reg1, %1.S, %1.shift, %1.reg2}
|
|
|
|
|
1988-02-17 15:44:54 +00:00
|
|
|
with regplusrSreg GENREG
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen move {regS, %1.reg2, %1.S, %1.sreg}, %a
|
|
|
|
STR_B %2, {regregrel, %1.reg1, %a}
|
|
|
|
|
1988-02-17 15:44:54 +00:00
|
|
|
with regminrSreg GENREG
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
gen STR_B %2, {regminrSregrel, %1.reg1, %1.S, %1.sreg, %1.reg2}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat sti $1==2
|
|
|
|
with GENREG GENREG
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
/*uses GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
gen move {imS, %2, "LSR", 8}, %a
|
|
|
|
SUB %2, %2, {imS, %a, "LSL", 8}
|
|
|
|
STR_B %2, {regind, %1}
|
|
|
|
STR_B %a, {regrel, %1, 1}
|
1990-11-12 15:36:03 +00:00
|
|
|
*/
|
|
|
|
gen STR_B %2, {regind, %1}
|
|
|
|
MOV %2, {imS, %2, "LSR", 8}
|
|
|
|
STR_B %2, {regrel, %1, 1}
|
|
|
|
/*with GENREG fitcon %2.num==0
|
|
|
|
kills address
|
|
|
|
gen STR_B %2, {regind, %1}
|
|
|
|
STR_B %2, {regrel, %1, 1}
|
|
|
|
*/
|
1988-02-17 15:44:54 +00:00
|
|
|
pat sti $1==4
|
|
|
|
with GENREG GENREG
|
|
|
|
kills address
|
|
|
|
gen move %2, {regind, %1}
|
|
|
|
with addr_local GENREG
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
gen move %2, {lb_local, %1.ind}
|
1988-02-17 15:44:54 +00:00
|
|
|
with addr_external GENREG
|
|
|
|
kills address
|
|
|
|
gen move %2, {absolute, %1.add}
|
|
|
|
with regconst GENREG
|
|
|
|
kills address
|
|
|
|
gen move %2, {regrel, %1.reg, %1.ind}
|
|
|
|
with regplusreg GENREG
|
|
|
|
kills address
|
|
|
|
gen move %2, {regregrel, %1.reg1, %1.reg2}
|
1990-11-12 15:36:03 +00:00
|
|
|
with regminreg GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
gen move %2, {regminregrel, %1.reg1, %1.reg2}
|
1988-02-17 15:44:54 +00:00
|
|
|
with regplusiSreg GENREG
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
gen move %2, {regiSregrel, %1.reg1, %1.S, %1.shift, %1.reg2}
|
1988-02-17 15:44:54 +00:00
|
|
|
with regminiSreg GENREG
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
gen move %2, {regminiSregrel, %1.reg1, %1.S, %1.shift, %1.reg2}
|
1988-02-17 15:44:54 +00:00
|
|
|
with regplusrSreg GENREG
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen move {regS, %1.reg2, %1.S, %1.sreg}, %a
|
|
|
|
STR %2, {regregrel, %1.reg1, %a}
|
1988-02-17 15:44:54 +00:00
|
|
|
with regminrSreg GENREG
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
gen move %2, {regminrSregrel, %1.reg1, %1.S, %1.sreg, %1.reg2}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat sti defined($1) && legal($1)
|
1988-02-17 15:44:54 +00:00
|
|
|
with GENREG STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
kills address
|
|
|
|
uses GENREG={fitcon, $1}
|
1988-02-17 15:44:54 +00:00
|
|
|
gen LABEL {label, "1:"}
|
|
|
|
SUB_S %a, %a, {fitcon, 4}
|
1990-11-12 15:36:03 +00:00
|
|
|
move {st_regregrel, SP, %a}, R11
|
1988-02-17 15:44:54 +00:00
|
|
|
move R11, {regregrel, %1, %a}
|
1990-11-12 15:36:03 +00:00
|
|
|
BGT {label,"1B"}
|
|
|
|
ADD SP, SP, {fitcon, $1}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat sti defined($1)
|
|
|
|
with GENREG STACK
|
|
|
|
kills address
|
|
|
|
uses GENREG={const4, $1}, GENREG
|
|
|
|
gen move %a, %b
|
|
|
|
LABEL {label, "1:"}
|
|
|
|
SUB_S %a, %a, {fitcon, 4}
|
|
|
|
move {st_regregrel, SP, %a}, R11
|
|
|
|
move R11, {regregrel, %1, %a}
|
|
|
|
BGT {label,"1B"}
|
|
|
|
ADD SP, SP, %b
|
|
|
|
|
|
|
|
pat sts
|
1988-02-17 15:44:54 +00:00
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
gen BAL_L {label, ".sts"}
|
|
|
|
|
|
|
|
pat sdl
|
|
|
|
with GENREG GENREG
|
|
|
|
kills address-absolute
|
1990-11-12 15:36:03 +00:00
|
|
|
gen move %1, {lb_local,$1}
|
|
|
|
move %2, {lb_local,$1+4}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat sde
|
|
|
|
with GENREG GENREG
|
|
|
|
kills address
|
|
|
|
gen move %1, {absolute, $1}
|
|
|
|
move %2, {absolute, $1+4}
|
|
|
|
|
|
|
|
pat sdf
|
|
|
|
with GENREG GENREG GENREG
|
|
|
|
kills address
|
|
|
|
gen move %2, {regrel, %1, $1}
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|
|
|
move %3, {regrel, %1, $1+4}
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* *
|
|
|
|
* GROUP III : Integer Arithmetic *
|
|
|
|
* *
|
|
|
|
************************************************************************/
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|
|
|
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|
|
pat adi $1==4
|
1990-11-12 15:36:03 +00:00
|
|
|
with GENREG constant yields {regconst, %1, %2.num}
|
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|
|
with constant GENREG yields {regconst, %2, %1.num}
|
1988-02-17 15:44:54 +00:00
|
|
|
with GENREG GENREG yields {regplusreg, %1, %2}
|
1990-11-12 15:36:03 +00:00
|
|
|
with GENREG imS yields {regplusiSreg,%1, %2.S,
|
|
|
|
%2.shift, %2.reg}
|
|
|
|
with imS GENREG yields {regplusiSreg,%2, %1.S,
|
|
|
|
%1.shift, %1.reg}
|
|
|
|
with GENREG regS yields {regplusrSreg,%1, %2.S,
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|
|
|
%2.sreg, %2.reg}
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|
|
|
with regS GENREG yields {regplusrSreg,%2, %1.S,
|
|
|
|
%1.sreg, %1.reg}
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|
|
|
with exact addr_local constant yields {addr_local, %1.ind+%2.num}
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|
|
|
with exact constant addr_local yields {addr_local, %2.ind+%1.num}
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|
|
|
with exact addr_external constant yields {addr_external, %1.add+%2.num}
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|
|
with exact constant addr_external yields {addr_external, %2.add+%1.num}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat sbi $1==4
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|
|
with GENREG GENREG yields {regminreg, %2, %1}
|
1990-11-12 15:36:03 +00:00
|
|
|
with imS GENREG yields {regminiSreg,%2,%1.S,
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|
|
|
%1.shift,%1.reg}
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|
|
|
with regS GENREG yields {regminrSreg,%2,%1.S,
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|
|
|
%1.sreg,%1.reg}
|
|
|
|
with GENREG fitcon
|
|
|
|
uses GENREG
|
|
|
|
gen RSB %a, %1, %2 yields %a
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|
|
with fitcon GENREG
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|
|
gen SUB %2, %2, %1 yields %2
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|
|
with GENREG const4
|
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|
|
uses GENREG
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|
|
gen move %2, %a
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|
|
RSB %1, %1, %a yields %1
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|
|
with const4 GENREG
|
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|
|
uses GENREG
|
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|
|
gen move %1, %a
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|
|
SUB %a, %2, %a yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
with GENREG REGcon
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen RSB %a, %1, %2 yields %a
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|
|
|
/*with constant GENREG yields {regconst, %2, 0-%1.num}*/
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|
|
with exact constant addr_local yields {addr_local, %2.ind-%1.num}
|
1988-02-17 15:44:54 +00:00
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|
|
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|
|
pat loc mli $1<0 && $2==4 leaving loc 0-$1
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|
|
|
mli 4
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|
|
ngi 4
|
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|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat loc mli $1==2 && $2==4
|
1988-02-17 15:44:54 +00:00
|
|
|
with GENREG yields {imS, %1, "LSL", 1}
|
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|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat loc mli $1==4 && $2==4
|
1988-02-17 15:44:54 +00:00
|
|
|
with GENREG yields {imS, %1, "LSL", 2}
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat loc mli $1==8 && $2==4
|
1988-02-17 15:44:54 +00:00
|
|
|
with GENREG yields {imS, %1, "LSL", 3}
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat loc mli $1==16 && $2==4
|
1988-02-17 15:44:54 +00:00
|
|
|
with GENREG yields {imS, %1, "LSL", 4}
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat loc mli $1==32 && $2==4
|
1988-02-17 15:44:54 +00:00
|
|
|
with GENREG yields {imS, %1, "LSL", 5}
|
|
|
|
|
|
|
|
pat loc mli $1==3 && $2==4
|
|
|
|
with GENREG yields {regplusiSreg,%1,"LSL",1,%1}
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|
|
|
|
|
|
|
pat loc mli $1==5 && $2==4
|
|
|
|
with GENREG yields {regplusiSreg,%1,"LSL",2,%1}
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|
|
|
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|
|
|
pat loc mli $1==6 && $2==4
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen MOV %a, {imS,%1,"LSL",2}
|
|
|
|
ADD %a, %a, {imS,%1,"LSL",1} yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat loc mli $1==7 && $2==4
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen RSB %a, %1, {imS, %1, "LSL", 3} yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat loc mli $1==9 && $2==4
|
|
|
|
with GENREG yields {regplusiSreg,%1,"LSL",3,%1}
|
|
|
|
|
|
|
|
pat loc mli $1==10 && $2==4
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen MOV %a,{imS, %1, "LSL", 1}
|
|
|
|
ADD %a, %a, {imS, %1, "LSL", 3} yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat loc mli $1==12 && $2==4
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen move {imS, %1, "LSL", 3}, %a yields {regplusiSreg,%a,"LSR",1,%a}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat mli $1==4
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
gen BAL_L {label, ".mli"} yields R0
|
|
|
|
|
|
|
|
pat loc dvi $1<0 && $2==4 leaving loc 0-$1
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|
|
|
dvi 4
|
|
|
|
|
|
|
|
pat dvi $1==4
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
gen BAL_L {label, ".dvi"} yields R3
|
|
|
|
|
|
|
|
pat rmi $1==4
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
gen BAL_L {label, ".dvi"} yields R2
|
|
|
|
|
|
|
|
pat ngi $1==4
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen RSB %a, %1, {fitcon, 0} yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat sli $1==4
|
1990-11-12 15:36:03 +00:00
|
|
|
with fitcon GENREG yields {imS, %2, "LSL", %1.num}
|
1988-02-17 15:44:54 +00:00
|
|
|
with GENREG GENREG yields {regS, %2, "LSL", %1}
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat loc sri $1==0 && $2==4
|
1988-02-17 15:44:54 +00:00
|
|
|
with address+REGcon yields %1
|
|
|
|
|
|
|
|
pat sri $1==4
|
1990-11-12 15:36:03 +00:00
|
|
|
with fitcon GENREG yields {imS, %2, "ASR", %1.num}
|
1988-02-17 15:44:54 +00:00
|
|
|
with GENREG GENREG yields {regS, %2, "ASR", %1}
|
|
|
|
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* *
|
|
|
|
* GROUP IV : Unsigned Arithmetic *
|
|
|
|
* *
|
|
|
|
************************************************************************/
|
|
|
|
|
1988-02-18 11:17:39 +00:00
|
|
|
pat adu leaving adi $1
|
1988-02-17 15:44:54 +00:00
|
|
|
|
1988-02-18 11:17:39 +00:00
|
|
|
pat sbu leaving sbi $1
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat loc mlu $1<11 && $1>0 && $2==4 leaving loc $1
|
|
|
|
mli 4
|
|
|
|
|
|
|
|
pat mlu $1==4
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
gen BAL_L {label, ".mlu"} yields R0
|
|
|
|
|
|
|
|
pat loc dvu $1<33 && $1>0 && $2==4 leaving loc $1
|
|
|
|
dvi 4
|
|
|
|
|
|
|
|
pat dvu $1==4
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
gen BAL_L {label, ".dvu"} yields R3
|
|
|
|
|
|
|
|
pat rmu $1==4
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
gen BAL_L {label, ".dvu"} yields R2
|
|
|
|
|
|
|
|
pat slu $1==4
|
|
|
|
with GENREG GENREG yields {regS, %2, "LSL", %1}
|
1990-11-12 15:36:03 +00:00
|
|
|
with const4+fitcon GENREG yields {imS, %2, "LSL", %1.num}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat sru $1==4
|
|
|
|
with GENREG GENREG yields {regS, %2, "LSR", %1}
|
1990-11-12 15:36:03 +00:00
|
|
|
with const4+fitcon GENREG yields {imS, %2, "LSR", %1.num}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* *
|
|
|
|
* GROUP V : Floating Point Arithmetic *
|
|
|
|
* *
|
|
|
|
************************************************************************/
|
|
|
|
|
1990-11-13 13:21:21 +00:00
|
|
|
pat adf $1==4 leaving cal ".adf4" asp 4
|
|
|
|
pat adf $1==8 leaving cal ".adf8" asp 8
|
|
|
|
pat sbf $1==4 leaving cal ".sbf4" asp 4
|
|
|
|
pat sbf $1==8 leaving cal ".sbf8" asp 8
|
|
|
|
pat mlf $1==4 leaving cal ".mlf4" asp 4
|
|
|
|
pat mlf $1==8 leaving cal ".mlf8" asp 8
|
|
|
|
pat dvf $1==4 leaving cal ".dvf4" asp 4
|
|
|
|
pat dvf $1==8 leaving cal ".dvf8" asp 8
|
|
|
|
pat ngf $1==4 leaving cal ".ngf4"
|
|
|
|
pat ngf $1==8 leaving cal ".ngf8"
|
|
|
|
pat fif $1==4 leaving lor 1 cal ".fif4" asp 4
|
|
|
|
pat fif $1==8 leaving lor 1 cal ".fif8" asp 4
|
|
|
|
pat fef $1==4 leaving lor 1 adp 0-4 cal ".fef4"
|
|
|
|
pat fef $1==8 leaving lor 1 adp 0-4 cal ".fef8"
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* *
|
|
|
|
* GROUP VI : Pointer Arithmetic *
|
|
|
|
* *
|
|
|
|
************************************************************************/
|
|
|
|
|
|
|
|
pat adp
|
|
|
|
with GENREG yields {regconst, %1, $1}
|
|
|
|
with exact addr_local yields {addr_local, %1.ind+$1}
|
|
|
|
with exact addr_external yields {addr_external, %1.add+$1}
|
|
|
|
with exact regconst yields {regconst, %1.reg, %1.ind+$1}
|
|
|
|
|
1988-02-18 11:17:39 +00:00
|
|
|
pat ads $1==4 leaving adi 4
|
1988-02-17 15:44:54 +00:00
|
|
|
|
1988-02-18 11:17:39 +00:00
|
|
|
pat sbs $1==4 leaving sbi 4
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* *
|
|
|
|
* GROUP VII : Increment/Decrement/Zero *
|
|
|
|
* *
|
|
|
|
************************************************************************/
|
|
|
|
|
|
|
|
pat inc
|
|
|
|
with GENREG yields {regconst, %1, 1}
|
|
|
|
with exact regconst yields {regconst, %1.reg, %1.ind+1}
|
|
|
|
|
|
|
|
pat inl
|
|
|
|
kills address-absolute
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG={lb_local,$1}
|
|
|
|
gen ADD %a,%a,{fitcon,1}
|
|
|
|
move %a,{lb_local,$1}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat ine
|
1990-11-12 15:36:03 +00:00
|
|
|
kills address
|
|
|
|
uses GENREG={absolute,$1}
|
|
|
|
gen ADD %a,%a,{fitcon,1}
|
1988-02-17 15:44:54 +00:00
|
|
|
move %a,{absolute,$1}
|
|
|
|
|
|
|
|
pat dec
|
|
|
|
with GENREG yields {regconst, %1, 0-1}
|
1990-11-12 15:36:03 +00:00
|
|
|
/*gen SUB %a, %1, {fitcon, 1}*/
|
|
|
|
with exact regconst yields {regconst, %1.reg, %1.ind-1}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat del
|
|
|
|
kills address-absolute
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG={lb_local,$1}
|
1988-02-17 15:44:54 +00:00
|
|
|
gen SUB %a,%a,{fitcon,1}
|
1990-11-12 15:36:03 +00:00
|
|
|
move %a,{lb_local,$1}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat dee
|
1990-11-12 15:36:03 +00:00
|
|
|
kills address
|
|
|
|
uses GENREG={absolute,$1}
|
1988-02-17 15:44:54 +00:00
|
|
|
gen SUB %a,%a,{fitcon,1}
|
|
|
|
move %a,{absolute,$1}
|
|
|
|
|
|
|
|
pat zrl
|
|
|
|
kills address-absolute
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG={fitcon,0}
|
|
|
|
gen move %a,{lb_local,$1}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat zre
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG={fitcon,0}
|
1988-02-17 15:44:54 +00:00
|
|
|
gen move %a,{absolute,$1}
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat zrf leaving zer $1
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat zer $1==4 yields {fitcon,0}
|
|
|
|
|
|
|
|
pat zer $1==8 yields {fitcon,0} {fitcon,0}
|
|
|
|
|
|
|
|
pat zer $1==12 yields {fitcon,0} {fitcon,0} {fitcon,0}
|
|
|
|
|
|
|
|
pat zer defined($1)
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG={fitcon,0},GENREG={const4,$1}
|
1988-02-17 15:44:54 +00:00
|
|
|
gen LABEL {label, "1:"}
|
1990-11-12 15:36:03 +00:00
|
|
|
STMFD {autoid, SP}, {reglist1, %a}
|
1988-02-17 15:44:54 +00:00
|
|
|
SUB_S %b,%b,{fitcon,4}
|
|
|
|
BNE {label,"1B"}
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* *
|
|
|
|
* GROUP VIII : Convert *
|
|
|
|
* *
|
|
|
|
************************************************************************/
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
/* sign extension short -> integer */
|
|
|
|
pat loc loc cii $1==2 && $2==4
|
|
|
|
with GENREG
|
|
|
|
uses GENREG
|
|
|
|
gen MOV %a, {imS, %1, "LSL", 16}
|
|
|
|
MOV %a, {imS, %a, "ASR", 16} yields %a
|
|
|
|
|
|
|
|
/* sign extension byte -> integer */
|
|
|
|
pat loc loc cii $1==1 && $2==4
|
|
|
|
with GENREG
|
|
|
|
uses GENREG
|
|
|
|
gen MOV %a, {imS, %1, "LSL", 24}
|
|
|
|
MOV %a, {imS, %a, "ASR", 24} yields %a
|
|
|
|
|
|
|
|
pat loc loc cii ($1 > 2)
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat cui
|
|
|
|
with address +REGcon address + REGcon
|
|
|
|
|
1990-11-13 13:21:21 +00:00
|
|
|
pat loc loc cif $1==4 && $2==4 leaving loc 4 cal ".cif4" asp 4
|
|
|
|
pat loc loc cif $1==4 && $2==8 leaving loc 4 cal ".cif8"
|
1990-11-12 15:36:03 +00:00
|
|
|
|
1990-11-13 13:21:21 +00:00
|
|
|
pat loc loc cuf $1==4 && $2==4 leaving loc 4 cal ".cuf4" asp 4
|
1990-11-12 15:36:03 +00:00
|
|
|
pat loc loc cuf $1==4 && $2==8 leaving loc 4 cal ".cuf8"
|
|
|
|
|
1990-11-13 13:21:21 +00:00
|
|
|
pat loc loc cfi leaving loc $1 loc $2 cal ".cfi" asp 8+($1-4)
|
1990-11-12 15:36:03 +00:00
|
|
|
|
1990-11-13 13:21:21 +00:00
|
|
|
pat loc loc cfu leaving loc $1 loc $2 cal ".cfu" asp 8+($1-4)
|
1990-11-12 15:36:03 +00:00
|
|
|
|
|
|
|
pat loc loc cff $1==8 && $2==4 leaving cal ".cff4" asp 4
|
|
|
|
|
|
|
|
/* this one expects a 4 byte hole on the stack */
|
|
|
|
pat loc loc cff $1==4 && $2==8 leaving dup 4 cal ".cff8"
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat ciu
|
|
|
|
with address +REGcon address + REGcon
|
|
|
|
|
|
|
|
pat cuu
|
|
|
|
with address +REGcon address + REGcon
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* *
|
|
|
|
* GROUP IX : Logical *
|
|
|
|
* *
|
|
|
|
************************************************************************/
|
|
|
|
|
|
|
|
pat and $1==4
|
|
|
|
with REGcon GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen AND %a, %2, %1 yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
with GENREG REGcon
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen AND %a, %1, %2 yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat ior $1==4
|
|
|
|
with REGcon GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen ORR %a, %2, %1 yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
with GENREG REGcon
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen ORR %a, %1, %2 yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat xor $1==4
|
|
|
|
with REGcon GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen EOR %a, %2, %1 yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
with GENREG REGcon
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen EOR %a, %1, %2 yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat com $1==4
|
|
|
|
with REGcon
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
gen MVN %a,%1 yields %a
|
|
|
|
|
|
|
|
pat ror $1==4
|
1990-11-12 15:36:03 +00:00
|
|
|
with constant GENREG yields {imS, %2, "ROR", %1.num}
|
1988-02-17 15:44:54 +00:00
|
|
|
with GENREG GENREG yields {regS, %2, "ROR", %1}
|
|
|
|
|
|
|
|
pat rol $1==4
|
1990-11-12 15:36:03 +00:00
|
|
|
with constant GENREG yields {imS, %2, "ROR", 32-%1.num}
|
1988-02-17 15:44:54 +00:00
|
|
|
with GENREG GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen RSB %a, %1, {fitcon,32} yields {regS, %2, "ROR", %a}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat and $1>4
|
|
|
|
with STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
kills ALL
|
|
|
|
uses GENREG,GENREG,GENREG,GENREG
|
|
|
|
gen move {const4,$1}, %b
|
|
|
|
move SP, %a
|
|
|
|
ADD SP, SP, %b
|
1988-02-17 15:44:54 +00:00
|
|
|
LABEL {label, "1:"}
|
1990-11-12 15:36:03 +00:00
|
|
|
SUB_S %b, %b, {fitcon, 4}
|
|
|
|
move {st_regregrel, SP,%b}, %c
|
|
|
|
move {regregrel, %a, %b}, %d
|
|
|
|
AND %c, %c, %d
|
|
|
|
move %c, {st_regregrel, SP, %b}
|
1988-02-17 15:44:54 +00:00
|
|
|
BNE {label, "1B"}
|
|
|
|
|
|
|
|
pat ior $1>4
|
|
|
|
with STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
kills ALL
|
|
|
|
uses GENREG,GENREG,GENREG,GENREG
|
|
|
|
gen move {const4,$1}, %b
|
|
|
|
move SP, %a
|
|
|
|
ADD SP, SP, %b
|
1988-02-17 15:44:54 +00:00
|
|
|
LABEL {label, "1:"}
|
1990-11-12 15:36:03 +00:00
|
|
|
SUB_S %b, %b, {fitcon, 4}
|
|
|
|
move {st_regregrel, SP,%b}, %c
|
|
|
|
move {regregrel, %a, %b}, %d
|
|
|
|
ORR %c, %c, %d
|
|
|
|
move %c, {st_regregrel, SP, %b}
|
|
|
|
BNE {label, "1B"}
|
|
|
|
|
|
|
|
pat ior !defined($1)
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
uses GENREG,GENREG,GENREG,GENREG
|
|
|
|
gen LDMFD {autoid, SP}, {reglist1, %b}
|
|
|
|
move SP, %a
|
|
|
|
ADD SP, SP, %b
|
|
|
|
LABEL {label, "1:"}
|
|
|
|
SUB_S %b, %b, {fitcon, 4}
|
|
|
|
move {st_regregrel, SP, %b}, %c
|
|
|
|
move {regregrel, %a, %b}, %d
|
|
|
|
ORR %c, %c, %d
|
|
|
|
move %c, {st_regregrel, SP, %b}
|
1988-02-17 15:44:54 +00:00
|
|
|
BNE {label, "1B"}
|
|
|
|
|
|
|
|
|
|
|
|
pat xor $1>4
|
|
|
|
with STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
kills ALL
|
|
|
|
uses GENREG,GENREG,GENREG,GENREG
|
|
|
|
gen move {const4,$1}, %b
|
|
|
|
move SP, %a
|
|
|
|
ADD SP, SP, %b
|
1988-02-17 15:44:54 +00:00
|
|
|
LABEL {label, "1:"}
|
1990-11-12 15:36:03 +00:00
|
|
|
SUB_S %b, %b, {fitcon, 4}
|
|
|
|
move {st_regregrel, SP,%b}, %c
|
|
|
|
move {regregrel, %a, %b}, %d
|
|
|
|
EOR %c, %c, %d
|
|
|
|
move %c, {st_regregrel, SP, %b}
|
1988-02-17 15:44:54 +00:00
|
|
|
BNE {label, "1B"}
|
|
|
|
|
|
|
|
pat com $1>4
|
|
|
|
with STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
kills ALL
|
|
|
|
uses GENREG,GENREG,GENREG
|
|
|
|
gen move {const4,$1}, %b
|
1988-02-17 15:44:54 +00:00
|
|
|
LABEL {label, "1:"}
|
1990-11-12 15:36:03 +00:00
|
|
|
SUB_S %b, %b, {fitcon, 4}
|
|
|
|
move {st_regregrel, SP, %b}, %c
|
|
|
|
MVN %c, %c
|
|
|
|
move %c, {st_regregrel, SP, %b}
|
1988-02-17 15:44:54 +00:00
|
|
|
BNE {label, "1B"}
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* *
|
|
|
|
* GROUP X: Sets *
|
|
|
|
* *
|
|
|
|
************************************************************************/
|
|
|
|
|
|
|
|
pat loc loc inn !defined($3) leaving loc $1 inn $2
|
|
|
|
|
|
|
|
pat loc inn $2==4 && $1>=0 && $1<32
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG={fitcon,1},GENREG
|
|
|
|
gen AND %b, %1, {imS,%a,"LSL",$1} yields %b
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat loc inn $2==4 && $1<0
|
|
|
|
with GENREG
|
|
|
|
gen move {fitcon,0}, %1 yields %1
|
|
|
|
|
|
|
|
pat loc inn $2==4 && $1>31 leaving loc 2 trp
|
|
|
|
|
|
|
|
pat loc inn !defined($2) leaving inn $1
|
|
|
|
|
|
|
|
pat inn defined($1)
|
1990-11-12 15:36:03 +00:00
|
|
|
with GENREG STACK
|
|
|
|
uses GENREG={fitcon,1}, GENREG, GENREG
|
|
|
|
gen AND %b, %1, {fitcon, 31}
|
|
|
|
move {regS, %a, "LSL", %b}, %b
|
|
|
|
move {imS, %1, "LSR", 5}, %1
|
|
|
|
move {st_regiSregrel, SP, "LSL", 2, %1}, %c
|
|
|
|
AND_S %b, %b, %c
|
|
|
|
MOV_NE %b, {fitcon, 1}
|
|
|
|
ADD SP, SP, {const4, $1} yields %b
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat inn !defined($1)
|
1990-11-12 15:36:03 +00:00
|
|
|
with GENREG GENREG STACK
|
|
|
|
uses GENREG={fitcon,1}, GENREG, GENREG
|
|
|
|
gen AND %b, %2, {fitcon, 31}
|
|
|
|
move {regS, %a, "LSL", %b}, %b
|
|
|
|
move {imS, %2, "LSR", 5}, %2
|
|
|
|
move {st_regiSregrel, SP, "LSL", 2, %2}, %c
|
|
|
|
AND_S %b, %b, %c
|
|
|
|
MOV_NE %b, {fitcon, 1}
|
|
|
|
ADD SP, SP, %1 yields %b
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat loc set !defined($2) leaving set $1
|
|
|
|
|
|
|
|
pat set $1==4
|
1990-11-12 15:36:03 +00:00
|
|
|
with const4
|
|
|
|
uses GENREG={fitcon,1} yields {imS,%a,"LSL",%1.num}
|
|
|
|
with GENREG
|
|
|
|
uses GENREG={fitcon,1} yields {regS,%a,"LSL",%1}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat set $1>4
|
|
|
|
with GENREG STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG={fitcon,1}, GENREG={fitcon,0}, GENREG={const4,$1}
|
1988-02-17 15:44:54 +00:00
|
|
|
gen LABEL {label, "2:"}
|
1990-11-12 15:36:03 +00:00
|
|
|
STMFD {autoid, SP}, {reglist1, %b}
|
1988-02-17 15:44:54 +00:00
|
|
|
SUB_S %c, %c, {fitcon,4}
|
|
|
|
BGT {label, "2B"}
|
|
|
|
CMP %1, {fitcon, 0}
|
|
|
|
BMI {label, "1F"}
|
|
|
|
AND %b, %1, {fitcon, 31}
|
|
|
|
move {regS, %a, "LSL", %b}, %b
|
|
|
|
move {imS, %1, "LSR", 5}, %1
|
1990-11-12 15:36:03 +00:00
|
|
|
move %b, {st_regiSregrel, SP, "LSL", 2, %1}
|
1988-02-17 15:44:54 +00:00
|
|
|
LABEL {label, "1:"}
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat set !defined($1)
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
uses GENREG={fitcon,1}, GENREG={fitcon,0}, GENREG, GENREG
|
|
|
|
gen LDMFD {autoid, SP}, {reglist1, %c}
|
|
|
|
LDMFD {autoid, SP}, {reglist1, %d}
|
|
|
|
LABEL {label, "2:"}
|
|
|
|
STMFD {autoid, SP}, {reglist1, %b}
|
|
|
|
SUB_S %c, %c, {fitcon,4}
|
|
|
|
BGT {label, "2B"}
|
|
|
|
CMP %d, {fitcon, 0}
|
|
|
|
BMI {label, "1F"}
|
|
|
|
AND %b, %d, {fitcon, 31}
|
|
|
|
move {regS, %a, "LSL", %b}, %b
|
|
|
|
move {imS, %d, "LSR", 5}, %d
|
|
|
|
move %b, {st_regiSregrel, SP, "LSL", 2, %d}
|
|
|
|
LABEL {label, "1:"}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* *
|
|
|
|
* GROUP XI : Array Instructions *
|
|
|
|
* *
|
|
|
|
************************************************************************/
|
|
|
|
|
|
|
|
pat lae aar $2==4 && rom($1,3)==1 && rom($1,1)==0 leaving adi 4
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat lae aar $2==4 && rom($1,3)==1 && rom($1,1)>0 && legal(rom($1,1))
|
|
|
|
with GENREG
|
|
|
|
uses GENREG
|
|
|
|
gen SUB %a,%1,{fitcon,rom($1,1)} yields %a
|
|
|
|
leaving adi 4
|
|
|
|
with exact regconst yields {regconst, %1.reg,
|
|
|
|
%1.ind-rom($1,1)}
|
|
|
|
leaving adi 4
|
|
|
|
|
1988-02-17 15:44:54 +00:00
|
|
|
pat lae aar $2==4 && rom($1,3)==1 && rom($1,1)!=0
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG={const4, 0-rom($1,1)}
|
|
|
|
gen ADD %a,%1,%a yields %a
|
|
|
|
leaving adi 4
|
|
|
|
with exact regconst yields {regconst, %1.reg,
|
|
|
|
%1.ind-rom($1,1)}
|
1988-02-17 15:44:54 +00:00
|
|
|
leaving adi 4
|
|
|
|
|
|
|
|
pat lae aar $2==4 && rom($1,3)==4 && rom($1,1)==0
|
|
|
|
with GENREG yields {imS, %1,"LSL", 2}
|
|
|
|
leaving adi 4
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat lae aar $2==4 && rom($1,3)==4 && rom($1,1)>0 && legal(rom($1,1))
|
|
|
|
with GENREG
|
|
|
|
uses GENREG
|
|
|
|
gen SUB %a,%1,{fitcon, rom($1,1)} yields {imS, %a,"LSL", 2}
|
|
|
|
leaving adi 4
|
|
|
|
|
1988-02-17 15:44:54 +00:00
|
|
|
pat lae aar $2==4 && rom($1,3)==4 && rom($1,1)!=0
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG={const4, 0-rom($1,1)}
|
|
|
|
gen ADD %a,%1,%a yields {imS, %a,"LSL", 2}
|
1988-02-17 15:44:54 +00:00
|
|
|
leaving adi 4
|
|
|
|
|
|
|
|
pat lae aar $2==4 && rom($1,1)==0
|
1990-11-12 15:36:03 +00:00
|
|
|
leaving loc rom($1,3)
|
|
|
|
mli 4 adi 4
|
|
|
|
|
|
|
|
pat lae aar $2==4 && rom($1,1)>0 && legal(rom($1,1))
|
|
|
|
with GENREG
|
|
|
|
uses GENREG
|
|
|
|
gen SUB %a,%1,{fitcon,rom($1,1)} yields %a
|
|
|
|
leaving loc rom($1,3)
|
1988-02-17 15:44:54 +00:00
|
|
|
mli 4 adi 4
|
|
|
|
|
|
|
|
pat lae aar $2==4 && rom($1,1)!=0
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG={const4, 0-rom($1,1)}
|
|
|
|
gen ADD %a,%1,%a yields %a
|
|
|
|
leaving loc rom($1,3)
|
1988-02-17 15:44:54 +00:00
|
|
|
mli 4 adi 4
|
|
|
|
|
|
|
|
pat aar $1==4
|
|
|
|
with GENREG GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
gen move {regind, %1}, %a
|
|
|
|
SUB %2, %2, %a yields %2 {regrel, %1, 8}
|
|
|
|
leaving mli 4 adi 4
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat lae sar $2==4 && defined(rom($1,3)) leaving lae $1 aar 4
|
1988-02-17 15:44:54 +00:00
|
|
|
sti rom($1,3)
|
1990-11-12 15:36:03 +00:00
|
|
|
|
|
|
|
pat lae lar $2==4 && defined(rom($1,3)) leaving lae $1 aar 4
|
1988-02-17 15:44:54 +00:00
|
|
|
loi rom($1,3)
|
|
|
|
|
|
|
|
pat loc aar !defined($2) leaving aar $1
|
1990-11-12 15:36:03 +00:00
|
|
|
|
1988-02-17 15:44:54 +00:00
|
|
|
pat lae loc sar !defined($3) && $2==4 && defined(rom($1,3))
|
|
|
|
leaving lae $1 aar 4
|
|
|
|
sti rom($1,3)
|
1990-11-12 15:36:03 +00:00
|
|
|
|
1988-02-17 15:44:54 +00:00
|
|
|
pat lae loc lar !defined($3) && $2==4 && defined(rom($1,3))
|
|
|
|
leaving lae $1 aar 4
|
|
|
|
loi rom($1,3)
|
1990-11-12 15:36:03 +00:00
|
|
|
|
|
|
|
/* next two: dynamic arrays in modula2 - not tested */
|
|
|
|
|
|
|
|
pat lal sar $2==4 leaving lal $1 aar 4 lal $1 adp 8 loi 4 sts
|
|
|
|
|
|
|
|
pat lal lar $2==4 leaving lal $1 aar 4 lal $1 adp 8 loi 4 los
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* *
|
|
|
|
* GROUP XII : Compare Instructions *
|
|
|
|
* *
|
|
|
|
************************************************************************/
|
|
|
|
|
|
|
|
pat cmi
|
|
|
|
with GENREG REGcon
|
1990-11-12 15:36:03 +00:00
|
|
|
uses reusing %1, GENREG=%1
|
1988-02-17 15:44:54 +00:00
|
|
|
gen RSB_S %a, %1, %2 yields %a
|
|
|
|
with REGcon GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses reusing %2, GENREG=%2
|
1988-02-17 15:44:54 +00:00
|
|
|
gen SUB_S %a, %2, %1 yields %a
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat cmu $1==4
|
|
|
|
with GENREG REGcon
|
|
|
|
uses GENREG
|
|
|
|
gen CMP %1, %2
|
|
|
|
MOV_HI %a, {fitcon, 0-1}
|
|
|
|
MOV_LS %a, {fitcon, 1}
|
|
|
|
MOV_EQ %a, {fitcon, 0} yields %a
|
|
|
|
with REGcon GENREG
|
|
|
|
uses GENREG
|
|
|
|
gen CMP %2, %1
|
|
|
|
MOV_HI %a, {fitcon, 1}
|
|
|
|
MOV_LS %a, {fitcon, 0-1}
|
|
|
|
MOV_EQ %a, {fitcon, 0} yields %a
|
1988-02-17 15:44:54 +00:00
|
|
|
|
1988-02-18 11:17:39 +00:00
|
|
|
pat cmp leaving cmu 4
|
1988-02-17 15:44:54 +00:00
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat cmf $1==4 leaving cal ".cmf4" asp 8 lfr 4
|
|
|
|
pat cmf $1==8 leaving cal ".cmf8" asp 16 lfr 4
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat loc cms !defined($2) leaving cms $1
|
|
|
|
|
|
|
|
pat cms $1==4
|
|
|
|
with GENREG REGcon
|
|
|
|
gen EOR_S %1, %1, %2 yields %1
|
|
|
|
with REGcon GENREG
|
|
|
|
gen EOR_S %2, %2, %1 yields %2
|
|
|
|
|
|
|
|
pat cms $1!=4
|
|
|
|
with STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
kills ALL
|
|
|
|
uses GENREG = {const4, $1}, GENREG, GENREG, GENREG, GENREG
|
|
|
|
gen move %a, %e
|
|
|
|
ADD %b, %a, SP
|
1988-02-17 15:44:54 +00:00
|
|
|
LABEL {label, "1:"}
|
|
|
|
SUB_S %a, %a, {fitcon, 4}
|
|
|
|
BLT {label, "2F"}
|
1990-11-12 15:36:03 +00:00
|
|
|
move {st_regregrel, SP, %a}, %c
|
1988-02-17 15:44:54 +00:00
|
|
|
move {regregrel, %b, %a}, %d
|
|
|
|
EOR_S %c, %c, %d
|
|
|
|
BEQ {label, "1B"}
|
|
|
|
LABEL {label, "2:"}
|
1990-11-12 15:36:03 +00:00
|
|
|
ADD SP, %b, %e yields %c
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat cms !defined($1)
|
|
|
|
with GENREG STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG, GENREG, GENREG, GENREG
|
|
|
|
gen move %1, %d
|
|
|
|
ADD %a, %1, SP
|
1988-02-17 15:44:54 +00:00
|
|
|
LABEL {label, "1:"}
|
|
|
|
SUB_S %1, %1, {fitcon, 4}
|
|
|
|
BLT {label, "2F"}
|
1990-11-12 15:36:03 +00:00
|
|
|
move {st_regregrel, SP, %1}, %b
|
1988-02-17 15:44:54 +00:00
|
|
|
move {regregrel, %a, %1}, %c
|
|
|
|
EOR_S %b, %b, %c
|
|
|
|
BEQ {label, "1B"}
|
|
|
|
LABEL {label, "2:"}
|
1990-11-12 15:36:03 +00:00
|
|
|
ADD SP, %a, %d yields %b
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat tlt
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses reusing %1, GENREG=%1
|
1988-02-17 15:44:54 +00:00
|
|
|
gen test %1
|
|
|
|
MOV_LT %a, {fitcon,1}
|
|
|
|
MOV_GE %a, {fitcon,0} yields %a
|
|
|
|
|
|
|
|
pat tle
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses reusing %1, GENREG=%1
|
1988-02-17 15:44:54 +00:00
|
|
|
gen test %1
|
|
|
|
MOV_LE %a, {fitcon,1}
|
|
|
|
MOV_GT %a, {fitcon,0} yields %a
|
|
|
|
|
|
|
|
pat teq
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses reusing %1, GENREG=%1
|
1988-02-17 15:44:54 +00:00
|
|
|
gen test %1
|
|
|
|
MOV_EQ %a, {fitcon,1}
|
|
|
|
MOV_NE %a, {fitcon,0} yields %a
|
|
|
|
|
|
|
|
pat tne
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses reusing %1, GENREG=%1
|
1988-02-17 15:44:54 +00:00
|
|
|
gen test %1
|
|
|
|
MOV_NE %a, {fitcon,1}
|
|
|
|
MOV_EQ %a, {fitcon,0} yields %a
|
|
|
|
|
|
|
|
pat tge
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses reusing %1, GENREG=%1
|
1988-02-17 15:44:54 +00:00
|
|
|
gen test %1
|
|
|
|
MOV_GE %a, {fitcon,1}
|
|
|
|
MOV_LT %a, {fitcon,0} yields %a
|
|
|
|
|
|
|
|
pat tgt
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
uses reusing %1, GENREG=%1
|
1988-02-17 15:44:54 +00:00
|
|
|
gen test %1
|
|
|
|
MOV_GT %a, {fitcon,1}
|
|
|
|
MOV_LE %a, {fitcon,0} yields %a
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* *
|
|
|
|
* GROUP XIII : Branch Instructions *
|
|
|
|
* *
|
|
|
|
************************************************************************/
|
|
|
|
|
|
|
|
pat bra
|
|
|
|
with STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
kills ALL
|
1988-02-17 15:44:54 +00:00
|
|
|
gen BAL {label, $1}
|
|
|
|
|
|
|
|
pat bne
|
|
|
|
with REGcon GENREG STACK
|
|
|
|
gen CMP %2, %1
|
|
|
|
BNE {label, $1}
|
|
|
|
with GENREG REGcon STACK
|
|
|
|
gen CMP %1, %2
|
|
|
|
BNE {label, $1}
|
|
|
|
|
|
|
|
pat beq
|
|
|
|
with REGcon GENREG STACK
|
|
|
|
gen CMP %2, %1
|
|
|
|
BEQ {label, $1}
|
|
|
|
with GENREG REGcon STACK
|
|
|
|
gen CMP %1, %2
|
|
|
|
BEQ {label, $1}
|
|
|
|
|
|
|
|
pat blt
|
|
|
|
with REGcon GENREG STACK
|
|
|
|
gen CMP %2, %1
|
|
|
|
BLT {label, $1}
|
|
|
|
|
|
|
|
pat ble
|
|
|
|
with REGcon GENREG STACK
|
|
|
|
gen CMP %2, %1
|
|
|
|
BLE {label, $1}
|
|
|
|
|
|
|
|
pat bgt
|
|
|
|
with REGcon GENREG STACK
|
|
|
|
gen CMP %2, %1
|
|
|
|
BGT {label, $1}
|
|
|
|
|
|
|
|
pat bge
|
|
|
|
with REGcon GENREG STACK
|
|
|
|
gen CMP %2, %1
|
|
|
|
BGE {label, $1}
|
|
|
|
|
|
|
|
pat zlt
|
|
|
|
with GENREG STACK
|
|
|
|
gen test %1
|
|
|
|
BLT {label, $1}
|
|
|
|
|
|
|
|
pat zle
|
|
|
|
with GENREG STACK
|
|
|
|
gen test %1
|
|
|
|
BLE {label, $1}
|
|
|
|
|
|
|
|
pat zeq
|
|
|
|
with GENREG STACK
|
|
|
|
gen test %1
|
|
|
|
BEQ {label, $1}
|
|
|
|
|
|
|
|
pat zne
|
|
|
|
with GENREG STACK
|
|
|
|
gen test %1
|
|
|
|
BNE {label, $1}
|
|
|
|
|
|
|
|
pat zge
|
|
|
|
with GENREG STACK
|
|
|
|
gen test %1
|
|
|
|
BGE {label, $1}
|
|
|
|
|
|
|
|
pat zgt
|
|
|
|
with GENREG STACK
|
|
|
|
gen test %1
|
|
|
|
BGT {label, $1}
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* *
|
|
|
|
* GROUP XIV : Procedure Call *
|
|
|
|
* *
|
|
|
|
************************************************************************/
|
|
|
|
|
|
|
|
pat cal
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
gen BAL_L {label, $1}
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat cai
|
|
|
|
with GENREG STACK
|
|
|
|
kills ALL
|
|
|
|
gen /* the trick is to set up R14 properly */
|
|
|
|
ADR LR, {label, "1F"}
|
|
|
|
MOV PC, %1
|
|
|
|
LABEL {label, "1:"}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat lfr $1==4 yields R0
|
|
|
|
|
|
|
|
pat lfr $1==8 yields R1 R0
|
|
|
|
|
|
|
|
pat lfr $1==12 yields R2 R1 R0
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat ret $1==0
|
1988-02-17 15:44:54 +00:00
|
|
|
with STACK
|
|
|
|
kills ALL
|
1990-11-12 15:36:03 +00:00
|
|
|
gen return
|
|
|
|
MOV SP, LB
|
|
|
|
LDMFD {autoid, SP}, {lb_pc_reglist2, LB, PC}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat ret $1==4
|
|
|
|
with address STACK
|
|
|
|
kills ALL
|
|
|
|
gen move %1, R0
|
1990-11-12 15:36:03 +00:00
|
|
|
return
|
1988-02-17 15:44:54 +00:00
|
|
|
move LB, SP
|
1990-11-12 15:36:03 +00:00
|
|
|
LDMFD {autoid, SP}, {lb_pc_reglist2, LB, PC}
|
1988-02-17 15:44:54 +00:00
|
|
|
with REGcon STACK
|
|
|
|
kills ALL
|
|
|
|
gen move %1, R0
|
1990-11-12 15:36:03 +00:00
|
|
|
return
|
1988-02-17 15:44:54 +00:00
|
|
|
move LB, SP
|
1990-11-12 15:36:03 +00:00
|
|
|
LDMFD {autoid, SP}, {lb_pc_reglist2, LB, PC}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat ret $1==8
|
|
|
|
with REGcon REGcon STACK
|
|
|
|
kills ALL
|
|
|
|
gen move %1, R0
|
|
|
|
move %2, R1
|
1990-11-12 15:36:03 +00:00
|
|
|
return
|
1988-02-17 15:44:54 +00:00
|
|
|
move LB, SP
|
1990-11-12 15:36:03 +00:00
|
|
|
LDMFD {autoid, SP}, {lb_pc_reglist2, LB, PC}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat ret $1==12
|
|
|
|
with REGcon REGcon REGcon STACK
|
|
|
|
kills ALL
|
|
|
|
gen move %1, R0
|
|
|
|
move %2, R1
|
|
|
|
move %3, R2
|
1990-11-12 15:36:03 +00:00
|
|
|
return
|
1988-02-17 15:44:54 +00:00
|
|
|
move LB, SP
|
1990-11-12 15:36:03 +00:00
|
|
|
LDMFD {autoid, SP}, {lb_pc_reglist2, LB, PC}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
|
|
|
|
/************************************************************************
|
|
|
|
* *
|
|
|
|
* GROUP XV : Miscellaneous *
|
|
|
|
* *
|
|
|
|
************************************************************************/
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat asp legal($1)
|
1988-02-17 15:44:54 +00:00
|
|
|
with STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
kills ALL
|
|
|
|
gen ADD SP, SP, {fitcon, $1}
|
|
|
|
|
1990-11-13 14:52:51 +00:00
|
|
|
pat asp
|
1990-11-12 15:36:03 +00:00
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
uses GENREG={const4, $1}
|
|
|
|
gen ADD SP, SP, %a
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat ass $1==4
|
|
|
|
with REGcon STACK
|
|
|
|
gen ADD SP, SP, %1
|
|
|
|
|
|
|
|
pat blm $1==0
|
|
|
|
with address+REGcon address+REGcon
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat blm $1==1
|
|
|
|
with GENREG GENREG
|
|
|
|
kills address
|
|
|
|
uses GENREG
|
|
|
|
gen LDR_B %a, {regind, %2}
|
|
|
|
STR_B %a, {regind, %1}
|
|
|
|
|
1988-02-17 15:44:54 +00:00
|
|
|
pat blm $1==4
|
|
|
|
with GENREG GENREG
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
gen move {regind, %2}, %a
|
|
|
|
move %a, {regind, %1}
|
|
|
|
|
|
|
|
pat blm $1>4
|
|
|
|
with GENREG GENREG
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG, GENREG={const4, $1-4}
|
1988-02-17 15:44:54 +00:00
|
|
|
gen LABEL {label, "1:"}
|
|
|
|
move {regregrel, %2, %b}, %a
|
|
|
|
move %a, {regregrel, %1, %b}
|
|
|
|
SUB_S %b, %b, {fitcon, 4}
|
|
|
|
BGE {label,"1B"}
|
|
|
|
|
|
|
|
pat bls $1==4
|
|
|
|
with GENREG GENREG GENREG
|
|
|
|
kills address
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
gen LABEL {label, "1:"}
|
|
|
|
SUB_S %1, %1, {fitcon, 4}
|
|
|
|
move {regregrel, %3, %1}, %a
|
|
|
|
move %a, {regregrel, %2, %1}
|
|
|
|
BGT {label,"1B"}
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat csa $1==4
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
gen BAL_L {label, "_Csa"}
|
|
|
|
move R2, PC
|
1988-02-17 15:44:54 +00:00
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat csb $1==4
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
gen BAL_L {label, "_Csb"}
|
|
|
|
move R3, PC
|
1988-02-17 15:44:54 +00:00
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat dch leaving loi 4
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat dup $1==4
|
|
|
|
with address+REGcon yields %1 %1
|
|
|
|
|
|
|
|
pat dup $1==8
|
|
|
|
with address+REGcon address+REGcon yields %2 %1 %2 %1
|
|
|
|
|
|
|
|
pat dup $1>8
|
|
|
|
with STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
kills ALL
|
|
|
|
uses GENREG={const4,$1}, GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
gen LABEL {label, "1:"}
|
1990-11-12 15:36:03 +00:00
|
|
|
move {st_regrel, SP, $1-4}, %b
|
|
|
|
STMFD {autoid, SP}, {reglist1, %b}
|
1988-02-17 15:44:54 +00:00
|
|
|
SUB_S %a, %a, {fitcon, 4}
|
|
|
|
BGT {label, "1B"}
|
|
|
|
|
|
|
|
pat dus
|
|
|
|
with GENREG STACK
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG, GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
gen SUB %b, %1, {fitcon, 4}
|
|
|
|
LABEL {label, "1:"}
|
1990-11-12 15:36:03 +00:00
|
|
|
move {st_regregrel, SP, %b}, %a
|
|
|
|
STMFD {autoid, SP}, {reglist1, %a}
|
1988-02-17 15:44:54 +00:00
|
|
|
SUB_S %1, %1, {fitcon, 4}
|
|
|
|
BGT {label, "1B"}
|
|
|
|
|
|
|
|
pat exg $1==4
|
|
|
|
with address+REGcon address+REGcon yields %1 %2
|
|
|
|
|
|
|
|
pat exg $1==8
|
|
|
|
with address+REGcon address+REGcon
|
|
|
|
address+REGcon address+REGcon yields %2 %1 %4 %3
|
|
|
|
|
|
|
|
pat exg $1>8
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG, GENREG, GENREG={const4, $1-4}, GENREG, GENREG={const4, $1}
|
|
|
|
gen ADD %d, SP, %e
|
1988-02-17 15:44:54 +00:00
|
|
|
LABEL {label, "1:"}
|
1990-11-12 15:36:03 +00:00
|
|
|
move {st_regregrel, SP,%c}, %a
|
1988-02-17 15:44:54 +00:00
|
|
|
move {regregrel,%d,%c}, %b
|
|
|
|
move %a, {regregrel,%d,%c}
|
1990-11-12 15:36:03 +00:00
|
|
|
move %b, {st_regregrel, SP,%c}
|
1988-02-17 15:44:54 +00:00
|
|
|
SUB_S %c, %c, {fitcon, 4}
|
|
|
|
BGE {label, "1B"}
|
|
|
|
|
|
|
|
pat fil
|
1990-11-12 15:36:03 +00:00
|
|
|
uses GENREG
|
|
|
|
gen move {addr_external,$1}, %a
|
|
|
|
move %a, {addr_external, "_Filna"}
|
|
|
|
|
|
|
|
pat gto /* this code does NOT restore registers */
|
|
|
|
uses GENREG,GENREG,GENREG,GENREG
|
|
|
|
gen move {addr_external, $1}, %d
|
|
|
|
move {regind, %d}, %a
|
|
|
|
move {regrel, %d, 4}, %b
|
|
|
|
move {regrel, %d, 8}, %c
|
|
|
|
MOV LB, %c
|
|
|
|
MOV SP, %b
|
|
|
|
MOV PC, %a
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat lin
|
1990-11-12 15:36:03 +00:00
|
|
|
kills address
|
|
|
|
uses GENREG={const4,$1}
|
|
|
|
gen move %a,{addr_external,"_Lineno"}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat lni
|
1990-11-12 15:36:03 +00:00
|
|
|
kills address
|
|
|
|
uses GENREG
|
|
|
|
gen move {addr_external,"_Lineno"}, %a
|
|
|
|
LDR %a, {regind, %a}
|
|
|
|
ADD %a,%a,{fitcon,1}
|
|
|
|
move %a,{addr_external,"_Lineno"}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat lor $1==0 yields LB
|
|
|
|
|
|
|
|
pat lor $1==1
|
1990-11-12 15:36:03 +00:00
|
|
|
with STACK
|
|
|
|
kills ALL yields SP
|
1988-02-17 15:44:54 +00:00
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
pat lor $1==2 yields {absolute, "_RegHp"}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat lpb leaving adp 8
|
|
|
|
|
|
|
|
pat nop
|
1991-09-04 10:55:52 +00:00
|
|
|
kills ALL
|
1990-11-12 15:36:03 +00:00
|
|
|
gen MOV_NV R0,R0
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat rck
|
1990-11-12 15:36:03 +00:00
|
|
|
with GENREG REGcon STACK
|
|
|
|
uses GENREG,GENREG
|
1988-02-17 15:44:54 +00:00
|
|
|
gen move {regind, %1}, %a
|
1990-11-12 15:36:03 +00:00
|
|
|
/* for some reason, the code generator expects the value
|
|
|
|
* to be checked on top of the stack after checking, while
|
|
|
|
* in fact it is held in %2. This causes mayhem later on, and
|
|
|
|
* the following two lines rectify this.
|
|
|
|
*/
|
|
|
|
move %2,%b
|
|
|
|
STMFD {autoid, SP}, {reglist1, %b}
|
1988-02-17 15:44:54 +00:00
|
|
|
CMP %a, %2
|
1990-11-12 15:36:03 +00:00
|
|
|
BGT {label, "_RckTrap"}
|
1988-02-17 15:44:54 +00:00
|
|
|
move {regrel, %1, 4}, %a
|
|
|
|
CMP %a, %2
|
1990-11-12 15:36:03 +00:00
|
|
|
BLT {label, "_RckTrap"}
|
|
|
|
|
|
|
|
pat lim
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
uses GENREG
|
|
|
|
gen move {addr_external, "_IgnoreMask"}, %a
|
|
|
|
STMFD {autoid, SP}, {reglist1, %a}
|
|
|
|
|
|
|
|
pat mon
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
gen BAL_L {label, "_EmMon"}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat rtt
|
1990-11-12 15:36:03 +00:00
|
|
|
leaving ret 0
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat sig
|
1990-11-12 15:36:03 +00:00
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
uses GENREG,GENREG
|
|
|
|
gen move {addr_external, "_TrpReg"}, %a
|
|
|
|
LDR %a, {regind, %a}
|
|
|
|
LDMFD {autoid, SP}, {reglist1, %b}
|
|
|
|
move %b, {addr_external, "_TrpReg"}
|
|
|
|
STMFD {autoid, SP}, {reglist1, %a}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat sim
|
1990-11-12 15:36:03 +00:00
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
uses GENREG
|
|
|
|
gen LDMFD {autoid, SP}, {reglist1, %a}
|
|
|
|
move %a, {addr_external, "_IgnoreMask"}
|
|
|
|
|
|
|
|
pat trp
|
|
|
|
with STACK
|
|
|
|
kills ALL
|
|
|
|
gen BAL_L {label, "_EmTrp"}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat str $1==0
|
|
|
|
with address
|
|
|
|
gen move %1, LB
|
|
|
|
with REGcon
|
|
|
|
gen move %1, LB
|
|
|
|
|
|
|
|
pat str $1==1
|
|
|
|
with address
|
1990-11-12 15:36:03 +00:00
|
|
|
gen MOV SP, %1
|
1988-02-17 15:44:54 +00:00
|
|
|
with REGcon
|
1990-11-12 15:36:03 +00:00
|
|
|
gen MOV SP, %1
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat str $1==2
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
gen move %1, {absolute, "_RegHp"}
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
/***********************************************************************/
|
|
|
|
|
1990-11-12 15:36:03 +00:00
|
|
|
/* code for *p++ and *p-- (integers)*/
|
1988-02-17 15:44:54 +00:00
|
|
|
pat lol lol adp stl loi $1==$2 && $2==$4 && $5==4
|
1990-11-12 15:36:03 +00:00
|
|
|
kills GENREG
|
|
|
|
uses GENREG, GENREG
|
|
|
|
gen move {lb_local, $1}, %a
|
|
|
|
LDR %b, {regrelpi, %a, $5}
|
|
|
|
STR %a, {lb_local, $1} yields %b
|
1988-02-17 15:44:54 +00:00
|
|
|
|
|
|
|
pat lol lol adp stl sti $1==$2 && $2==$4 && $5==4
|
|
|
|
with GENREG
|
1990-11-12 15:36:03 +00:00
|
|
|
kills GENREG
|
|
|
|
uses GENREG
|
|
|
|
gen move {lb_local,$1}, %a
|
|
|
|
STR %1, {regrelpi, %a, $5}
|
|
|
|
STR %a, {lb_local, $1}
|
|
|
|
|
|
|
|
/* code for *p++ and *p-- (bytes)*/
|
|
|
|
pat lol lol adp stl loi $1==$2 && $2==$4 && $5==1
|
|
|
|
kills GENREG
|
|
|
|
uses GENREG, GENREG
|
|
|
|
gen move {lb_local, $1}, %a
|
|
|
|
LDR_B %b, {regrelpi, %a, $5}
|
|
|
|
STR %a, {lb_local, $1} yields %b
|
|
|
|
|
|
|
|
pat lol lol adp stl sti $1==$2 && $2==$4 && $5==1
|
|
|
|
with GENREG
|
|
|
|
kills GENREG
|
|
|
|
uses GENREG
|
|
|
|
gen move {lb_local,$1}, %a
|
|
|
|
STR_B %1, {regrelpi, %a, $5}
|
|
|
|
STR %a, {lb_local, $1}
|
|
|
|
|
|
|
|
/* code for *pp->p++ and *pp->p-- (integers)*/
|
|
|
|
pat lil lil adp sil loi $1==$2 && $2==$4 && $5==4
|
|
|
|
kills GENREG
|
|
|
|
uses GENREG, GENREG, GENREG
|
|
|
|
gen move {lb_local, $1}, %a
|
|
|
|
LDR %b, {regind, %a}
|
|
|
|
ADD %c, %b, {fitcon, $5}
|
|
|
|
STR %c, {regind, %a}
|
|
|
|
LDR %c, {regind, %b} yields %c
|
|
|
|
|
|
|
|
pat lil lil adp sil sti $1==$2 && $2==$4 && $5==4
|
|
|
|
with GENREG
|
|
|
|
kills GENREG
|
|
|
|
uses GENREG, GENREG, GENREG
|
|
|
|
gen move {lb_local, $1}, %a
|
|
|
|
LDR %b, {regind, %a}
|
|
|
|
ADD %c, %b, {fitcon, $5}
|
|
|
|
STR %c, {regind, %a}
|
|
|
|
STR %1, {regind, %b}
|
|
|
|
|
|
|
|
/* code for *pp->p++ and *pp->p-- (bytes)*/
|
|
|
|
pat lil lil adp sil loi $1==$2 && $2==$4 && $5==1
|
|
|
|
kills GENREG
|
|
|
|
uses GENREG, GENREG, GENREG
|
|
|
|
gen move {lb_local, $1}, %a
|
|
|
|
LDR %b, {regind, %a}
|
|
|
|
ADD %c, %b, {fitcon, $5}
|
|
|
|
STR %c, {regind, %a}
|
|
|
|
LDR_B %c, {regind, %b} yields %c
|
|
|
|
|
|
|
|
pat lil lil adp sil sti $1==$2 && $2==$4 && $5==1
|
|
|
|
with GENREG
|
|
|
|
kills GENREG
|
|
|
|
uses GENREG, GENREG, GENREG
|
|
|
|
gen move {lb_local, $1}, %a
|
|
|
|
LDR %b, {regind, %a}
|
|
|
|
ADD %c, %b, {fitcon, $5}
|
|
|
|
STR %c, {regind, %a}
|
|
|
|
STR_B %1, {regind, %b}
|
|
|
|
|
|
|
|
|
|
|
|
/* global array access of the form x[y-1] */
|
|
|
|
|
|
|
|
pat lol loc mli loc sbi $2==$4 && $3==4 && $5==4
|
|
|
|
leaving lol $1 dec 4 loc $2 mli 4
|
|
|
|
|
|
|
|
/* x[i] = y with large array elements */
|
|
|
|
|
|
|
|
pat lae loi lae lol loc mli ads sti $2==$8 && $2 > 4
|
|
|
|
leaving lae $1 lae $3 lol $4 loc $5 mli $6 ads $7 blm $8
|
|
|
|
pat lae loi lae lol loc mlu ads sti $2==$8 && $2 > 4
|
|
|
|
leaving lae $1 lae $3 lol $4 loc $5 mlu $6 ads $7 blm $8
|
|
|
|
|
|
|
|
/* prevent double push/pull of $1 */
|
|
|
|
|
|
|
|
pat lae lol loc mli ads
|
|
|
|
leaving lol $2 loc $3 mli $4 lae $1 ads $5
|
|
|
|
pat lae lol loc mlu ads
|
|
|
|
leaving lol $2 loc $3 mlu $4 lae $1 ads $5
|
|
|
|
|
|
|
|
pat lae lol loc mli ads lol loc mli ads $5==$9 && $4==$8
|
|
|
|
leaving lol $2 loc $3 mli $4 lol $6 loc $7 mli $8 ads $5 lae $1 ads $9
|
|
|
|
pat lae lol loc mlu ads lol loc mlu ads $5==$9 && $4==$8
|
|
|
|
leaving lol $2 loc $3 mlu $4 lol $6 loc $7 mlu $8 ads $5 lae $1 ads $9
|
|
|
|
|
|
|
|
pat lae lol adp loi loc mli ads
|
|
|
|
leaving lol $2 adp $3 loi $4 loc $5 mli $6 lae $1 ads $7
|
|
|
|
pat lae lol adp loi loc mlu ads
|
|
|
|
leaving lol $2 adp $3 loi $4 loc $5 mlu $6 lae $1 ads $7
|
|
|
|
|
|
|
|
/*
|
|
|
|
pat lae loi lae lol adp loi loc mli ads sti $2==$10 && $2 > 4
|
|
|
|
leaving lae $1 lae $3 lol $4 adp $5 loi $6 loc $7 mli $8 ads $9 blm $2
|
|
|
|
pat lae loi lae lol adp loi loc mlu ads sti $2==$10 && $2 > 4
|
|
|
|
leaving lae $1 lae $3 lol $4 adp $5 loi $6 loc $7 mlu $8 ads $9 blm $2
|
|
|
|
*/
|