1988-11-08 14:09:24 +00:00
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adc dst:REG, src:EADDR ==> @text1( 0x13);
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mod_RM( dst->reg, src).
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add dst:REG, src:EADDR ==> @text1( 0x3);
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mod_RM( dst->reg, src).
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... dst:ACCU, src:DATA ==> @text1( 0x5);
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@text2( %$(src->expr)).
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... dst:EADDR, src:DATA ==> @text1( 0x81);
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mod_RM( 0, dst);
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@text2( %$(src->expr)).
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... dst:ACCU, src:lABEL ==> @text1( 0x5);
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@reloc2( %$(src->lab), %$(src->off), !PC_REL).
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... dst:EADDR, src:lABEL ==> @text1( 0x81);
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mod_RM( 0, dst);
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@reloc2( %$(src->lab), %$(src->off), !PC_REL).
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and dst:REG, src:EADDR ==> @text1( 0x23);
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mod_RM( dst->reg, src).
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... dst:ACCU, src:DATA ==> @text1( 0x25);
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@text2( %$(src->expr)).
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call dst:lABEL ==> @text1( 0xe8);
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@reloc2( %$(dst->lab), %$(dst->off), PC_REL).
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... dst:EADDR ==> @text1( 0xff);
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mod_RM( 2, dst).
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cmp dst:REG, src:EADDR ==> @text1( 0x3b);
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mod_RM( dst->reg, src).
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... dst:ACCU, src:DATA ==> @text1( 0x3d);
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@text2( %$(src->expr)).
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1989-02-07 11:42:28 +00:00
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... dst:EADDR, src:DATA ==> @text1( 0x81);
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mod_RM(7,dst);
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@text2( %$(src->expr)).
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1988-11-08 14:09:24 +00:00
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cwd ==> @text1( 0x99).
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dec dst:REG ==> R53( 9, dst->reg).
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... dst:EADDR ==> @text1( 0xff);
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mod_RM( 1, dst).
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div divisor:EADDR ==> @text1( 0xf7);
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mod_RM( 6, divisor).
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idiv divisor:EADDR ==> @text1( 0xf7);
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mod_RM( 7, divisor).
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inc dst:REG ==> R53( 8, dst->reg).
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... dst:EADDR ==> @text1( 0xff);
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mod_RM( 0, dst).
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jb dst:ILB ==> @text1( 0x72);
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@text1( %dist( dst->lab)).
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je dst:ILB ==> @text1( 0x74);
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@text1( %dist( dst->lab)).
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... dst:lABEL ==> save_op( dst);
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assemble( "jne 9f");
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jmp_instr( &saved_op);
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assemble( "9:").
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jg dst:ILB ==> @text1( 0x7f);
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@text1( %dist( dst->lab)).
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... dst:lABEL ==> save_op( dst);
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assemble( "jle 9f");
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jmp_instr( &saved_op);
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assemble( "9:").
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jge dst:ILB ==> @text1( 0x7d);
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@text1( %dist( dst->lab)).
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... dst:lABEL ==> save_op( dst);
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assemble( "jl 9f");
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jmp_instr( &saved_op);
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assemble( "9:").
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jl dst:ILB ==> @text1( 0x7c);
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@text1( %dist( dst->lab)).
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... dst:lABEL ==> save_op( dst);
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assemble( "jge 9f");
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jmp_instr( &saved_op);
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assemble( "9:").
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jle dst:ILB ==> @text1( 0x7e);
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@text1( %dist( dst->lab)).
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... dst:lABEL ==> save_op( dst);
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assemble( "jg 9f");
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jmp_instr( &saved_op);
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assemble( "9:").
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jmp dst:ILB ==> @text1( 0xeb);
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@text1( %dist( dst->lab)).
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... dst:lABEL ==> @text1( 0xe9);
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@reloc2( %$(dst->lab), %$(dst->off), PC_REL).
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jne dst:ILB ==> @text1( 0x75);
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@text1( %dist( dst->lab)).
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... dst:lABEL ==> save_op( dst);
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assemble( "je 9f");
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jmp_instr( &saved_op);
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assemble( "9:").
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lea dst:REG, src:EADDR ==> @text1( 0x8d);
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mod_RM( dst->reg, src).
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loop dst:ILB ==> @text1( 0xe2);
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@text1( %dist( dst->lab)).
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mov dst:REG, src:EADDR ==> mov_REG_EADDR( dst, src).
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... dst:REG, src:DATA ==> R53( 0x17, dst->reg);
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@text2( %$(src->expr)).
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... dst:REG, src:lABEL ==> R53( 0x17, dst->reg);
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@reloc2( %$(src->lab), %$(src->off), !PC_REL).
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... dst:EADDR, src:REG ==> @text1( 0x89);
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mod_RM( src->reg, dst).
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... dst:EADDR, src:DATA ==> @text1( 0xc7);
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mod_RM( 0, dst);
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@text2( %$(src->expr)).
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... dst:EADDR, src:lABEL ==> @text1( 0xc7);
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mod_RM( 0, dst);
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@reloc2( %$(src->lab), %$(src->off), !PC_REL).
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movb dst:REG, src:EADDR ==> @text1( 0x8a);
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mod_RM( dst->reg, src).
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... dst:EADDR, src:REG ==> @text1( 0x88);
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mod_RM( src->reg, dst).
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mul mplier:EADDR ==> @text1( 0xf7);
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mod_RM( 4, mplier).
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neg dst:EADDR ==> @text1( 0xf7);
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mod_RM( 3, dst).
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not dst:EADDR ==> @text1( 0xf7);
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mod_RM( 2, dst).
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or dst:REG, src:EADDR ==> @text1( 0x0b);
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mod_RM( dst->reg, src).
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pop dst:REG ==> R53( 0xb, dst->reg).
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... dst:EADDR ==> @text1( 0x8f);
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mod_RM( 0, dst).
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POP dst ==> @if ( push_waiting)
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mov_instr( dst, AX_oper);
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@assign( push_waiting, FALSE).
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@else
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pop_instr( dst).
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@fi.
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push src:REG ==> R53( 0xa, src->reg).
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... src:EADDR ==> @text1( 0xff);
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mod_RM( 6, src).
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PUSH src ==> mov_instr( AX_oper, src);
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@assign( push_waiting, TRUE).
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rcr dst:EADDR, src:CONST1 ==> @text1( 0xd1);
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mod_RM( 3, dst).
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rep ins:MOVS ==> @text1( 0xf3);
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@text1( 0xa5). /* Wie zet direction flag? */
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ret ==> @text1( 0xc3). /* Altijd NEAR! */
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rol dst:EADDR, src:REG_CL ==> @text1( 0xd3);
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mod_RM( 0, dst).
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ror dst:EADDR, src:REG_CL ==> @text1( 0xd3);
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mod_RM( 1, dst).
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sal dst:EADDR, src:REG_CL ==> @text1( 0xd3);
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mod_RM( 4, dst).
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sar dst:EADDR, src:REG_CL ==> @text1( 0xd3);
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mod_RM( 7, dst).
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... dst:EADDR, src:CONST1 ==> @text1( 0xd1);
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mod_RM( 7, dst).
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sbb dst:REG, src:EADDR ==> @text1( 0x1b);
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mod_RM( dst->reg, src).
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... dst:ACCU, src:DATA ==> @text1( 0x1d);
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@text2( %$(src->expr)).
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shl dst, src ==> sal_instr( dst, src).
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shr dst:EADDR, src:REG_CL ==> @text1( 0xd3);
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mod_RM( 5, dst).
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... dst:EADDR, src:CONST1 ==> @text1( 0xd1);
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mod_RM( 5, dst).
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sub dst:REG, src:EADDR ==> @text1( 0x2b);
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mod_RM( dst->reg, src).
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... dst:EADDR, src:DATA ==> @text1( 0x81);
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mod_RM( 5, dst);
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@text2( %$(src->expr)).
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test dst:REG, src:EADDR ==> @text1( 0x85);
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mod_RM( dst->reg, src).
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xchg dst:EADDR, src:REG ==> @text1( 0x87);
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mod_RM( src->reg, dst).
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xor dst:REG, src:EADDR ==> @text1( 0x33);
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mod_RM( dst->reg, src).
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