366 lines
9.5 KiB
C
366 lines
9.5 KiB
C
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#define RCSID3 "$Header$"
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/*
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** Zilog z8000 keywords
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*/
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0, R8, 8, "RL0",
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0, R8, 0, "RH0",
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0, R8, 9, "RL1",
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0, R8, 1, "RH1",
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0, R8, 10, "RL2",
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0, R8, 2, "RH2",
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0, R8, 11, "RL3",
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0, R8, 3, "RH3",
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0, R8, 12, "RL4",
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0, R8, 4, "RH4",
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0, R8, 13, "RL5",
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0, R8, 5, "RH5",
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0, R8, 14, "RL6",
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0, R8, 6, "RH6",
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0, R8, 15, "RL7",
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0, R8, 7, "RH7",
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/* Special format for some byte-registers. Not really available on
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** the z8000 but designed to ease writing a z8000-backend-table.
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** LR[0..7] are equivalent with RL[0..7].
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*/
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0, R8, 8, "LR0",
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0, R8, 9, "LR1",
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0, R8, 10, "LR2",
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0, R8, 11, "LR3",
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0, R8, 12, "LR4",
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0, R8, 13, "LR5",
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0, R8, 14, "LR6",
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0, R8, 15, "LR7",
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0, R16, 0, "R0",
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0, R16, 1, "R1",
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0, R16, 2, "R2",
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0, R16, 3, "R3",
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0, R16, 4, "R4",
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0, R16, 5, "R5",
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0, R16, 6, "R6",
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0, R16, 7, "R7",
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0, R16, 8, "R8",
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0, R16, 9, "R9",
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0, R16, 10, "R10",
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0, R16, 11, "R11",
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0, R16, 12, "R12",
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0, R16, 13, "R13",
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0, R16, 14, "R14",
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0, R16, 15, "R15",
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0, R32, 0, "RR0",
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0, R32, 2, "RR2",
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0, R32, 4, "RR4",
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0, R32, 6, "RR6",
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0, R32, 8, "RR8",
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0, R32, 10, "RR10",
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0, R32, 12, "RR12",
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0, R32, 14, "RR14",
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0, R64, 0, "RQ0",
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0, R64, 4, "RQ4",
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0, R64, 8, "RQ8",
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0, R64, 12, "RQ12",
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0, CC, 14, "NZ",
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0, CC, 15, "NC",
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0, CC, 13, "PL",
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0, CC, 5, "MI",
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0, CC, 14, "NE",
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0, CC, 6, "EQ",
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0, CC, 4, "OV",
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0, CC, 12, "NOV",
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0, CC, 4, "PE",
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0, CC, 12, "PO",
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0, CC, 9, "GE",
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0, CC, 1, "LT",
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0, CC, 10, "GT",
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0, CC, 2, "LE",
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0, CC, 15, "UGE",
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0, CC, 7, "ULT",
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0, CC, 11, "UGT",
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0, CC, 3, "ULE",
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0, FLAG, 0x80, "C",
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0, FLAG, 0x40, "Z",
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0, FLAG, 0x20, "S",
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0, FLAG, 0x10, "P",
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0, FLAG, 0x10, "V",
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0, INTCB, 2, "VI",
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0, INTCB, 1, "NVI",
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0, CTLRFLAGS, 1, "FLAGS",
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0, CTLR, 2, "FCW",
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0, CTLR, 3, "REFRESH",
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0, CTLR, 4, "PSAPSEG",
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0, CTLR, 5, "PSAPOFF",
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0, CTLR, 6, "NSPSEG",
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0, CTLR, 7, "NSPOFF",
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0, CTLR, 5, "PSAP",
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0, CTLR, 7, "NSP",
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/* TYPE_11a23 */
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0, F1_1F2_3, 0x1F00, "call",
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0, F1_1F2_3, 0x3900, "ldps",
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/* TYPE_11b23 */
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0, F1_1F2_3, 0x0D08, "clr",
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0, F1_1F2_3, 0x0C08, "clrb",
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0, F1_1F2_3, 0x0D00, "com",
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0, F1_1F2_3, 0x0C00, "comb",
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0, F1_1F2_3, 0x0D02, "neg",
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0, F1_1F2_3, 0x0C02, "negb",
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0, F1_1F2_3, 0x0D04, "test",
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0, F1_1F2_3, 0x0C04, "testb",
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0, F1_1F2_3, 0x1C08, "testl",
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0, F1_1F2_3, 0x0D06, "tset",
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0, F1_1F2_3, 0x0C06, "tsetb",
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0, F1_1a, 0xB000, "dab",
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0, F1_1a, 0xB10A, "exts",
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0, F1_1a, 0xB100, "extsb",
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0, F1_1a, 0xB107, "extsl",
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0, F1_1b, 0xB300, "rl",
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0, F1_1b, 0xB200, "rlb",
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0, F1_1b, 0xB308, "rlc",
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0, F1_1b, 0xB208, "rlcb",
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0, F1_1b, 0xB304, "rr",
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0, F1_1b, 0xB204, "rrb",
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0, F1_1b, 0xB30C, "rrc",
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0, F1_1b, 0xB20C, "rrcb",
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/* TYPE_12 */
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0, F1_2, 0x2B00, "dec",
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0, F1_2, 0x2A00, "decb",
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0, F1_2, 0x2900, "inc",
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0, F1_2, 0x2800, "incb",
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0, LDK, 0xBD00, "ldk",
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/* TYPE_1263 */
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0, F1_2F6_3, 0x2700, "bit",
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0, F1_2F6_3, 0x2600, "bitb",
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0, F1_2F6_3, 0x2300, "res",
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0, F1_2F6_3, 0x2200, "resb",
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0, F1_2F6_3, 0x2500, "set",
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0, F1_2F6_3, 0x2400, "setb",
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/* TYPE_jp */
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0, JP, 0x1E00, "jp",
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0, TCC, 0xAF00, "tcc",
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0, TCC, 0xAE00, "tccb",
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/* TYPE_21a */
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0, F2_1, 0x2D00, "ex",
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0, F2_1, 0x2C00, "exb",
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/* TYPE_21b */
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0, F2_1, 0x3500, "adc",
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0, F2_1, 0x3400, "adcb",
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0, F2_1, 0x3E00, "rldb",
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0, F2_1, 0x3C00, "rrdb",
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0, F2_1, 0x3700, "sbc",
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0, F2_1, 0x3600, "sbcb",
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/* TYPE_2151.
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** Depending on their operands the cp-instructions might
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** have an opcode of 0x201 more then listed below. This is
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** added at the appropriate place.
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** The difference in opcode between byte-,word- and long-
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** instructions of the F2_1F5_1 group is as follows:
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** If bit 8 is on it is a word instruction; If it is not a
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** word instruction and bit 12 is on it is a long instruction,
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** else it is a byte instruction. This information is used
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** when one of the operands is of type IM.
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*/
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0, F2_1F5_1, 0x0100, "add",
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0, F2_1F5_1, 0x0000, "addb",
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0, F2_1F5_1, 0x1600, "addl",
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0, F2_1F5_1, 0x0700, "and",
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0, F2_1F5_1, 0x0600, "andb",
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0, F2_1F5_1, 0x1B00, "div",
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0, F2_1F5_1, 0x1A00, "divl",
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0, F2_1F5_1, 0x1900, "mult",
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0, F2_1F5_1, 0x1800, "multl",
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0, F2_1F5_1, 0x0500, "or",
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0, F2_1F5_1, 0x0400, "orb",
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0, F2_1F5_1, 0x0300, "sub",
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0, F2_1F5_1, 0x0200, "subb",
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0, F2_1F5_1, 0x1200, "subl",
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0, F2_1F5_1, 0x0900, "xor",
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0, F2_1F5_1, 0x0800, "xorb",
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0, F2_1F5_1, 0x0B00, "cp",
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0, F2_1F5_1, 0x0A00, "cpb",
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0, F2_1F5_1, 0x1000, "cpl",
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0, LDA, 0, "lda",
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/* TYPE_pop */
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0, POP, 0x1700, "pop",
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0, POP, 0x1500, "popl",
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/* TYPE_push */
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0, PUSH, 0x1300, "push",
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0, PUSH, 0x1100, "pushl",
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/* TYPE_ld */
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0, LD, 0x0100, "ld",
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0, LD, 0, "ldb",
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0, LDL, 0, "ldl",
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0, DJNZ, 0xF080, "djnz",
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0, DJNZ, 0xF000, "dbjnz",
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0, JR, 0xE000, "jr",
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0, CALR, 0xD000, "calr",
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/* Depending on their operands the LDR-instructions might
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** have an opcode of 0x200 more then listed below. This is
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** or-ed in at the appropriate place.
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*/
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0, LDR, 0x3100, "ldr",
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0, LDR, 0x3000, "ldrb",
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0, LDR, 0x3500, "ldrl",
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0, LDAR, 0x3400, "ldar",
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0, F5_1L, 0xB309, "sla",
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0, F5_1L, 0xB209, "slab",
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0, F5_1L, 0xB30D, "slal",
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0, F5_1L, 0xB301, "sll",
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0, F5_1L, 0xB201, "sllb",
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0, F5_1L, 0xB305, "slll",
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0, F5_1R, 0xB309, "sra",
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0, F5_1R, 0xB209, "srab",
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0, F5_1R, 0xB30D, "sral",
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0, F5_1R, 0xB301, "srl",
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0, F5_1R, 0xB201, "srlb",
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0, F5_1R, 0xB305, "srll",
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/* Depending on its operands the LDM-instruction might have
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** an opcode of 8 more then listed below. This is added at the
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** appropriate place.
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** TYPE_ldm
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*/
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0, LDM, 0x1C01, "ldm",
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/* For the F6.4 instructions below the yylval-column contains
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** the opcode for the instruction. However the third hexa-digit
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** should be 0; But this is the opcode which must be put into
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** the second word of the instruction!
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*/
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0, F6_4, 0x3B88, "ind",
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0, F6_4, 0x3A88, "indb",
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0, F6_4, 0x3B08, "indr",
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0, F6_4, 0x3A08, "indrb",
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0, F6_4, 0x3B80, "ini",
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0, F6_4, 0x3A80, "inib",
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0, F6_4, 0x3B00, "inir",
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0, F6_4, 0x3A00, "inirb",
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0, F6_4, 0xBB89, "ldd",
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0, F6_4, 0xBA89, "lddb",
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0, F6_4, 0xBB09, "lddr",
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0, F6_4, 0xBA09, "lddrb",
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0, F6_4, 0xBB81, "ldi",
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0, F6_4, 0xBA81, "ldib",
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0, F6_4, 0xBB01, "ldir",
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0, F6_4, 0xBA01, "ldirb",
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0, F6_4, 0x3B0A, "otdr",
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0, F6_4, 0x3A0A, "otdrb",
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0, F6_4, 0x3B02, "otir",
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0, F6_4, 0x3A02, "otirb",
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0, F6_4, 0x3B8A, "outd",
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0, F6_4, 0x3A8A, "outdb",
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0, F6_4, 0x3B82, "outi",
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0, F6_4, 0x3A82, "outib",
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0, F6_4, 0x3B89, "sind",
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0, F6_4, 0x3A89, "sindb",
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0, F6_4, 0x3B09, "sindr",
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0, F6_4, 0x3A09, "sindrb",
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0, F6_4, 0x3B81, "sini",
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0, F6_4, 0x3A81, "sinib",
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0, F6_4, 0x3B01, "sinir",
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0, F6_4, 0x3A01, "sinirb",
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0, F6_4, 0x3B0B, "sotdr",
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0, F6_4, 0x3A0B, "sotdrb",
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0, F6_4, 0x3B03, "sotir",
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0, F6_4, 0x3A03, "sotirb",
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0, F6_4, 0x3B8B, "soutd",
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0, F6_4, 0x3A8B, "soutdb",
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0, F6_4, 0x3B83, "souti",
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0, F6_4, 0x3A83, "soutib",
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0, F6_4, 0xB808, "trdb",
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0, F6_4, 0xB80C, "trdrb",
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0, F6_4, 0xB800, "trib",
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0, F6_4, 0xB804, "trirb",
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0, F6_4, 0xB80A, "trtdb",
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0, F6_4, 0xB8EE, "trtdrb",
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0, F6_4, 0xB802, "trtib",
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0, F6_4, 0xB8E6, "trtirb",
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/* From the F6.5 instructions below the last eight ('string'-
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** instructions) want an 'ir' as operand; The others want a 'r'.
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** In the opcode for the string-instructions bit 1 is on, which
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** indicates the difference.
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*/
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0, F6_5, 0xBB08, "cpd",
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0, F6_5, 0xBA08, "cpdb",
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0, F6_5, 0xBB0C, "cpdr",
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0, F6_5, 0xBA0C, "cpdrb",
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0, F6_5, 0xBB00, "cpi",
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0, F6_5, 0xBA00, "cpib",
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0, F6_5, 0xBB04, "cpir",
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0, F6_5, 0xBA04, "cpirb",
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0, F6_5, 0xBB0A, "cpsd",
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|
0, F6_5, 0xBA0A, "cpsdb",
|
||
|
|
0, F6_5, 0xBB0E, "cpsdr",
|
||
|
|
0, F6_5, 0xBA0E, "cpsdrb",
|
||
|
|
0, F6_5, 0xBB02, "cpsi",
|
||
|
|
0, F6_5, 0xBA02, "cpsib",
|
||
|
|
0, F6_5, 0xBB06, "cpsir",
|
||
|
|
0, F6_5, 0xBA06, "cpsirb",
|
||
|
|
|
||
|
|
0, F6_6, 0xB30B, "sda",
|
||
|
|
0, F6_6, 0xB20B, "sdab",
|
||
|
|
0, F6_6, 0xB30F, "sdal",
|
||
|
|
0, F6_6, 0xB303, "sdl",
|
||
|
|
0, F6_6, 0xB203, "sdlb",
|
||
|
|
0, F6_6, 0xB307, "sdll",
|
||
|
|
|
||
|
|
/* The instructions in\b and out\b have two different opcodes
|
||
|
|
** depending on their operands (...). Therefore the opcodes
|
||
|
|
** below are not complete. The rest is or-ed in at the ap-
|
||
|
|
** propriate place!
|
||
|
|
** rest | r and da r and ir
|
||
|
|
** ---------------------------------
|
||
|
|
** in\b | 0xA04 0xC00
|
||
|
|
** out\b | 0xA06 OxE00
|
||
|
|
** Furthermore the 'special'-instructions don't allow an 'ir'
|
||
|
|
** as operand. In their opcode bit 0 is on, which indicates
|
||
|
|
** the difference with the other instructions of this group.
|
||
|
|
*/
|
||
|
|
0, IN, 0x3100, "in",
|
||
|
|
0, IN, 0x3000, "inb",
|
||
|
|
0, IN, 0x3B05, "sin",
|
||
|
|
0, IN, 0x3A05, "sinb",
|
||
|
|
0, OUT, 0x3100, "out",
|
||
|
|
0, OUT, 0x3000, "outb",
|
||
|
|
0, OUT, 0x3B07, "sout",
|
||
|
|
0, OUT, 0x3A07, "soutb",
|
||
|
|
|
||
|
|
/* Depending on their operands the LDCTL-instructions might
|
||
|
|
** have an opcode of 8 more then listed below. This is or-ed
|
||
|
|
** in at the appropriate place.
|
||
|
|
*/
|
||
|
|
0, LDCTL, 0x7D00, "ldctl",
|
||
|
|
0, LDCTLB, 0x8C00, "ldctlb",
|
||
|
|
0, MREQ, 0x7B0D, "mreq",
|
||
|
|
|
||
|
|
0, F9_1, 0x8D05, "comflg",
|
||
|
|
0, F9_1, 0x8D03, "resflg",
|
||
|
|
0, F9_1, 0x8D01, "setflg",
|
||
|
|
|
||
|
|
0, F9_2, 0x7C00, "di",
|
||
|
|
0, F9_2, 0x7C04, "ei",
|
||
|
|
|
||
|
|
0, F9_3, 0x7A00, "halt",
|
||
|
|
0, F9_3, 0x7B00, "iret",
|
||
|
|
0, F9_3, 0x7B0A, "mbit",
|
||
|
|
0, F9_3, 0x7B09, "mres",
|
||
|
|
0, F9_3, 0x7B08, "mset",
|
||
|
|
0, F9_3, 0x8D07, "nop",
|
||
|
|
|
||
|
|
/* Rest of the opcode-0x200 is or-ed in at the appropriate place
|
||
|
|
*/
|
||
|
|
0, RET, 0x9E00, "ret",
|
||
|
|
0, SC, 0x7F00, "sc",
|