2007-11-02 18:56:58 +00:00
|
|
|
/*
|
|
|
|
|
* $Source$
|
|
|
|
|
* $State$
|
|
|
|
|
*/
|
|
|
|
|
|
|
|
|
|
#define THREE_PASS /* branch and offset optimization */
|
|
|
|
|
#define BYTES_REVERSED /* high order byte has lowest address */
|
|
|
|
|
#define WORDS_REVERSED /* high order word has lowest address */
|
|
|
|
|
#define LISTING /* enable listing facilities */
|
|
|
|
|
#define RELOCATION /* generate relocatable code */
|
|
|
|
|
#define DEBUG 0
|
|
|
|
|
|
|
|
|
|
#undef valu_t
|
2017-01-30 21:15:02 +00:00
|
|
|
#define valu_t int32_t
|
2007-11-02 18:56:58 +00:00
|
|
|
|
|
|
|
|
#undef ADDR_T
|
2017-01-30 21:15:02 +00:00
|
|
|
#define ADDR_T uint32_t
|
2007-11-02 18:56:58 +00:00
|
|
|
|
|
|
|
|
#undef word_t
|
2017-01-30 21:15:02 +00:00
|
|
|
#define word_t uint32_t
|
2016-10-17 22:21:32 +00:00
|
|
|
|
2007-11-02 18:56:58 +00:00
|
|
|
#undef ALIGNWORD
|
|
|
|
|
#define ALIGNWORD 4
|
|
|
|
|
|
|
|
|
|
#undef ALIGNSECT
|
|
|
|
|
#define ALIGNSECT 4
|
|
|
|
|
|
|
|
|
|
#undef VALWIDTH
|
|
|
|
|
#define VALWIDTH 8
|
|
|
|
|
|
|
|
|
|
#define FIXUPFLAGS (RELBR | RELWR)
|
Teach the assembler about PowerPC extended mnemonics.
Also make a few changes to basic mnemonics. Fix typo in name of the
basic "creqv". Add the basic "addc" and relatives, because it would
be odd to have the extended "subc" without "addc". Fix the basic
"rldicl", "rldicr", "rldic", "rldimi" to correctly encode the 6-bit MB
field. Fix "slw" and relatives to correctly swap their RA and RS
operands.
Add many, but not all, of the extended mnemonics from IBM's Power ISA
Version 2.06 Book I Appendix E. (I used 2.06, published 2009, just
because I already had the PDF of it.) This commit includes mnemonics
for branching, subtraction, traps, bit rotation, and a few others,
like "mflr" and "nop". The assembler now understands branches like
`beq cr7, label` and bit shifts like `slwi r7, r7, 2`. These encode
the same machine instructions as the basic "bc" and "rlwinm".
Some operands to basic names become optional. The assembler no longer
requires the level in "sc" or the branch hint in "bcctr" and "bclr";
they default to zero. Some extended names take an optional branch
hint or condition register.
Some extended names are still missing. I don't provide names with
static branch prediction, like "beq+" or "bge-", because the assembler
parses '+' and '-' as operators, not as part of an instruction name.
I also don't provide some names that 2.06 has for moving to or from
the condition register or some special purpose registers, names like
"mtcr" or "mfuamr".
This commit also deletes some unused tokens and one unused yacc rule.
2017-01-22 04:49:29 +00:00
|
|
|
|
|
|
|
|
/* 6-bit mb (mask begin) or me (mask end) field */
|
|
|
|
|
#define MB6(v) (((v) & 0x1F)<<6 | ((v) & 0x20)>>0)
|
|
|
|
|
|
|
|
|
|
/* 6-bit sh (shift) field */
|
|
|
|
|
#define SH6(v) (((v) & 0x1F)<<11 | ((v) & 0x20)>>4)
|
