285 lines
9.3 KiB
Plaintext
285 lines
9.3 KiB
Plaintext
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.TL
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Code Expander
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.br
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(proposal)
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.SH
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Introduction
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.LP
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The \fBcode expander\fR, \fBce\fR, is a program that translates EM-code to
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objectcode. The main goal is to translate very fast. \fBce\fR is an instance
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of the EM_CODE(3L)-interface. During execution of \fBce\fR, \fBce\fR will build
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in core a machine independent objectfile ( NEW A.OUT(5L)). With \fBcv\fR or
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with routines supplied by the user the machine independent objectcode will
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be converted to a machine dependent object code. \fBce\fR needs
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information about the targetmachine (e.g. the opcode's). We divide the
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information into two parts:
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.IP
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- The description in assembly instructions of EM-code instructions.
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.IP
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- The description in objectcode of assembly instructions.
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.LP
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With these two tables we can make a \fBcode expander generator\fR which
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generates a \fBce\fR. It is possible to put the information in one table
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but that will probably introduce (propable) more bugs in the table. So we
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divide and conquer. With this approach it is also possible to generate
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assembly code ( rather yhan objectcode), wich is useful for debugging.
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There is of course a link between the two tables, the link
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consist of a restriction on the assembly format. Every assembly
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instruction must have the following format:
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.sp
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INSTR ::= LABEL : MNEMONIC [ OPERAND ( "," OPERAND)* ]
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.sp
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.LP
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\fBCeg\fR uses the following algorithm:
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.IP \0\0a)
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The assembly table will be converted to a (C-)routine assemble().
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assemble() gets as argument a string, the assembler instruction,
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and can use the MNEMONIC to execute the corresponding action in the
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assembly table.
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.IP \0\0b)
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The routine assemble() can now be used to convert the EM-code table to
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a set of C-routines, wich together form an instance of the
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EM_CODE(3L).
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.SH
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The EM-instruction table
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.LP
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We use the following grammar:
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.sp
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.TS
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center box ;
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l.
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TABLE ::= (ROW)*
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ROW ::= C_instr ( SPECIAL | SIMPLE)
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SPECIAL ::= ( CONDITION SIMPLE)+ 'default' SIMPLE
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SIMPLE ::= '==>' ACTIONLIST | '::=' ACTIONLIST
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ACTIONLIST ::= [ ACTION ( ';' ACTION)* ] '.'
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ACTION ::= function-call | assembly-instruction
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.TE
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.LP
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An example for the 8086:
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.LP
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.DS
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C_lxl
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$arg1 == 0 ==> "push bp".
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$arg1 == 1 ==> "push EM_BSIZE(bp)".
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default ==> "mov cx, $arg1";
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"mov si, bp";
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"1: mov si, EM_BSIZE(si);
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"loop 1b"
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"push si".
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.DE
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.sp
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Some remarks:
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.sp
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* The C_instr is a function indentifier in the EM_CODE(3L)-interface.
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.LP
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* CONDITION is a "boolean" C-expression.
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.LP
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* The arguments of an EM-instruction can be used in CONDITION and in assembly
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instructions. They are referred by $arg\fIi\fR. \fBceg\fR modifies the
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arguments as follows:
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.IP \0\0-
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For local variables at positive offsets it increases this offset by EM_BSIZE
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.IP \0\0-
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It makes names en labels unique. The user must supply the formats (see mach.h).
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.LP
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* function-call is allowed to implement e.g. push/pop optimization.
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For example:
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.LP
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.DS
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C_adi
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$arg1 == 2 ==> combine( "pop ax");
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combine( "pop bx");
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"add ax, bx";
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save( "push ax").
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default ==> arg_error( "C_adi", $arg1).
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.DE
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.LP
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* The C-functions called in the EM-instructions table have to use the routine
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assemble()/gen?(). "assembler-instr" is in fact assemble( "assembler-instr").
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.LP
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* \fBceg\fR takes care not only about the conversions of arguments but also
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about
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changes between segments. There are situation when one doesn't want
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conversion of arguments. This can be done by using ::= in stead of ==>.
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This is usefull when two C_instr are equivalent. For example:
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.IP
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C_slu ::= C_sli( $arg1)
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.LP
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* There are EM-CODE instructions wich are machine independent (e.g. C_open()).
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For these EM_CODE instructions \fBceg\fR will generate \fIdefault\fR-
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instructions. There is one exception: in the case of C_pro() the tablewriter
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has to supply a function prolog().
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.LP
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* Also the EM-pseudoinstructions C_bss_\fIcstp\fR(), C_hol_\fIcstp\fR(),
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C_con_\fIcstp\fR() and C_rom_\fIcstp\fR can be translated automaticly.
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\fBceg\fR only has to know how to interpretate string-constants:
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.DS
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\&..icon $arg2 == 1 ==> gen1( (char) atoi( $arg1))
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$arg2 == 2 ==> gen2( atoi( $arg1))
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$arg2 == 4 ==> gen4( atol( $arg1))
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\&..ucon $arg2 == 1 ==> gen1( (char) atoi( $arg1))
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$arg2 == 2 ==> gen2( atoi( $arg1))
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$arg2 == 4 ==> gen4( atol( $arg1))
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\&..fcon ::= not_implemented( "..fcon")
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.DE
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.LP
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* Still, life can be made easier for the tablewriter; For the routines wich
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he/she didn't implement \fBceg\fR will generate a default instruction wich
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generates an error-message. \fBceg\fR seems to generate :
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.IP
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C_xxx ::= not_implemented( "C_xxx")
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.SH
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The assembly table
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.LP
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How to map assembly on objectcode.
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.LP
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Each row in the table consists of two fields, one field for the assembly
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instruction, the other field for the corresponding objectcode. The tablewriter
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can use the following primitives to generate code for the machine
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instructions :
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.IP "\0\0gen1( b)\0\0:" 17
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generates one byte in de machine independent objectfile.
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.IP "\0\0gen2( w)\0\0:" 17
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generates one word ( = two bytes), the table writer can change the byte
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order by setting the flag BYTES_REVERSED.
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.IP "\0\0gen4( l)\0\0:" 17
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generates two words ( = four bytes), the table writer can change the word
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order by setting the flag WORDS_REVERSED.
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.IP "\0\0reloc( n, o, r)\0\0:" 17
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generates relocation information for a label ( = name + offset +
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relocationtype).
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.LP
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Besides these primitives the table writer may use his self written
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C-functions. This allows the table writer e.g. to write functions to set
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bitfields within a byte.
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.LP
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There are more or less two methods to encode the assembly instructions:
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.IP \0\0a)
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MNEMONIC and OPERAND('s) are encoded independently of each other. This can be
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done when the target machine has an orthogonal instruction set (e.g. pdp-11).
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.IP \0\0b)
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MNEMONIC and OPERAND('s) together determine the opcode. In this case the
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assembler often uses overloading: one MNEMONIC is used for several
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different machine-instructions. For example : (8086)
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.br
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mov ax, bx
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.br
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mov ax, variable
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.br
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These instructions have different opcodes.
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.LP
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As the transformation MNEMONIC-OPCODE is not one to
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one the table writer must be allowed to put restrictions on the operands.
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This can be done with type declarations. For example:
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.LP
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.DS
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mov dst:REG, src:MEM ==>
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gen1( 0x8b);
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modRM( op2.reg, op1);
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.DE
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.DS
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mov dst:REG, src:REG ==>
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gen1( 0x89);
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modRM( op2.reg, op1);
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.DE
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.LP
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modRM() is a function written by the tablewriter and is used to encode
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the operands. This frees the table writer of endless typing.
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.LP
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The table writer has to do the "typechecking" by himself. But typechecking
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is almost the same as operand decoding. So it's more efficient to do this
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in one function. We now have all the tools to describe the function
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assemble().
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.IP
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assemble() first calls the function
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decode_operand() ( by the table writer written), with two arguments: a
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string ( the operand) and a
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pointer to a struct. The struct is declared by the table writer and must
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consist of at least a field called type. ( the other fields in the struct can
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be used to remember information about the decoded operand.) Now assemble()
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fires a row wich is selected by mapping the MNEMONIC and the type of the
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operands.
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.br
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In the second field of a row there may be references to other
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fields in the struct (e.g. op2.reg in the example above).
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.LP
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We ignored one problem. It's possible when the operands are encoded, that
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not everything is known. For example $arg\fIi\fR arguments in the
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EM-instruction table get their value at runtime. This problem is solved by
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introducing a function eval(). eval() has a string as argument and returns
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an arith. The string consists of constants and/or $arg\fIi\fR's and the value
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returned by eval() is the value of the string. To encode the $arg\fIi\fR's
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in as few bytes as possible the table writer can use the statements %if,
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%else and %endif. They can be used in the same manner as #if, #else and
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#endif in C and result in a runtime test. An example :
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.LP
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.DS
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-- Some rows of the assembly table
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mov dst:REG, src:DATA ==>
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%if sfit( eval( src), 8) /* does the immediate-data fit in 1 byte? */
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R53( 0x16 , op1.reg);
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gen1( eval( src));
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%else
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R53( 0x17 , op1.reg);
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gen2( eval( src));
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%endif
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.LD
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mov dst:REG, src:REG ==>
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gen1( 0x8b);
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modRM( op1.reg, op2);
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.DE
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.DS
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-- The corresponding part in the function assemble() :
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case MNEM_mov :
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decode_operand( arg1, &op1);
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decode_operand( arg2, &op2);
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if ( REG( op1.type) && DATA( op2.type)) {
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printf( "if ( sfit( %s, 8)) {\\\\n", eval( src));
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R53( 0x16 , op1.reg);
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printf( "gen1( %s)\\\\n", eval( arg2));
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printf( "}\\\\nelse {\\\\n");
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R53( 0x17 , op1.reg);
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printf( "gen2( %s)\\\\n", eval( arg2));
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printf( "}\\\\n");
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}
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else if ( REG( op1.type) && REG( op2.type)) {
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gen1( 0x8b);
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modRM( op1.reg, op2);
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}
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.DE
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.DS
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-- Some rows of the right part of the EM-instruction table are translated
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-- in the following C-functions.
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"mov ax, $arg1" ==>
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if ( sfit( w, 8)) { /* w is the actual argument of C_xxx( w) */
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gen1( 176); /* R53() */
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gen1( w);
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}
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else {
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gen1( 184);
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gen2( w);
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}
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.LD
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"mov ax, bx" ==>
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gen1( 138);
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gen1( 99); /* modRM() */
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.DE
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.SH
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Restrictions
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.LP
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.IP \0\01)
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The EM-instructions C_exc() is not implemented.
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.IP \0\03)
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All messages are ignored.
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