246 lines
8.6 KiB
Plaintext
246 lines
8.6 KiB
Plaintext
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.SN 5
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.BP
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.S1 "MAPPING OF EM DATA MEMORY ONTO TARGET MACHINE MEMORY"
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The EM architecture is designed to be implemented
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on many existing and future machines.
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EM memory is highly fragmented to make
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adaptation to various memory architectures possible.
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Format and encoding of pointers is explicitly undefined.
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.P
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This chapter gives solutions to some of the
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anticipated problems.
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First, we describe a possible memory layout for machines
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with 64K bytes of address space.
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Here we use a member of the EM family with 2-byte word and pointer
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size.
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The most straightforward layout is shown in figure 2.
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.N 1
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.DS
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65534 -> |-------------------------------|
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|///////////////////////////////|
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|//// unimplemented memory /////|
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|///////////////////////////////|
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ML -> |-------------------------------|
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| | <- LB
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| stack and local area |
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|-------------------------------| <- SP
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|///////////////////////////////|
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|//////// inaccessible /////////|
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|///////////////////////////////|
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|-------------------------------| <- HP
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| heap area |
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HB -> |-------------------------------|
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| global data area |
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EB -> |-------------------------------|
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| program text | <- PC
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| ( and tables ) |
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PB -> |-------------------------------|
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|///////////////////////////////|
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|////////// undefined //////////|
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|///////////////////////////////|
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0 -> |-------------------------------|
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Figure 2. Memory layout showing typical register
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positions during execution of an EM program.
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.DE 2
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The base registers for the various memory pieces can be stored
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in target machine registers or memory.
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.IS
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.N 1
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.TS
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tab(;);
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l 1 l l l.
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PB;:;program base;points to the base of the instruction address space.
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EB;:;external base;points to the base of the data address space.
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HB;:;heap base;points to the base of the heap area.
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ML;:;memory limit;marks the high end of the addressable data space.
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.TE 1
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.IE
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The stack grows from high
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EM addresses to low EM addresses, and the heap the
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other way.
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The memory between SP and HP is not accessible,
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but may be allocated later to the stack or the heap if needed.
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The local data area is allocated starting at the high end of
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memory.
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.P
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Because EM address 0 is not mapped onto target
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address 0, a problem arises when pointers are used.
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If a program pushed a constant, say 6, onto the stack,
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and then tried to indirect through it,
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the wrong word would be fetched,
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because EM address 6 is mapped onto target address EB+6
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and not target address 6 itself.
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This particular problem is solved by explicitly declaring
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the format of a pointer to be undefined,
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so that using a constant as a pointer is completely illegal.
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However, the general problem of mapping pointers still exists.
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.P
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There are two possible solutions.
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In the first solution, EM pointers are represented
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in the target machine as true EM addresses,
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for example, a pointer to EM address 6 really is
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stored as a 6 in the target machine.
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This solution implies that every time a pointer is fetched
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EB must be added before referencing
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the target machine's memory.
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If the target machine has powerful indexing
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facilities, EB can be kept in a target machine register,
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and the relocation can indeed be done on
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every reference to the data address space
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at a modest cost in speed.
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.P
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The other solution consists of having EM pointers
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refer to the true target machine address.
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Thus the instruction LAE 6 (Load Address of External 6)
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would push the value of EB+6 onto the stack.
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When this approach is chosen, back ends must know
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how to offset from EB, to translate all
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instructions that manipulate EM addresses.
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However, the problem is not completely solved,
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because a front end may have to initialize a pointer
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in CON or ROM data to point to a global address.
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This pointer must also be relocated by the back end or the interpreter.
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.P
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Although the EM stack grows from high to low EM addresses,
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some machines have hardware PUSH and POP
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instructions that require the stack to grow upwards.
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If reasons of efficiency urge you to use these
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instructions, then EM
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can be implemented with the memory layout
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upside down, as shown in figure 3.
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This is possible because the pointer format is explicitly undefined.
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The first element of a word array will have a
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lower physical address than the second element.
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.N 2
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.DS
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| EB=60 | | ^ |
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| | | | |
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|-----------------| |-----------------|
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105 | 45 | 44 | 104 214 | 41 | 40 | 215
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|-----------------| |-----------------|
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103 | 43 | 42 | 102 212 | 43 | 42 | 213
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|-----------------| |-----------------|
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101 | 41 | 40 | 100 210 | 45 | 44 | 211
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|-----------------| |-----------------|
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| v | | EB=255 |
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Type A Type B
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.sp 2
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Figure 3. Two possible memory implementations.
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Numbers within the boxes are EM addresses.
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The other numbers are physical addresses.
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.DE 2
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.A 0 0
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So, we have two different EM memory implementations:
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.IS
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.PS - 4
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.PT A~-
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stack downwards
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.PT B~-
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stack upwards
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.PE
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.IE
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.P
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For each of these two possibilities we give the translation of
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the EM instructions to push the third byte of a global data
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block starting at EM address 40 onto the stack and to load the
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word at address 40.
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All translations assume a word and pointer size of two bytes.
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The target machine used is a PDP-11 augmented with push and pop instructions.
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Registers 'r0' and 'r1' are used and suffer from sign extension for byte
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transfers.
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Push $40 means push the constant 40, not word 40.
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.P
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The translation of the EM instructions depends on the pointer representation
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used.
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For each of the two solutions explained above the translation is given.
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.P
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First, the translation for the two implementations using EM addresses as
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pointer representation:
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.DS
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.TS
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tab(:), center;
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l s l s l s
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_ s _ s _ s
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l 2 l 6 l 2 l 6 l 2 l.
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EM:type A:type B
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LAE:40:push:$40:push:$40
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ADP:3:pop:r0:pop:r0
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::add:$3,r0:add:$3,r0
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::push:r0:push:r0
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LOI:1:pop:r0:pop:r0
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::-::neg:r0
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::clr:r1:clr:r1
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::bisb:eb(r0),r1:bisb:eb(r0),r1
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::push:r1:push:r1
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LOE:40:push:eb+40:push:eb-41
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.TE
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.DE
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.BP
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.P
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The translation for the two implementations, if the target machine address is
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used as pointer representation, is:
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.N 1
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.DS
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.TS
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tab(:), center;
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l s l s l s
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_ s _ s _ s
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l 2 l 6 l 2 l 6 l 2 l.
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EM:type A:type B
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LAE:40:push:$eb+40:push:$eb-40
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ADP:3:pop:r0:pop:r0
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::add:$3,r0:sub:$3,r0
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::push:r0:push:r0
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LOI:1:pop:r0:pop:r0
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::clr:r1:clr:r1
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::bisb:(r0),r1:bisb:(r0),r1
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::push:r1:push:r1
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LOE:40:push:eb+40:push:eb-41
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.TE
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.DE
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.P
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The translation presented above is not intended to be optimal.
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Most machines can handle these simple cases in one or two instructions.
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It demonstrates, however, the flexibility of the EM design.
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.P
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There are several possibilities to implement EM on machines with
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address spaces larger than 64k bytes.
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For EM with two byte pointers one could allocate instruction and
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data space each in a separate 64k piece of memory.
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EM pointers still have to fit in two bytes,
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but the base registers PB and EB may be loaded in hardware registers
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wider than 16 bits, if available.
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EM implementations can also make efficient use of a machine
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with separate instruction and data space.
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.P
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EM with 32 bit pointers allows one to make use of machines
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with large address spaces.
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In a virtual, segmented memory system one could use a separate
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segment for each fragment.
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