1990-01-12 16:55:50 +00:00
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/*
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* (c) copyright 1990 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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1990-01-17 16:05:00 +00:00
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#define RCSID3 "$Header$"
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1990-01-12 16:55:50 +00:00
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/*
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* VAX-11 keywords
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*/
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0, REG, 0, "r0",
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0, REG, 1, "r1",
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0, REG, 2, "r2",
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0, REG, 3, "r3",
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0, REG, 4, "r4",
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0, REG, 5, "r5",
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0, REG, 6, "r6",
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0, REG, 7, "r7",
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0, REG, 8, "r8",
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0, REG, 9, "r9",
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0, REG, 10, "r10",
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0, REG, 11, "r11",
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0, REG, 12, "r12",
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0, REG, 12, "ap",
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0, REG, 13, "r13",
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0, REG, 13, "fp",
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0, REG, 14, "r14",
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0, REG, 14, "sp",
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0, REG, 15, "r15",
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0, REG, 15, "pc",
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/* For immediate mode, we need the size as specified by the instruction.
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Ordinary operands are therefore encoded as _w, _b, and _l to indicate
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size.
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For now, immediate floating point and immediate values of size > 4 are not
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implemented. _u is used for this.
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1990-01-17 16:05:00 +00:00
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The valu_t field is used for the opcode. Most opcodes take one byte.
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The ones that don't take two bytes.
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1990-01-12 16:55:50 +00:00
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*/
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/* integer arithmetic and logical instructions */
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0, OP2_w_w, 0x58, "adawi",
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0, OP2_b_b, 0x80, "addb2",
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0, OP3_b_b_b, 0x81, "addb3",
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0, OP2_w_w, 0xa0, "addw2",
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0, OP3_w_w_w, 0xa1, "addw3",
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0, OP2_l_l, 0xc0, "addl2",
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0, OP3_l_l_l, 0xc1, "addl3",
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0, OP2_l_l, 0xd8, "adwc",
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0, OP3_b_l_l, 0x78, "ashl",
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0, OP3_b_u_u, 0x79, "ashq",
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0, OP2_b_b, 0x8a, "bicb2",
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0, OP3_b_b_b, 0x8b, "bicb3",
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0, OP2_w_w, 0xaa, "bicw2",
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0, OP3_w_w_w, 0xab, "bicw3",
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0, OP2_l_l, 0xca, "bicl2",
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0, OP3_l_l_l, 0xcb, "bicl3",
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0, OP2_b_b, 0x88, "bisb2",
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0, OP3_b_b_b, 0x89, "bisb3",
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0, OP2_w_w, 0xa8, "bisw2",
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0, OP3_w_w_w, 0xa9, "bisw3",
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0, OP2_l_l, 0xc8, "bisl2",
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0, OP3_l_l_l, 0xc9, "bisl3",
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0, OP2_b_b, 0x93, "bitb",
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0, OP2_w_w, 0xb3, "bitw",
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0, OP2_l_l, 0xd3, "bitl",
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0, OP1_b, 0x94, "clrb",
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0, OP1_w, 0xb4, "clrw",
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0, OP1_l, 0xd4, "clrl",
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0, OP1_u, 0x7c, "clrq",
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0, OP1_u, 0x7cfd, "clro",
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0, OP2_b_b, 0x91, "cmpb",
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0, OP2_w_w, 0xb1, "cmpw",
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0, OP2_l_l, 0xd1, "cmpl",
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0, OP2_b_w, 0x99, "cvtbw",
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0, OP2_b_l, 0x98, "cvtbl",
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0, OP2_w_b, 0x33, "cvtwb",
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0, OP2_w_l, 0x32, "cvtwl",
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0, OP2_l_b, 0xf6, "cvtlb",
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0, OP2_l_w, 0xf7, "cvtlw",
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0, OP1_b, 0x97, "decb",
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0, OP1_w, 0xb7, "decw",
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0, OP1_l, 0xd7, "decl",
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0, OP2_b_b, 0x86, "divb2",
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0, OP3_b_b_b, 0x87, "divb3",
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0, OP2_w_w, 0xa6, "divw2",
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0, OP3_w_w_w, 0xa7, "divw3",
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0, OP2_l_l, 0xc6, "divl2",
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0, OP3_l_l_l, 0xc7, "divl3",
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0, OP4_l_u_l_l, 0x7b, "ediv",
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0, OP4_l_l_l_u, 0x7a, "emul",
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0, OP1_b, 0x96, "incb",
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0, OP1_w, 0xb6, "incw",
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0, OP1_l, 0xd6, "incl",
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0, OP2_b_b, 0x92, "mcomb",
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0, OP2_w_w, 0xb2, "mcomw",
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0, OP2_l_l, 0xd2, "mcoml",
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0, OP2_b_b, 0x8e, "mnegb",
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0, OP2_w_w, 0xae, "mnegw",
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0, OP2_l_l, 0xce, "mnegl",
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0, OP2_b_b, 0x90, "movb",
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0, OP2_w_w, 0xb0, "movw",
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0, OP2_l_l, 0xd0, "movl",
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0, OP2_u_u, 0x7d, "movq",
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0, OP2_u_u, 0x7dfd, "movo",
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0, OP2_b_w, 0x9b, "movzbw",
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0, OP2_b_l, 0x9a, "movzbl",
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0, OP2_w_l, 0x3c, "movzwl",
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0, OP2_b_b, 0x84, "mulb2",
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0, OP3_b_b_b, 0x85, "mulb3",
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0, OP2_w_w, 0xa4, "mulw2",
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0, OP3_w_w_w, 0xa5, "mulw3",
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0, OP2_l_l, 0xc4, "mull2",
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0, OP3_l_l_l, 0xc5, "mull3",
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0, OP1_l, 0xdd, "pushl",
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0, OP3_b_l_l, 0x9c, "rotl",
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0, OP2_l_l, 0xd9, "sbwc",
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0, OP2_b_b, 0x82, "subb2",
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0, OP3_b_b_b, 0x83, "subb3",
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0, OP2_w_w, 0xa2, "subw2",
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0, OP3_w_w_w, 0xa3, "subw3",
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0, OP2_l_l, 0xc2, "subl2",
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0, OP3_l_l_l, 0xc3, "subl3",
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0, OP1_b, 0x95, "tstb",
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0, OP1_w, 0xb5, "tstw",
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0, OP1_l, 0xd5, "tstl",
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0, OP2_b_b, 0x8c, "xorb2",
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0, OP3_b_b_b, 0x8d, "xorb3",
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0, OP2_w_w, 0xac, "xorw2",
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0, OP3_w_w_w, 0xad, "xorw3",
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0, OP2_l_l, 0xcc, "xorl2",
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0, OP3_l_l_l, 0xcd, "xorl3",
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/* Address instructions */
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0, OP2_A_l, 0x9e, "movab",
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0, OP2_A_l, 0x3e, "movaw",
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0, OP2_A_l, 0xde, "moval",
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0, OP2_A_l, 0xde, "movaf",
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0, OP2_A_l, 0x7e, "movaq",
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0, OP2_A_l, 0x7e, "movad",
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0, OP2_A_l, 0x7e, "movag",
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0, OP2_A_l, 0x7efd, "movah",
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0, OP2_A_l, 0x7efd, "movao",
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0, OP1_A, 0x9f, "pushab",
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0, OP1_A, 0x3f, "pushaw",
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0, OP1_A, 0xdf, "pushal",
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0, OP1_A, 0xdf, "pushaf",
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0, OP1_A, 0x7f, "pushaq",
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0, OP1_A, 0x7f, "pushad",
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0, OP1_A, 0x7f, "pushag",
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0, OP1_A, 0x7ffd, "pushah",
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0, OP1_A, 0x7ffd, "pushao",
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/* Variable length bit-field instructions */
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0, OP4_l_b_V_l, 0xec, "cmpv",
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0, OP4_l_b_V_l, 0xed, "cmpzv",
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0, OP4_l_b_V_l, 0xee, "extv",
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0, OP4_l_b_V_l, 0xef, "extzv",
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0, OP4_l_b_V_l, 0xeb, "ffc",
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0, OP4_l_b_V_l, 0xea, "ffs",
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0, OP4_l_l_b_V, 0xf0, "insv",
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/* Control instructions */
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0, OP4_b_b_b_Bw, 0x9d, "acbb",
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0, OP4_w_w_w_Bw, 0x3d, "acbw",
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0, OP4_l_l_l_Bw, 0xf1, "acbl",
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0, OP4_u_u_u_Bw, 0x4f, "acbf",
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0, OP4_u_u_u_Bw, 0x6f, "acbd",
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0, OP4_u_u_u_Bw, 0x4ffd, "acbg",
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0, OP4_u_u_u_Bw, 0x6ffd, "acbh",
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0, OP3_l_l_Bb, 0xf3, "aobleq",
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0, OP3_l_l_Bb, 0xf2, "aoblss",
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0, OP1_Bb, 0x14, "bgtr",
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0, OP1_Bb, 0x15, "bleq",
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0, OP1_Bb, 0x12, "bneq",
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0, OP1_Bb, 0x12, "bnequ",
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0, OP1_Bb, 0x13, "beql",
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0, OP1_Bb, 0x13, "beqlu",
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0, OP1_Bb, 0x18, "bgeq",
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0, OP1_Bb, 0x19, "blss",
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0, OP1_Bb, 0x1a, "bgtru",
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0, OP1_Bb, 0x1b, "blequ",
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0, OP1_Bb, 0x1c, "bvc",
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0, OP1_Bb, 0x1d, "bvs",
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0, OP1_Bb, 0x1e, "bgequ",
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0, OP1_Bb, 0x1e, "bcc",
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0, OP1_Bb, 0x1f, "blssu",
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0, OP1_Bb, 0x1f, "bcs",
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0, OP3_l_V_Bb, 0xe0, "bbs",
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0, OP3_l_V_Bb, 0xe1, "bbc",
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0, OP3_l_V_Bb, 0xe2, "bbss",
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0, OP3_l_V_Bb, 0xe3, "bbcs",
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0, OP3_l_V_Bb, 0xe4, "bbsc",
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0, OP3_l_V_Bb, 0xe5, "bbcc",
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0, OP3_l_V_Bb, 0xe6, "bbssi",
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0, OP3_l_V_Bb, 0xe7, "bbcci",
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0, OP2_l_Bb, 0xe8, "blbs",
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0, OP2_l_Bb, 0xe9, "blbc",
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0, OP1_Be, 0x14, "jgtr",
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0, OP1_Be, 0x15, "jleq",
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0, OP1_Be, 0x12, "jneq",
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0, OP1_Be, 0x12, "jnequ",
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0, OP1_Be, 0x13, "jeql",
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0, OP1_Be, 0x13, "jeqlu",
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0, OP1_Be, 0x18, "jgeq",
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0, OP1_Be, 0x19, "jlss",
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0, OP1_Be, 0x1a, "jgtru",
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0, OP1_Be, 0x1b, "jlequ",
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0, OP1_Be, 0x1c, "jvc",
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0, OP1_Be, 0x1d, "jvs",
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0, OP1_Be, 0x1e, "jgequ",
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0, OP1_Be, 0x1e, "jcc",
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0, OP1_Be, 0x1f, "jlssu",
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0, OP1_Be, 0x1f, "jcs",
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0, OP2_l_Be, 0xe8, "jlbs",
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0, OP2_l_Be, 0xe9, "jlbc",
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0, OP3_l_V_Be, 0xe0, "jbs",
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0, OP3_l_V_Be, 0xe1, "jbc",
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0, OP3_l_V_Be, 0xe2, "jbss",
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0, OP3_l_V_Be, 0xe3, "jbcs",
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0, OP3_l_V_Be, 0xe4, "jbsc",
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0, OP3_l_V_Be, 0xe5, "jbcc",
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0, OP3_l_V_Be, 0xe6, "jbssi",
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0, OP3_l_V_Be, 0xe7, "jbcci",
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0, OP1_Bx, 0x11, "br",
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0, OP1_Bb, 0x11, "brb",
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0, OP1_Bw, 0x31, "brw",
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0, OP1_Be, 0x11, "jbr",
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0, OP1_Bx, 0x10, "bsb",
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1990-06-19 15:27:43 +00:00
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0, OP1_Bb, 0x10, "bsbb",
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0, OP1_Bw, 0x30, "bsbw",
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1990-01-12 16:55:50 +00:00
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0, CASE_b_b_b, 0x8f, "caseb",
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0, CASE_w_w_w, 0xaf, "casew",
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0, CASE_l_l_l, 0xcf, "casel",
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0, OP1_A, 0x17, "jmp",
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0, OP1_A, 0x16, "jsb",
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0, OP0, 0x05, "rsb",
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0, OP2_l_Bb, 0xf4, "sobgeq",
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0, OP2_l_Bb, 0xf5, "sobgtr",
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/* Procedure call instructions */
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0, OP2_A_A, 0xfa, "callg",
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0, OP2_l_A, 0xfb, "calls",
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0, OP0, 0x04, "ret",
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/* Miscellaneous instructions */
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0, OP1_w, 0xb9, "bicpsw",
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0, OP1_w, 0xb8, "bispsw",
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0, OP0, 0x03, "bpt",
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0, OP0, 0x00, "halt",
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0, OP6_l_l_l_l_l_l,0x0a, "index",
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0, OP1_l, 0xdc, "movpsl",
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0, OP0, 0x01, "nop",
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0, OP1_w, 0xba, "popr",
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0, OP1_w, 0xbb, "pushr",
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0, OP0, 0xfc, "xfc",
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/* Queue instructions */
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0, OP2_A_A, 0x5c, "insqhi",
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0, OP2_A_A, 0x5d, "insqti",
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0, OP2_A_A, 0x0e, "insque",
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0, OP2_A_l, 0x5e, "remqhi",
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0, OP2_A_l, 0x5f, "remqti",
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0, OP2_A_l, 0x0f, "remque",
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/* Floating point instructions */
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0, OP2_u_u, 0x40, "addf2",
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0, OP3_u_u_u, 0x41, "addf3",
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0, OP2_u_u, 0x60, "addd2",
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0, OP3_u_u_u, 0x61, "addd3",
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0, OP2_u_u, 0x40fd, "addg2",
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0, OP3_u_u_u, 0x41fd, "addg3",
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0, OP2_u_u, 0x60fd, "addh2",
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0, OP3_u_u_u, 0x61fd, "addh3",
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0, OP1_u, 0xd4, "clrf",
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0, OP1_u, 0x7c, "clrd",
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0, OP1_u, 0x7c, "clrg",
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0, OP1_u, 0x7cfd, "clrh",
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0, OP2_u_u, 0x51, "cmpf",
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0, OP2_u_u, 0x71, "cmpd",
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0, OP2_u_u, 0x51fd, "cmpg",
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0, OP2_u_u, 0x71fd, "cmph",
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0, OP2_b_u, 0x4c, "cvtbf",
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0, OP2_b_u, 0x6c, "cvtbd",
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0, OP2_b_u, 0x4cfd, "cvtbg",
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0, OP2_b_u, 0x6cfd, "cvtbh",
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0, OP2_w_u, 0x4d, "cvtwf",
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0, OP2_w_u, 0x6d, "cvtwd",
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0, OP2_w_u, 0x4dfd, "cvtwg",
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0, OP2_w_u, 0x6dfd, "cvtwh",
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0, OP2_l_u, 0x4e, "cvtlf",
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0, OP2_l_u, 0x6e, "cvtld",
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0, OP2_l_u, 0x4efd, "cvtlg",
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0, OP2_l_u, 0x6efd, "cvtlh",
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0, OP2_u_b, 0x48, "cvtfb",
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0, OP2_u_b, 0x68, "cvtdb",
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0, OP2_u_b, 0x48fd, "cvtgb",
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0, OP2_u_b, 0x68fd, "cvthb",
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0, OP2_u_w, 0x49, "cvtfw",
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0, OP2_u_w, 0x69, "cvtdw",
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0, OP2_u_w, 0x49fd, "cvtgw",
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0, OP2_u_w, 0x69fd, "cvthw",
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0, OP2_u_l, 0x4a, "cvtfl",
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0, OP2_u_l, 0x6a, "cvtdl",
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0, OP2_u_l, 0x4afd, "cvtgl",
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0, OP2_u_l, 0x6afd, "cvthl",
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0, OP2_u_l, 0x4b, "cvtrfl",
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0, OP2_u_l, 0x6b, "cvtrdl",
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0, OP2_u_l, 0x4bfd, "cvtrgl",
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0, OP2_u_l, 0x6bfd, "cvtrhl",
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0, OP2_u_u, 0x56, "cvtfd",
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0, OP2_u_u, 0x99fd, "cvtfg",
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0, OP2_u_u, 0x98fd, "cvtfh",
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0, OP2_u_u, 0x76, "cvtdf",
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0, OP2_u_u, 0x32fd, "cvtdh",
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0, OP2_u_u, 0x33fd, "cvtgf",
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0, OP2_u_u, 0x56fd, "cvtgh",
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0, OP2_u_u, 0xf6fd, "cvthf",
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0, OP2_u_u, 0xf7fd, "cvthd",
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0, OP2_u_u, 0x76fd, "cvthg",
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0, OP2_u_u, 0x46, "divf2",
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0, OP3_u_u_u, 0x47, "divf3",
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0, OP2_u_u, 0x66, "divd2",
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0, OP3_u_u_u, 0x67, "divd3",
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0, OP2_u_u, 0x46fd, "divg2",
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0, OP3_u_u_u, 0x47fd, "divg3",
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0, OP2_u_u, 0x66fd, "divh2",
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0, OP3_u_u_u, 0x67fd, "divh3",
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0, OP5_u_b_u_l_u, 0x54, "emodf",
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0, OP5_u_b_u_l_u, 0x74, "emodd",
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0, OP5_u_w_u_l_u, 0x54fd, "emodg",
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0, OP5_u_w_u_l_u, 0x74fd, "emodh",
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0, OP2_u_u, 0x52, "mnegf",
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0, OP2_u_u, 0x72, "mnegd",
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0, OP2_u_u, 0x52fd, "mnegg",
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0, OP2_u_u, 0x72fd, "mnegh",
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0, OP2_u_u, 0x50, "movf",
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0, OP2_u_u, 0x70, "movd",
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0, OP2_u_u, 0x50fd, "movg",
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0, OP2_u_u, 0x70fd, "movh",
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0, OP2_u_u, 0x44, "mulf2",
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0, OP3_u_u_u, 0x45, "mulf3",
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0, OP2_u_u, 0x64, "muld2",
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0, OP3_u_u_u, 0x65, "muld3",
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0, OP2_u_u, 0x44fd, "mulg2",
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0, OP3_u_u_u, 0x45fd, "mulg3",
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0, OP2_u_u, 0x64fd, "mulh2",
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0, OP3_u_u_u, 0x65fd, "mulh3",
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0, OP3_u_w_A, 0x55, "polyf",
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0, OP3_u_w_A, 0x75, "polyd",
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0, OP3_u_w_A, 0x55fd, "polyg",
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0, OP3_u_w_A, 0x75fd, "polyh",
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0, OP2_u_u, 0x42, "subf2",
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0, OP3_u_u_u, 0x43, "subf3",
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0, OP2_u_u, 0x62, "subd2",
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0, OP3_u_u_u, 0x63, "subd3",
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0, OP2_u_u, 0x42fd, "subg2",
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0, OP3_u_u_u, 0x43fd, "subg3",
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0, OP2_u_u, 0x62fd, "subh2",
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0, OP3_u_u_u, 0x63fd, "subh3",
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0, OP1_u, 0x53, "tstf",
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0, OP1_u, 0x73, "tstd",
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0, OP1_u, 0x53fd, "tstg",
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0, OP1_u, 0x73fd, "tsth",
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/* Character string instructions */
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0, OP3_w_A_A, 0x29, "cmpc3",
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0, OP5_w_A_b_w_A, 0x2d, "cmpc5",
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0, OP3_b_w_A, 0x3a, "locc",
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0, OP4_w_A_w_A, 0x39, "matchc",
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0, OP3_w_A_A, 0x28, "movc3",
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0, OP5_w_A_b_w_A, 0x2c, "movc5",
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0, OP6_w_A_b_A_w_A,0x2e, "movtc",
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0, OP6_w_A_b_A_w_A,0x2f, "movtuc",
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0, OP4_w_A_A_b, 0x2a, "scanc",
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0, OP3_b_w_A, 0x3b, "skpc",
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0, OP4_w_A_A_b, 0x2b, "spanc",
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/* Cyclic redundancy check instructions */
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0, OP4_A_l_w_A, 0x0b, "crc",
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/* Decimal string instructions */
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0, OP4_w_A_w_A, 0x20, "addp4",
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0, OP6_w_A_w_A_w_A,0x21, "addp6",
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0, OP6_b_w_A_b_w_A,0xf8, "ashp",
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0, OP3_w_A_A, 0x35, "cmpp3",
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0, OP4_w_A_w_A, 0x37, "cmpp4",
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0, OP3_l_w_A, 0xf9, "cvtlp",
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0, OP3_w_A_l, 0x36, "cvtpl",
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0, OP4_w_A_w_A, 0x08, "cvtps",
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0, OP5_w_A_A_w_A, 0x24, "cvtpt",
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0, OP4_w_A_w_A, 0x09, "cvtsp",
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0, OP5_w_A_A_w_A, 0x26, "cvttp",
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0, OP6_w_A_w_A_w_A,0x27, "divp",
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0, OP3_w_A_A, 0x34, "movp",
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0, OP6_w_A_w_A_w_A,0x25, "mulp",
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0, OP4_w_A_w_A, 0x22, "subp4",
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0, OP6_w_A_w_A_w_A,0x23, "subp6",
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/* Edit instruction */
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0, OP4_w_A_A_A, 0x38, "editpc",
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/* Other VAX-11 instructions */
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1990-01-17 16:05:00 +00:00
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/* BSD 4.3 adb has a different opinion of the bugw and bugl instructions:
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it thinks that an addressing mode byte is required. However, according
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to the VAX-11 Architecture Reference Manual, Revision 6.1, 1982, the
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access type is b, which means that the operand is a branch displacement.
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*/
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0, OP1_Bw, 0xfeff, "bugw",
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0, OP1_Bl, 0xfdff, "bugl",
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1990-01-12 16:55:50 +00:00
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0, OP3_b_w_A, 0x0c, "prober",
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0, OP3_b_w_A, 0x0d, "probew",
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0, OP0, 0x02, "rei",
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0, OP1_w, 0xbc, "chmk",
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0, OP1_w, 0xbd, "chme",
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0, OP1_w, 0xbe, "chms",
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0, OP1_w, 0xbf, "chmu",
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0, OP0, 0x06, "ldpctx",
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0, OP0, 0x07, "svpctx",
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0, OP2_l_l, 0xda, "mtpr",
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0, OP2_l_l, 0xdb, "mfpr",
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