1985-03-18 12:46:51 +00:00
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.define .dvi2
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1987-01-28 18:57:04 +00:00
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.sect .text
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.sect .rom
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.sect .data
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.sect .bss
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.sect .text
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1985-03-18 12:46:51 +00:00
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! 16 bits signed and unsigned integer divide and remainder routine
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! Bit 0 of a-reg is set iff quotient has to be delivered
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! Bit 7 of a-reg is set iff the operands are signed, so:
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! Expects in a-reg: 0 if called by rmu 2
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! 1 if called by dvu 2
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! 128 if called by rmi 2
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! 129 if called by dvi 2
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! Expects on stack: divisor
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! dividend
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! Yields in de-reg: quotient or remainder
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.dvi2: pop h
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shld .retadr
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mov h,b
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mov l,c
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shld .bcreg
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sta .areg
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pop b ! bc = divisor
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mov a,b ! trap if divisor = 0
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ora c
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cz eidivz
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pop d ! de = dividend
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mvi h,0
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lda .areg
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ral
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jnc 0f ! jump if unsigned
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mov a,d
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ral
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jnc 1f ! jump if dividend >= 0
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mvi h,129 ! indicate dividend is negative
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xra a ! negate dividend
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sub e
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mov e,a
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mvi a,0
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sbb d
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mov d,a
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! de is positive now
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1: mov a,b
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ral
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jc 2f ! jump if divisor < 0
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0: inr h ! indicate negation
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xra a ! negate divisor
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sub c
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mov c,a
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mvi a,0
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sbb b
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mov b,a
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! bc is negative now
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2: push h ! save h-reg
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lxi h,0 ! initial value of remainder
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mvi a,16 ! initialize loop counter
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3: push psw ! save loop counter
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dad h ! shift left: hl <- de <- 0
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xchg
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dad h
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xchg
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jnc 4f
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inx h
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4: push h ! save remainder
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dad b ! subtract divisor (add negative)
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jnc 5f
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xthl
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inx d
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5: pop h
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pop psw ! restore loop counter
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dcr a
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jnz 3b
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pop b ! b-reg becomes what once was h-reg
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lda .areg
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rar ! what has to be delivered: quotient or remainder?
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jnc 6f
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! for dvi 2 and dvu 2 only:
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mov a,b
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rar
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jc 8f ! jump if divisor and dividend had same sign
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xra a ! negate quotient
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sub e
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mov e,a
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mvi a,0
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sbb d
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mov d,a
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jmp 8f
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! for rmi 2 and rmu 2 only:
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6: mov a,b
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ral
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jnc 7f ! negate remainder if dividend was negative
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xra a
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sub l
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mov l,a
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mvi a,0
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sbb h
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mov h,a
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7: mov d,h ! return remainder
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mov e,l
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8: lhld .bcreg
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mov b,h
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mov c,l
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lhld .retadr
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pchl
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