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ack/util/mcgg/ir.dat

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IR codes are now owned by mcgg; ir terminals are inserted into the table during compilation (so you can refer to them).
2016-09-24 16:31:35 +00:00
# Flags:
# S: has size (use in CONST1, CONST2, CONST4, CONST8 forms)
# V: has no size (use in JUMP, CJUMP, RET forms)
# Simple terminals
We're going to need some type inference after all, I think. Let's do a little for now and see how it goes.
2016-10-01 17:10:22 +00:00
S CONST # must be followed by float form
S CONSTF
Instruction selection now happens on a shadow tree, rather than on the IR tree itself. Currently it's semantically the same but the implementation is cleaner.
2016-10-03 18:52:36 +00:00
V REG
V NOP
You know what, the type inference stuff is a complete red herring. What this actually needs is a more intelligent register allocator. So, remove the type inference.
2016-09-29 17:58:02 +00:00
S LABEL
S BLOCK
V PAIR
S ANY
S LOCAL
Instruction selection now happens on a shadow tree, rather than on the IR tree itself. Currently it's semantically the same but the implementation is cleaner.
2016-10-03 18:52:36 +00:00
V PHI
IR codes are now owned by mcgg; ir terminals are inserted into the table during compilation (so you can refer to them).
2016-09-24 16:31:35 +00:00
# Magic stack operations
You know what, the type inference stuff is a complete red herring. What this actually needs is a more intelligent register allocator. So, remove the type inference.
2016-09-29 17:58:02 +00:00
S PUSH
We're going to need some type inference after all, I think. Let's do a little for now and see how it goes.
2016-10-01 17:10:22 +00:00
S POP # must be followed by float form
S POPF
Keep more data around about ir instructions. Implement a half-baked type inference routine to propagate information about floats up the tree, so we know whether to put floats into special registers as early as possible.
2016-09-26 20:12:46 +00:00
#... Memory operations
We're going to need some type inference after all, I think. Let's do a little for now and see how it goes.
2016-10-01 17:10:22 +00:00
S LOAD # must be followed by float form
S LOADF
You know what, the type inference stuff is a complete red herring. What this actually needs is a more intelligent register allocator. So, remove the type inference.
2016-09-29 17:58:02 +00:00
S STORE
Add (pretty crummy) support for register aliases and static pairs of registers. We should have enough functionality now for rather buggy 8-bit ints and doubles. Rework the table and the platform.c to match.
2016-10-21 21:31:00 +00:00
S STOREF
IR codes are now owned by mcgg; ir terminals are inserted into the table during compilation (so you can refer to them).
2016-09-24 16:31:35 +00:00
# Arithemetic operations
You know what, the type inference stuff is a complete red herring. What this actually needs is a more intelligent register allocator. So, remove the type inference.
2016-09-29 17:58:02 +00:00
S ADD
S SUB
S MUL
S DIV
Hacky workaround the way the Modula-2 compiler generates non-standard sized loads and saves. More opcodes; simplified table using macros.
2016-10-22 08:48:22 +00:00
S DIVU
You know what, the type inference stuff is a complete red herring. What this actually needs is a more intelligent register allocator. So, remove the type inference.
2016-09-29 17:58:02 +00:00
S MOD
S NEG
Keep more data around about ir instructions. Implement a half-baked type inference routine to propagate information about floats up the tree, so we know whether to put floats into special registers as early as possible.
2016-09-26 20:12:46 +00:00
You know what, the type inference stuff is a complete red herring. What this actually needs is a more intelligent register allocator. So, remove the type inference.
2016-09-29 17:58:02 +00:00
S ADDF
S SUBF
S MULF
S DIVF
S NEGF
Keep more data around about ir instructions. Implement a half-baked type inference routine to propagate information about floats up the tree, so we know whether to put floats into special registers as early as possible.
2016-09-26 20:12:46 +00:00
You know what, the type inference stuff is a complete red herring. What this actually needs is a more intelligent register allocator. So, remove the type inference.
2016-09-29 17:58:02 +00:00
S AND
S OR
S EOR
S NOT
The register allocator now makes a spirited attempt to honour register attributes when allocating. Unfortunately, backward edges don't work (because the limited def-use chain stuff doesn't work across basic blocks). Needs more thought.
2016-10-09 13:09:34 +00:00
S ASL
S ASR
S LSL
S LSR
Keep more data around about ir instructions. Implement a half-baked type inference routine to propagate information about floats up the tree, so we know whether to put floats into special registers as early as possible.
2016-09-26 20:12:46 +00:00
IR codes are now owned by mcgg; ir terminals are inserted into the table during compilation (so you can refer to them).
2016-09-24 16:31:35 +00:00
# Conversions
You know what, the type inference stuff is a complete red herring. What this actually needs is a more intelligent register allocator. So, remove the type inference.
2016-09-29 17:58:02 +00:00
S CII1
S CII2
S CII4
S CII8
Keep more data around about ir instructions. Implement a half-baked type inference routine to propagate information about floats up the tree, so we know whether to put floats into special registers as early as possible.
2016-09-26 20:12:46 +00:00
You know what, the type inference stuff is a complete red herring. What this actually needs is a more intelligent register allocator. So, remove the type inference.
2016-09-29 17:58:02 +00:00
S CIU1
S CIU2
S CIU4
S CIU8
Keep more data around about ir instructions. Implement a half-baked type inference routine to propagate information about floats up the tree, so we know whether to put floats into special registers as early as possible.
2016-09-26 20:12:46 +00:00
Keep track of register types as well as attributes --- the type being how we find new registers when evicting values. Input constraints work (they were being ignored before). Various bug fixing so they actually work.
2016-10-12 20:58:46 +00:00
S CUI1
S CUI2
S CUI4
S CUI8
Lots more opcodes; better eviction behaviour; better register moves. Lots more PowerPC stuff (some working).
2016-10-19 21:29:05 +00:00
S CFI1
S CFI2
S CFI4
S CFI8
S CIF1
S CIF2
S CIF4
S CIF8
Better (and more correct) floating point conversions; fif; various new opcodes.
2016-10-21 22:48:26 +00:00
S CFF1
S CFF2
S CFF4
S CFF8
IR codes are now owned by mcgg; ir terminals are inserted into the table during compilation (so you can refer to them).
2016-09-24 16:31:35 +00:00
# Tristate comparisons
Better (and more correct) floating point conversions; fif; various new opcodes.
2016-10-21 22:48:26 +00:00
S COMPARES1
S COMPARES2
S COMPARES4
S COMPARES8
S COMPAREU1
S COMPAREU2
S COMPAREU4
S COMPAREU8
S COMPAREF1
S COMPAREF2
S COMPAREF4
S COMPAREF8
Keep more data around about ir instructions. Implement a half-baked type inference routine to propagate information about floats up the tree, so we know whether to put floats into special registers as early as possible.
2016-09-26 20:12:46 +00:00
IR codes are now owned by mcgg; ir terminals are inserted into the table during compilation (so you can refer to them).
2016-09-24 16:31:35 +00:00
# Boolean comparisons
You know what, the type inference stuff is a complete red herring. What this actually needs is a more intelligent register allocator. So, remove the type inference.
2016-09-29 17:58:02 +00:00
S IFEQ
S IFLT
S IFLE
Keep more data around about ir instructions. Implement a half-baked type inference routine to propagate information about floats up the tree, so we know whether to put floats into special registers as early as possible.
2016-09-26 20:12:46 +00:00
IR codes are now owned by mcgg; ir terminals are inserted into the table during compilation (so you can refer to them).
2016-09-24 16:31:35 +00:00
# Procedures
You know what, the type inference stuff is a complete red herring. What this actually needs is a more intelligent register allocator. So, remove the type inference.
2016-09-29 17:58:02 +00:00
V CALL
Keep more data around about ir instructions. Implement a half-baked type inference routine to propagate information about floats up the tree, so we know whether to put floats into special registers as early as possible.
2016-09-26 20:12:46 +00:00
IR codes are now owned by mcgg; ir terminals are inserted into the table during compilation (so you can refer to them).
2016-09-24 16:31:35 +00:00
# Flow control --- these never return
You know what, the type inference stuff is a complete red herring. What this actually needs is a more intelligent register allocator. So, remove the type inference.
2016-09-29 17:58:02 +00:00
V JUMP
V CJUMPEQ
V CJUMPLT
V CJUMPLE
V RET
IR codes are now owned by mcgg; ir terminals are inserted into the table during compilation (so you can refer to them).
2016-09-24 16:31:35 +00:00
# Special
You know what, the type inference stuff is a complete red herring. What this actually needs is a more intelligent register allocator. So, remove the type inference.
2016-09-29 17:58:02 +00:00
S STACKADJUST
S GETRET
S SETRET
Add a pile of new instructions used by Pascal; I'm going to need to think about how locals and the local base are handled.
2016-10-15 11:07:59 +00:00
S GETFP
More opcodes.
2016-10-22 09:26:28 +00:00
S GETSP
S SETSP
Add a pile of new instructions used by Pascal; I'm going to need to think about how locals and the local base are handled.
2016-10-15 11:07:59 +00:00
S CHAINFP
S FPTOARGS
IR codes are now owned by mcgg; ir terminals are inserted into the table during compilation (so you can refer to them).
2016-09-24 16:31:35 +00:00
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