322 lines
8.8 KiB
C
322 lines
8.8 KiB
C
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/*
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m68kmmu.h - PMMU implementation for 68851/68030/68040
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By R. Belmont
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Copyright Nicola Salmoria and the MAME Team.
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Visit http://mamedev.org for licensing and usage restrictions.
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*/
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/*
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pmmu_translate_addr: perform 68851/68030-style PMMU address translation
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*/
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uint pmmu_translate_addr(uint addr_in)
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{
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uint32 addr_out, tbl_entry = 0, tbl_entry2, tamode = 0, tbmode = 0, tcmode = 0;
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uint root_aptr, root_limit, tofs, is, abits, bbits, cbits;
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uint resolved, tptr, shift;
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resolved = 0;
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addr_out = addr_in;
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// if SRP is enabled and we're in supervisor mode, use it
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if ((m68ki_cpu.mmu_tc & 0x02000000) && (m68ki_get_sr() & 0x2000))
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{
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root_aptr = m68ki_cpu.mmu_srp_aptr;
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root_limit = m68ki_cpu.mmu_srp_limit;
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}
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else // else use the CRP
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{
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root_aptr = m68ki_cpu.mmu_crp_aptr;
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root_limit = m68ki_cpu.mmu_crp_limit;
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}
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// get initial shift (# of top bits to ignore)
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is = (m68ki_cpu.mmu_tc>>16) & 0xf;
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abits = (m68ki_cpu.mmu_tc>>12)&0xf;
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bbits = (m68ki_cpu.mmu_tc>>8)&0xf;
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cbits = (m68ki_cpu.mmu_tc>>4)&0xf;
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// fprintf(stderr,"PMMU: tcr %08x limit %08x aptr %08x is %x abits %d bbits %d cbits %d\n", m68ki_cpu.mmu_tc, root_limit, root_aptr, is, abits, bbits, cbits);
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// get table A offset
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tofs = (addr_in<<is)>>(32-abits);
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// find out what format table A is
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switch (root_limit & 3)
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{
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case 0: // invalid, should cause MMU exception
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case 1: // page descriptor, should cause direct mapping
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fatalerror("680x0 PMMU: Unhandled root mode\n");
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break;
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case 2: // valid 4 byte descriptors
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tofs *= 4;
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// fprintf(stderr,"PMMU: reading table A entry at %08x\n", tofs + (root_aptr & 0xfffffffc));
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tbl_entry = m68k_read_memory_32( tofs + (root_aptr & 0xfffffffc));
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tamode = tbl_entry & 3;
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// fprintf(stderr,"PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tamode, tofs);
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break;
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case 3: // valid 8 byte descriptors
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tofs *= 8;
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// fprintf(stderr,"PMMU: reading table A entries at %08x\n", tofs + (root_aptr & 0xfffffffc));
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tbl_entry2 = m68k_read_memory_32( tofs + (root_aptr & 0xfffffffc));
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tbl_entry = m68k_read_memory_32( tofs + (root_aptr & 0xfffffffc)+4);
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tamode = tbl_entry2 & 3;
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// fprintf(stderr,"PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tamode, tofs);
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break;
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}
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// get table B offset and pointer
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tofs = (addr_in<<(is+abits))>>(32-bbits);
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tptr = tbl_entry & 0xfffffff0;
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// find out what format table B is, if any
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switch (tamode)
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{
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case 0: // invalid, should cause MMU exception
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fatalerror("680x0 PMMU: Unhandled Table A mode %d (addr_in %08x)\n", tamode, addr_in);
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break;
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case 2: // 4-byte table B descriptor
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tofs *= 4;
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// fprintf(stderr,"PMMU: reading table B entry at %08x\n", tofs + tptr);
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tbl_entry = m68k_read_memory_32( tofs + tptr);
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tbmode = tbl_entry & 3;
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// fprintf(stderr,"PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tbmode, tofs);
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break;
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case 3: // 8-byte table B descriptor
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tofs *= 8;
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// fprintf(stderr,"PMMU: reading table B entries at %08x\n", tofs + tptr);
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tbl_entry2 = m68k_read_memory_32( tofs + tptr);
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tbl_entry = m68k_read_memory_32( tofs + tptr + 4);
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tbmode = tbl_entry2 & 3;
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// fprintf(stderr,"PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tbmode, tofs);
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break;
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case 1: // early termination descriptor
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tbl_entry &= 0xffffff00;
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shift = is+abits;
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addr_out = ((addr_in<<shift)>>shift) + tbl_entry;
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resolved = 1;
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break;
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}
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// if table A wasn't early-out, continue to process table B
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if (!resolved)
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{
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// get table C offset and pointer
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tofs = (addr_in<<(is+abits+bbits))>>(32-cbits);
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tptr = tbl_entry & 0xfffffff0;
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switch (tbmode)
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{
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case 0: // invalid, should cause MMU exception
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fatalerror("680x0 PMMU: Unhandled Table B mode %d (addr_in %08x PC %x)\n", tbmode, addr_in, REG_PC);
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break;
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case 2: // 4-byte table C descriptor
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tofs *= 4;
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// fprintf(stderr,"PMMU: reading table C entry at %08x\n", tofs + tptr);
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tbl_entry = m68k_read_memory_32(tofs + tptr);
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tcmode = tbl_entry & 3;
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// fprintf(stderr,"PMMU: addr %08x entry %08x mode %x tofs %x\n", addr_in, tbl_entry, tbmode, tofs);
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break;
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case 3: // 8-byte table C descriptor
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tofs *= 8;
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// fprintf(stderr,"PMMU: reading table C entries at %08x\n", tofs + tptr);
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tbl_entry2 = m68k_read_memory_32(tofs + tptr);
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tbl_entry = m68k_read_memory_32(tofs + tptr + 4);
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tcmode = tbl_entry2 & 3;
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// fprintf(stderr,"PMMU: addr %08x entry %08x entry2 %08x mode %x tofs %x\n", addr_in, tbl_entry, tbl_entry2, tbmode, tofs);
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break;
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case 1: // termination descriptor
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tbl_entry &= 0xffffff00;
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shift = is+abits+bbits;
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addr_out = ((addr_in<<shift)>>shift) + tbl_entry;
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resolved = 1;
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break;
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}
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}
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if (!resolved)
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{
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switch (tcmode)
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{
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case 0: // invalid, should cause MMU exception
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case 2: // 4-byte ??? descriptor
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case 3: // 8-byte ??? descriptor
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fatalerror("680x0 PMMU: Unhandled Table B mode %d (addr_in %08x PC %x)\n", tbmode, addr_in, REG_PC);
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break;
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case 1: // termination descriptor
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tbl_entry &= 0xffffff00;
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shift = is+abits+bbits+cbits;
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addr_out = ((addr_in<<shift)>>shift) + tbl_entry;
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resolved = 1;
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break;
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}
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}
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// fprintf(stderr,"PMMU: [%08x] => [%08x]\n", addr_in, addr_out);
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return addr_out;
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}
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/*
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m68881_mmu_ops: COP 0 MMU opcode handling
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*/
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void m68881_mmu_ops()
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{
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uint16 modes;
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uint32 ea = m68ki_cpu.ir & 0x3f;
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uint64 temp64;
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// catch the 2 "weird" encodings up front (PBcc)
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if ((m68ki_cpu.ir & 0xffc0) == 0xf0c0)
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{
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fprintf(stderr,"680x0: unhandled PBcc\n");
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return;
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}
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else if ((m68ki_cpu.ir & 0xffc0) == 0xf080)
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{
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fprintf(stderr,"680x0: unhandled PBcc\n");
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return;
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}
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else // the rest are 1111000xxxXXXXXX where xxx is the instruction family
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{
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switch ((m68ki_cpu.ir>>9) & 0x7)
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{
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case 0:
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modes = OPER_I_16();
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if ((modes & 0xfde0) == 0x2000) // PLOAD
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{
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fprintf(stderr,"680x0: unhandled PLOAD\n");
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return;
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}
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else if ((modes & 0xe200) == 0x2000) // PFLUSH
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{
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fprintf(stderr,"680x0: unhandled PFLUSH PC=%x\n", REG_PC);
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return;
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}
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else if (modes == 0xa000) // PFLUSHR
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{
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fprintf(stderr,"680x0: unhandled PFLUSHR\n");
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return;
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}
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else if (modes == 0x2800) // PVALID (FORMAT 1)
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{
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fprintf(stderr,"680x0: unhandled PVALID1\n");
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return;
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}
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else if ((modes & 0xfff8) == 0x2c00) // PVALID (FORMAT 2)
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{
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fprintf(stderr,"680x0: unhandled PVALID2\n");
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return;
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}
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else if ((modes & 0xe000) == 0x8000) // PTEST
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{
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fprintf(stderr,"680x0: unhandled PTEST\n");
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return;
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}
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else
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{
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switch ((modes>>13) & 0x7)
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{
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case 0: // MC68030/040 form with FD bit
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case 2: // MC68881 form, FD never set
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if (modes & 0x200)
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{
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switch ((modes>>10) & 7)
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{
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case 0: // translation control register
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WRITE_EA_32(ea, m68ki_cpu.mmu_tc);
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break;
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case 2: // supervisor root pointer
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WRITE_EA_64(ea, (uint64)m68ki_cpu.mmu_srp_limit<<32 | (uint64)m68ki_cpu.mmu_srp_aptr);
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break;
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case 3: // CPU root pointer
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WRITE_EA_64(ea, (uint64)m68ki_cpu.mmu_crp_limit<<32 | (uint64)m68ki_cpu.mmu_crp_aptr);
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break;
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default:
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fprintf(stderr,"680x0: PMOVE from unknown MMU register %x, PC %x\n", (modes>>10) & 7, REG_PC);
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break;
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}
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}
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else
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{
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switch ((modes>>10) & 7)
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{
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case 0: // translation control register
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m68ki_cpu.mmu_tc = READ_EA_32(ea);
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if (m68ki_cpu.mmu_tc & 0x80000000)
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{
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m68ki_cpu.pmmu_enabled = 1;
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}
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else
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{
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m68ki_cpu.pmmu_enabled = 0;
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}
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break;
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case 2: // supervisor root pointer
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temp64 = READ_EA_64(ea);
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m68ki_cpu.mmu_srp_limit = (temp64>>32) & 0xffffffff;
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m68ki_cpu.mmu_srp_aptr = temp64 & 0xffffffff;
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break;
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case 3: // CPU root pointer
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temp64 = READ_EA_64(ea);
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m68ki_cpu.mmu_crp_limit = (temp64>>32) & 0xffffffff;
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m68ki_cpu.mmu_crp_aptr = temp64 & 0xffffffff;
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break;
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default:
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fprintf(stderr,"680x0: PMOVE to unknown MMU register %x, PC %x\n", (modes>>10) & 7, REG_PC);
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break;
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}
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}
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break;
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case 3: // MC68030 to/from status reg
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if (modes & 0x200)
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{
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WRITE_EA_32(ea, m68ki_cpu.mmu_sr);
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}
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else
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{
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m68ki_cpu.mmu_sr = READ_EA_32(ea);
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}
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break;
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default:
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fprintf(stderr,"680x0: unknown PMOVE mode %x (modes %04x) (PC %x)\n", (modes>>13) & 0x7, modes, REG_PC);
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break;
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}
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}
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break;
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default:
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fprintf(stderr,"680x0: unknown PMMU instruction group %d\n", (m68ki_cpu.ir>>9) & 0x7);
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break;
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}
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}
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}
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