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ack/mach/powerpc/as/mach3.c

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Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/*
* $Source$
* $State$
*/
/* Integer registers */
0, GPR, 0, "r0",
0, GPR, 1, "r1",
0, GPR, 1, "sp",
0, GPR, 2, "r2",
0, GPR, 2, "fp",
0, GPR, 3, "r3",
0, GPR, 4, "r4",
0, GPR, 5, "r5",
0, GPR, 6, "r6",
0, GPR, 7, "r7",
0, GPR, 8, "r8",
0, GPR, 9, "r9",
0, GPR, 10, "r10",
0, GPR, 11, "r11",
0, GPR, 12, "r12",
0, GPR, 13, "r13",
0, GPR, 14, "r14",
0, GPR, 15, "r15",
0, GPR, 16, "r16",
0, GPR, 17, "r17",
0, GPR, 18, "r18",
0, GPR, 19, "r19",
0, GPR, 20, "r20",
0, GPR, 21, "r21",
0, GPR, 22, "r22",
0, GPR, 23, "r23",
0, GPR, 24, "r24",
0, GPR, 25, "r25",
0, GPR, 26, "r26",
0, GPR, 27, "r27",
0, GPR, 28, "r28",
0, GPR, 29, "r29",
0, GPR, 30, "r30",
0, GPR, 31, "r31",
/* Floating-point registers */
0, FPR, 0, "f0",
0, FPR, 1, "f1",
0, FPR, 2, "f2",
0, FPR, 3, "f3",
0, FPR, 4, "f4",
0, FPR, 5, "f5",
0, FPR, 6, "f6",
0, FPR, 7, "f7",
0, FPR, 8, "f8",
0, FPR, 9, "f9",
0, FPR, 10, "f10",
0, FPR, 11, "f11",
0, FPR, 12, "f12",
0, FPR, 13, "f13",
0, FPR, 14, "f14",
0, FPR, 15, "f15",
0, FPR, 16, "f16",
0, FPR, 17, "f17",
0, FPR, 18, "f18",
0, FPR, 19, "f19",
0, FPR, 20, "f20",
0, FPR, 21, "f21",
0, FPR, 22, "f22",
0, FPR, 23, "f23",
0, FPR, 24, "f24",
0, FPR, 25, "f25",
0, FPR, 26, "f26",
0, FPR, 27, "f27",
0, FPR, 28, "f28",
0, FPR, 29, "f29",
0, FPR, 30, "f30",
0, FPR, 31, "f31",
/* Special registers */
0, SPR, 32, "xer",
0, SPR, 256, "lr",
0, SPR, 288, "ctr",
/* Condition registers */
0, CR, 0, "cr0",
0, CR, 1, "cr1",
0, CR, 2, "cr2",
0, CR, 3, "cr3",
0, CR, 4, "cr4",
0, CR, 5, "cr5",
0, CR, 6, "cr6",
0, CR, 7, "cr7",
/* Condition code flag */
0, C, 0, ".",
/* Special instructions */
Rename our pseudo-opcode 'la' to 'li32'. GNU as has "la %r4,8(%r3)" as an alias for "addi %r4,%r3,8", meaning to load the address of the thing at 8(%r3). Our 'la', now 'li32', makes an addis/ori pair to load an immediate 32-bit value. For example, "li32 r4,23456789" loads a big number.
2016-09-18 21:03:23 +00:00
0, OP_LI32, 0, "li32",
Eliminate the RELOH2 relocation, as it never worked --- the address would be calculated incorrectly because of overflow errors. Replace it with an extended RELOPPC relocation which understands addis/ori pairs; add an la pseudoop to the assembler which generates these and the appropriate relocation. Make good. --HG-- branch : dtrg-experimental-powerpc-branch
2016-09-17 10:43:15 +00:00
0, OP_LA, 0, "la",
Add li and mr pseudoinstructions.
2016-10-17 22:21:32 +00:00
0, OP_LA, 0, "li",
0, OP_RS_RA_RA_C, 31<<26 | 444<<1, "mr",
Archival checkin (semi-working code).
2007-11-02 18:56:58 +00:00
/* Branch processor instructions (page 20) */
0, OP_LIL, 18<<26 | 0<<1 | 0<<0, "b",
0, OP_LIA, 18<<26 | 1<<1 | 0<<0, "ba",
0, OP_LIL, 18<<26 | 0<<1 | 1<<0, "bl",
0, OP_LIA, 18<<26 | 1<<1 | 1<<0, "bla",
0, OP_BO_BI_BDL, 16<<26 | 0<<1 | 0<<0, "bc",
0, OP_BO_BI_BDA, 16<<26 | 1<<1 | 0<<0, "bca",
0, OP_BO_BI_BDL, 16<<26 | 0<<1 | 1<<0, "bcl",
0, OP_BO_BI_BDA, 16<<26 | 1<<1 | 1<<0, "bcla",
0, OP_BO_BI_BH, 19<<26 | 16<<1 | 0<<0, "bclr",
0, OP_BO_BI_BH, 19<<26 | 16<<1 | 1<<0, "bclrl",
0, OP_BO_BI_BH, 19<<26 | 528<<1 | 0<<0, "bcctr",
0, OP_BO_BI_BH, 19<<26 | 528<<1 | 1<<0, "bcctrl",
0, OP_LEV, 17<<26 | 1<<1, "sc",
0, OP_BT_BA_BB, 19<<26 | 257<<1, "crand",
0, OP_BT_BA_BB, 19<<26 | 449<<1, "cror",
0, OP_BT_BA_BB, 19<<26 | 193<<1, "crxor",
0, OP_BT_BA_BB, 19<<26 | 225<<1, "crnand",
0, OP_BT_BA_BB, 19<<26 | 33<<1, "crnor",
0, OP_BT_BA_BB, 19<<26 | 289<<1, "crneqv",
0, OP_BT_BA_BB, 19<<26 | 129<<1, "crandc",
0, OP_BT_BA_BB, 19<<26 | 417<<1, "crorc",
0, OP_BF_BFA, 19<<26 | 0<<1, "mcrf",
/* Fixed point instructions (page 29) */
0, OP_RT_RA_D, 34<<26, "lbz",
0, OP_RT_RA_RB, 31<<26 | 87<<1, "lbzx",
0, OP_RT_RA_D, 35<<26, "lbzu",
0, OP_RT_RA_RB, 31<<26 | 119<<1, "lbzux",
0, OP_RT_RA_D, 40<<26, "lhz",
0, OP_RT_RA_RB, 31<<26 | 279<<1, "lhzx",
0, OP_RT_RA_D, 41<<26, "lhzu",
0, OP_RT_RA_RB, 31<<26 | 311<<1, "lhzux",
0, OP_RT_RA_D, 42<<26, "lha",
0, OP_RT_RA_RB, 31<<26 | 343<<1, "lhax",
0, OP_RT_RA_D, 43<<26, "lhau",
0, OP_RT_RA_RB, 31<<26 | 375<<1, "lhaux",
0, OP_RT_RA_D, 32<<26, "lwz",
0, OP_RT_RA_RB, 31<<26 | 23<<1, "lwzx",
0, OP_RT_RA_D, 33<<26, "lwzu",
0, OP_RT_RA_RB, 31<<26 | 55<<1, "lwzux",
0, OP_RT_RA_DS, 58<<26 | 2<<0, "lwa",
0, OP_RT_RA_RB, 31<<26 | 341<<1, "lwax",
0, OP_RT_RA_RB, 31<<26 | 363<<1, "lwaux",
0, OP_RT_RA_DS, 58<<26, "ld",
0, OP_RT_RA_RB, 31<<26 | 21<<1, "ldx",
0, OP_RT_RA_DS, 58<<26 | 1<<0, "ldu",
0, OP_RT_RA_RB, 31<<26 | 53<<1, "ldux",
0, OP_RS_RA_D, 38<<26, "stb",
0, OP_RS_RA_RB, 31<<26 | 215<<1, "stbx",
0, OP_RS_RA_D, 39<<26, "stbu",
0, OP_RS_RA_RB, 31<<26 | 247<<1, "stbux",
0, OP_RS_RA_D, 44<<26, "sth",
0, OP_RS_RA_RB, 31<<26 | 407<<1, "sthx",
0, OP_RS_RA_D, 45<<26, "sthu",
0, OP_RS_RA_RB, 31<<26 | 439<<1, "sthux",
0, OP_RS_RA_D, 36<<26, "stw",
0, OP_RS_RA_RB, 31<<26 | 151<<1, "stwx",
0, OP_RS_RA_D, 37<<26, "stwu",
0, OP_RS_RA_RB, 31<<26 | 183<<1, "stwux",
0, OP_RS_RA_DS, 62<<26, "std",
0, OP_RS_RA_RB, 31<<26 | 149<<1, "stdx",
0, OP_RS_RA_DS, 62<<26 | 1<<0, "stdu",
0, OP_RS_RA_RB, 31<<26 | 181<<1, "stdux",
/* page 42 */
0, OP_RT_RA_RB, 31<<26 | 790<<1, "lhbrx",
0, OP_RT_RA_RB, 31<<26 | 534<<1, "lwbrx",
0, OP_RS_RA_RB, 31<<26 | 918<<1, "sthbrx",
0, OP_RS_RA_RB, 31<<26 | 662<<1, "stwbrx",
/* page 44 */
0, OP_RT_RA_D, 46<<26, "lmw",
0, OP_RS_RA_D, 47<<26, "stmw",
/* page 45 */
0, OP_RT_RA_NB, 31<<26 | 597<<1, "lswi",
0, OP_RT_RA_RB, 31<<26 | 533<<1, "lswx",
0, OP_RS_RA_NB, 31<<26 | 725<<1, "stswi",
0, OP_RS_RA_RB, 31<<26 | 661<<1, "stswx",
/* page 49 */
0, OP_RT_RA_SI, 14<<26, "addi",
0, OP_RT_RA_SI, 15<<26, "addis",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 266<<1, "add",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 266<<1, "addo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 40<<1, "subf",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 40<<1, "subfo",
0, OP_RT_RA_SI_addic, 12<<26, "addic", /* special case C */
0, OP_RT_RA_SI, 8<<26, "subfic",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 138<<1, "adde",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 138<<1, "addeo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 136<<1, "subfe",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 136<<1, "subfeo",
0, OP_RT_RA_C, 31<<26 | 0<<10 | 234<<1, "addme",
0, OP_RT_RA_C, 31<<26 | 1<<10 | 234<<1, "addmeo",
0, OP_RT_RA_C, 31<<26 | 0<<10 | 232<<1, "subfme",
0, OP_RT_RA_C, 31<<26 | 1<<10 | 232<<1, "subfmeo",
0, OP_RT_RA_C, 31<<26 | 0<<10 | 202<<1, "addze",
0, OP_RT_RA_C, 31<<26 | 1<<10 | 202<<1, "addzeo",
0, OP_RT_RA_C, 31<<26 | 0<<10 | 200<<1, "subfze",
0, OP_RT_RA_C, 31<<26 | 1<<10 | 200<<1, "subfzeo",
0, OP_RT_RA_C, 31<<26 | 0<<10 | 104<<1, "neg",
0, OP_RT_RA_C, 31<<26 | 1<<10 | 104<<1, "nego",
/* page 54 */
0, OP_RT_RA_SI, 7<<26, "mulli",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 233<<1, "mulld",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 233<<1, "mulldo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 235<<1, "mullw",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 235<<1, "mullwo",
0, OP_RT_RA_RB_C, 31<<26 | 73<<1, "mulhd",
0, OP_RT_RA_RB_C, 31<<26 | 75<<1, "mulhw",
0, OP_RT_RA_RB_C, 31<<26 | 9<<1, "mulhdu",
0, OP_RT_RA_RB_C, 31<<26 | 11<<1, "mulhwu",
/* page 56 */
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 489<<1, "divd",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 489<<1, "divdo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 491<<1, "divw",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 491<<1, "divwo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 457<<1, "divdu",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 457<<1, "divduo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 459<<1, "divwu",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 459<<1, "divwuo",
/* page 58 */
0, OP_BF_L_RA_SI, 11<<26, "cmpi",
0, OP_BF_L_RA_RB, 31<<26 | 0<<1, "cmp",
0, OP_BF_L_RA_UI, 10<<26, "cmpli",
0, OP_BF_L_RA_RB, 31<<26 | 32<<1, "cmpl",
/* page 60 */
0, OP_TO_RA_SI, 2<<26, "tdi",
0, OP_TO_RA_SI, 3<<26, "twi",
0, OP_TO_RA_RB, 31<<26 | 68<<1, "td",
0, OP_TO_RA_RB, 31<<26 | 4<<1, "tw",
/* page 62 */
0, OP_RS_RA_UI_CC, 28<<26, "andi", /* C compulsory */
0, OP_RS_RA_UI_CC, 29<<26, "andis", /* C compulsory */
0, OP_RS_RA_UI, 24<<26, "ori",
0, OP_RS_RA_UI, 25<<26, "oris",
0, OP_RS_RA_UI, 26<<26, "xori",
0, OP_RS_RA_UI, 27<<26, "xoris",
0, OP_RS_RA_RB_C, 31<<26 | 28<<1, "and",
0, OP_RS_RA_RB_C, 31<<26 | 444<<1, "or",
0, OP_RS_RA_RB_C, 31<<26 | 316<<1, "xor",
0, OP_RS_RA_RB_C, 31<<26 | 476<<1, "nand",
0, OP_RS_RA_RB_C, 31<<26 | 124<<1, "nor",
0, OP_RS_RA_RB_C, 31<<26 | 284<<1, "eqv",
0, OP_RS_RA_RB_C, 31<<26 | 60<<1, "andc",
0, OP_RS_RA_RB_C, 31<<26 | 412<<1, "orc",
0, OP_RS_RA_C, 31<<26 | 954<<1, "extsb",
0, OP_RS_RA_C, 31<<26 | 922<<1, "extsh",
0, OP_RS_RA_C, 31<<26 | 986<<1, "extsw",
0, OP_RS_RA_C, 31<<26 | 58<<1, "cntlzd",
0, OP_RS_RA_C, 31<<26 | 26<<1, "cntlzw",
/* page 69 */
0, OP_RS_RA_SH_MB6_SH_C, 30<<26 | 0<<2, "rldicl",
0, OP_RS_RA_SH_ME6_SH_C, 30<<26 | 1<<2, "rldicr",
0, OP_RS_RA_SH_MB6_SH_C, 30<<26 | 2<<2, "rldic",
0, OP_RS_RA_SH_MB5_ME5_C, 21<<26, "rlwinm",
0, OP_RS_RA_RB_MB6_C, 30<<26 | 8<<1, "rldcl",
0, OP_RS_RA_RB_ME6_C, 30<<26 | 9<<1, "rldcr",
0, OP_RS_RA_RB_MB5_ME5_C, 23<<26, "rlwnm",
0, OP_RS_RA_SH_MB6_SH_C, 30<<26 | 3<<2, "rldimi",
0, OP_RS_RA_SH_MB5_ME5_C, 20<<26, "rlwimi",
/* page 74 */
0, OP_RS_RA_RB_C, 31<<26 | 27<<1, "sld",
0, OP_RS_RA_RB_C, 31<<26 | 24<<1, "slw",
0, OP_RS_RA_RB_C, 31<<26 | 539<<1, "srd",
0, OP_RS_RA_RB_C, 31<<26 | 536<<1, "srw",
0, OP_RS_RA_SH6_C, 31<<26 | 413<<2, "sradi",
0, OP_RS_RA_SH5_C, 31<<26 | 824<<1, "srawi",
0, OP_RS_RA_RB_C, 31<<26 | 794<<1, "srad",
0, OP_RS_RA_RB_C, 31<<26 | 792<<1, "sraw",
/* page 78 */
0, OP_RS_SPR, 31<<26 | 467<<1, "mtspr",
0, OP_RT_SPR, 31<<26 | 339<<1, "mfspr",
0, OP_RS_FXM, 31<<26 | 0<<21 | 144<<1, "mtcrf",
0, OP_RT, 31<<26 | 0<<21 | 19<<1, "mfcr",
/* Floating point instructions (page 83) */
0, OP_FRT_RA_D, 48<<26, "lfs",
0, OP_FRT_RA_RB, 31<<26 | 535<<1, "lfsx",
0, OP_FRT_RA_D, 49<<26, "lfsu",
0, OP_FRT_RA_RB, 31<<26 | 567<<1, "lfsux",
0, OP_FRT_RA_D, 50<<26, "lfd",
0, OP_FRT_RA_RB, 31<<26 | 599<<1, "lfdx",
0, OP_FRT_RA_D, 51<<26, "lfdu",
0, OP_FRT_RA_RB, 31<<26 | 631<<1, "lfdux",
0, OP_FRS_RA_D, 52<<26, "stfs",
0, OP_FRS_RA_RB, 31<<26 | 663<<1, "stfsx",
0, OP_FRS_RA_D, 53<<26, "stfsu",
0, OP_FRS_RA_RB, 31<<26 | 695<<1, "stfsux",
0, OP_FRS_RA_D, 54<<26, "stfd",
0, OP_FRS_RA_RB, 31<<26 | 727<<1, "stfdx",
0, OP_FRS_RA_D, 55<<26, "stfdu",
0, OP_FRS_RA_RB, 31<<26 | 759<<1, "stfdux",
0, OP_FRS_RA_RB, 31<<26 | 983<<1, "stfiwx",
0, OP_FRT_FRB_C, 63<<26 | 72<<1, "fmr",
0, OP_FRT_FRB_C, 63<<26 | 40<<1, "fneg",
0, OP_FRT_FRB_C, 63<<26 | 264<<1, "fabs",
0, OP_FRT_FRB_C, 63<<26 | 136<<1, "fnabs",
0, OP_FRT_FRA_FRB_C, 63<<26 | 21<<1, "fadd",
0, OP_FRT_FRA_FRB_C, 59<<26 | 21<<1, "fadds",
0, OP_FRT_FRA_FRB_C, 63<<26 | 20<<1, "fsub",
0, OP_FRT_FRA_FRB_C, 59<<26 | 20<<1, "fsubs",
0, OP_FRT_FRA_FRC_C, 63<<26 | 25<<1, "fmul",
0, OP_FRT_FRA_FRC_C, 59<<26 | 25<<1, "fmuls",
0, OP_FRT_FRA_FRB_C, 63<<26 | 18<<1, "fdiv",
0, OP_FRT_FRA_FRB_C, 59<<26 | 18<<1, "fdivs",
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 29<<1, "fmadd",
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 29<<1, "fmadds",
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 28<<1, "fmsub",
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 28<<1, "fmsubs",
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 31<<1, "fnmadd",
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 31<<1, "fnmadds",
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 30<<1, "fnmsub",
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 30<<1, "fnmsubs",
0, OP_FRT_FRB_C, 63<<26 | 12<<1, "frsp",
0, OP_FRT_FRB_C, 63<<26 | 814<<1, "fctid",
0, OP_FRT_FRB_C, 63<<26 | 815<<1, "fctidz",
0, OP_FRT_FRB_C, 63<<26 | 14<<1, "fctiw",
0, OP_FRT_FRB_C, 63<<26 | 15<<1, "fctiwz",
0, OP_FRT_FRB_C, 63<<26 | 846<<1, "fcfid",
0, OP_BF_FRA_FRB, 63<<26 | 0<<1, "fcmpu",
0, OP_BF_FRA_FRB, 63<<26 | 32<<1, "fcmpo",
0, OP_FRT_C, 63<<26 | 583<<1, "mffs",
0, OP_BF_BFA, 63<<26 | 64<<1, "mcrfs",
0, OP_BF_U_C, 63<<26 | 134<<1, "mtfsfi",
0, OP_FLM_FRB_C, 63<<26 | 711<<1, "mtfsf",
0, OP_BT_C, 63<<26 | 70<<1, "mtfsb0",
0, OP_BT_C, 63<<26 | 38<<1, "mtfsb1",
0, OP_FRT_FRB_C, 63<<26 | 22<<1, "fsqrt",
0, OP_FRT_FRB_C, 59<<26 | 22<<1, "fsqrts",
0, OP_FRT_FRB_C, 59<<26 | 24<<1, "fres",
0, OP_FRT_FRB_C, 63<<26 | 26<<1, "frsqrte",
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 23<<1, "fsel",
/* page 98 */
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