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Make inn work; fix broken 64-bit loads and stores.

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This commit is contained in:
David Given 2018-09-14 13:48:43 +02:00
parent 5d0876a30b
commit 08b1e8d71b
2 changed files with 12 additions and 13 deletions
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17
mach/mips/libem/inn.s
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@ -13,21 +13,20 @@
.define .inn
.inn:
lw r4, 0(sp) ! r4 = size of set (bytes)
lw r5, 0(sp) ! r5 = bit number
addiu sp, sp, 8 ! sp now points at bitset
lw r5, 4(sp) ! r5 = bit number
addiu sp, sp, 4 ! sp now points to word below bitset
srl r6, r5, 3 ! r6 = offset of word in set
andi r6, r5, ~31 ! r6 = bit offset of base of word in set
srl r6, r6, 3 ! r6 = byte offset of base of word in set
addu r6, sp, r6 ! r6 = address of word in set
lw r6, 0(r6) ! r6 = word
lw r6, 4(r6) ! r6 = word (remember stack offset)
ext r7, r5, 0, 3 ! r7 = bit number within word
andi r7, r5, 31 ! r7 = bit number within word
srlv r6, r6, r7 ! r7 = candidate bit now at bit 0
andi r6, r6, 1 ! r7 = bool
addu sp, sp, r4 ! retract over bitfield
addiu sp, sp, -4
sw r6, 0(sp) ! push result
addu sp, sp, r4 ! retract over bitfield (remember stack offset)
sw r6, 0(sp) ! store result
jr ra
nop

8
mach/mips/mcg/table
View file

@ -233,8 +233,8 @@ PATTERNS
/* Stores */
STORE.L(addr:address, value:(long)reg)
emit "sw %value.0, 4+%addr"
emit "sw %value.1, 0+%addr"
emit "sw %value.0, 0+%addr"
emit "sw %value.1, 4+%addr"
cost 8;
STORE.I(addr:address, value:(int)reg)
@ -267,8 +267,8 @@ PATTERNS
* a register, resulting in %addr being corrupted before %out.1 is
* loaded. */
out:(long)reg = LOAD.L(addr:address)
emit "lw at, 4+%addr"
emit "lw %out.1, 0+%addr"
emit "lw at, 0+%addr"
emit "lw %out.1, 4+%addr"
emit "mov %out.0, at"
cost 12;