several improvements + fixes
This commit is contained in:
eck
parent
2a26b4d335
commit
0bf7d60080
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@ -1151,6 +1151,11 @@ from regAregXcon %bd==0 && %sc==1
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uses reusing %1, AA_REG = %1.reg
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gen add_l {dreg4,%1.xreg},%a
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yields %a
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from regAregXcon %sc==1
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uses reusing %1, AA_REG = %1.reg
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gen add_l {dreg4, %1.xreg}, %a
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yields {regAcon, %a, %1.bd}
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#endif
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#if WORD_SIZE==2
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@ -2841,9 +2846,11 @@ pat ste loe $1==$2 leaving dup WORD_SIZE ste $1
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pat lil inreg($1)==reg_pointer
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kills pre_post %reg==regvar($1, reg_pointer)
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yields {indirect_int, regvar($1, reg_pointer)}
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#if WORD_SIZE==4
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pat lil inreg($1)==reg_any
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uses AA_REG = {DLOCAL, $1}
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yields {indirect_int, %a}
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#endif
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pat lil
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#if TBL68020
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@ -3045,6 +3052,16 @@ with exact ext_regX yields {abs_index4, %1.sc, %1.xreg, %1.bd}
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#endif /* FANCY_MODES */
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#endif /* TBL68020 */
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#if WORD_SIZE==2
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pat loi $1==6
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with AA_REG
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yields {offsetted2, %1, 4} {indirect4, %1}
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with exact local_addr
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yields {offsetted2, lb, %1.bd+4} {offsetted4, lb, %1.bd}
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with exact ext_addr
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yields {absolute2, %1.bd + 4} {absolute4, %1.bd}
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#endif
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pat loi $1==8
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#if WORD_SIZE!=2
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leaving ldf 0
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@ -3057,6 +3074,7 @@ with exact ext_addr
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yields {absolute4, %1.bd + 4} {absolute4, %1.bd}
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#endif
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#if WORD_SIZE==4
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pat loi $1==3*WORD_SIZE
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with AA_REG STACK
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kills ALL
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@ -3066,8 +3084,6 @@ with AA_REG STACK
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move_i {pre_dec_int, %1},{pre_dec_int, sp}
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move_i {pre_dec_int, %1},{pre_dec_int, sp}
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/* ??? */
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#if WORD_SIZE==4
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pat loi $1==4*WORD_SIZE
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with AA_REG STACK
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kills ALL
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@ -3190,6 +3206,7 @@ with exact STACK
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kills allexceptcon
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gen move_i {post_inc_int, sp}, {indirect_int, regvar($1, reg_pointer)}
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#if WORD_SIZE==4
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pat sil inreg($1)==reg_any
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with store_int-sconsts
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kills allexceptcon
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@ -3199,6 +3216,7 @@ with exact STACK
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kills allexceptcon
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uses AA_REG = {DLOCAL, $1}
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gen move_i {post_inc_int, sp}, {indirect_int, %a}
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#endif
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pat sil
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#if TBL68020
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@ -3238,10 +3256,12 @@ with exact local_addr store_int
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with exact ext_addr store_int
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kills allexceptcon
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gen move %2, {absolute_int, %1.bd+$1}
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#ifndef TBL68020
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#if TBL68000
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#if WORD_SIZE==4
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with regAcon store_int
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kills allexceptcon
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gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
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#endif
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#else TBL68020
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with exact regAcon store_int
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kills allexceptcon
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@ -3509,6 +3529,26 @@ with exact ext_regX store4
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#endif /* FANCY_MODES */
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#endif TBL68020
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#if WORD_SIZE==2
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pat sti $1==6
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with A_REG any4 any2
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kills ALL
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gen move %2, {indirect4, %1}
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move %3, {offsetted2, %1, 4}
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with AA_REG any4 any2
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kills ALL
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gen move %2, {post_inc4, %1}
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move %3, {post_inc2, %1}
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with exact A_REG STACK
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kills ALL
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gen move_l {post_inc4, sp}, {indirect4, %1}
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move_w {post_inc2, sp}, {offsetted2, %1, 4}
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with exact AA_REG STACK
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kills ALL
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gen move_l {post_inc4, sp}, {post_inc4, %1}
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move_w {post_inc2, sp}, {post_inc2, %1}
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#endif
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pat sti $1==8
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#if WORD_SIZE!=2
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leaving sdf 0
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@ -3527,6 +3567,8 @@ with exact ext_addr any4-pre_post any4-pre_post
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move_l %3,{absolute4, %1.bd+4}
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#endif
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#if WORD_SIZE==4
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pat sti $1==3*WORD_SIZE
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with AA_REG STACK
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kills ALL
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@ -3534,8 +3576,6 @@ pat sti $1==3*WORD_SIZE
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move_i {post_inc_int, sp},{post_inc_int,%1}
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move_i {post_inc_int, sp},{post_inc_int,%1}
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/* ??? */
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#if WORD_SIZE==4
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pat sti $1==4*WORD_SIZE
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with AA_REG STACK
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kills ALL
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@ -3713,7 +3753,7 @@ with STACK
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kills ALL
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gen jsr {absolute4, ".mli"}
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yields dl1
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#endif TBL68020
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#endif
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#if WORD_SIZE==2
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pat dvi $1==2
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@ -3756,7 +3796,7 @@ with data4-sconsts4 DD_REG4
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with STACK
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kills ALL
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gen jsr {absolute4, ".dvi"}
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yields dl0
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yields dl2
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#endif TBL68020
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#if WORD_SIZE==2
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@ -4304,6 +4344,18 @@ with D_REG4 yields {regX, 4, %1}
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pat loc sli ads $1==3 && $2==4 && $3==4
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with D_REG4 yields {regX, 8, %1}
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leaving ads 4
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#else
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pat loc sli $1==1 && $2==WORD_SIZE
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with DD_REG
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gen add_i %1, %1 yields %1
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#if WORD_SIZE==2
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pat loc sli $1==1 && $2==4
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with DD_REG4
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gen add_l %1, %1 yields %1
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#endif
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#endif TBL68020
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@ -4420,9 +4472,9 @@ pat loc loc ciu $1==2 && $2==4
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with zero_const
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yields {zero_const4, 0}
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with any
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uses reusing %1, DD_REG4
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uses DD_REG4 = {zero_const4, 0}
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gen move %1,%a.1
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ext_l %a yields %a
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yields %a
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pat loc loc ciu $1==4 && $2==2
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with zero_const4
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@ -5380,11 +5432,11 @@ pat lfr $1==8 yields d1 d0
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pat ret $1==0
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gen return
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pat asp ret $1==0
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pat asp ret $2==0
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gen return
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#if WORD_SIZE==2
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pat ret $1 ==2
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pat ret $1==2
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with any2
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gen move %1, d0
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return
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@ -5539,7 +5591,6 @@ with DD_REG4 AA_REG AA_REG
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bne {slabel, 1b}
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2:
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/* ??? interface */
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#if WORD_SIZE==2
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pat csa $1==2
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#if TBL68020
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@ -5665,7 +5716,7 @@ with STACK
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pat exg !defined($1)
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with any_int STACK
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kills ALL
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gen move_i %1, d0
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gen move %1, d0
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jsr {absolute4, ".exg"}
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pat fil
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@ -5708,10 +5759,11 @@ with STACK
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kills ALL
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gen jsr {absolute4, ".mon"}
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/* used by the ANSI-compiler to indicate volatile */
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pat nop
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with STACK
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kills ALL
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gen jsr {absolute4, ".nop"} /* */
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/* gen jsr {absolute4, ".nop"} */
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#if WORD_SIZE==2
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#ifdef TBL68020
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@ -1151,6 +1151,11 @@ from regAregXcon %bd==0 && %sc==1
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uses reusing %1, AA_REG = %1.reg
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gen add_l {dreg4,%1.xreg},%a
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yields %a
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from regAregXcon %sc==1
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uses reusing %1, AA_REG = %1.reg
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gen add_l {dreg4, %1.xreg}, %a
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yields {regAcon, %a, %1.bd}
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#endif
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#if WORD_SIZE==2
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@ -2841,9 +2846,11 @@ pat ste loe $1==$2 leaving dup WORD_SIZE ste $1
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pat lil inreg($1)==reg_pointer
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kills pre_post %reg==regvar($1, reg_pointer)
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yields {indirect_int, regvar($1, reg_pointer)}
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#if WORD_SIZE==4
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pat lil inreg($1)==reg_any
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uses AA_REG = {DLOCAL, $1}
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yields {indirect_int, %a}
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#endif
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pat lil
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#if TBL68020
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@ -3045,6 +3052,16 @@ with exact ext_regX yields {abs_index4, %1.sc, %1.xreg, %1.bd}
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#endif /* FANCY_MODES */
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#endif /* TBL68020 */
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#if WORD_SIZE==2
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pat loi $1==6
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with AA_REG
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yields {offsetted2, %1, 4} {indirect4, %1}
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with exact local_addr
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yields {offsetted2, lb, %1.bd+4} {offsetted4, lb, %1.bd}
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with exact ext_addr
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yields {absolute2, %1.bd + 4} {absolute4, %1.bd}
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#endif
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pat loi $1==8
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#if WORD_SIZE!=2
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leaving ldf 0
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@ -3057,6 +3074,7 @@ with exact ext_addr
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yields {absolute4, %1.bd + 4} {absolute4, %1.bd}
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#endif
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#if WORD_SIZE==4
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pat loi $1==3*WORD_SIZE
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with AA_REG STACK
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kills ALL
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@ -3066,8 +3084,6 @@ with AA_REG STACK
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move_i {pre_dec_int, %1},{pre_dec_int, sp}
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move_i {pre_dec_int, %1},{pre_dec_int, sp}
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/* ??? */
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#if WORD_SIZE==4
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pat loi $1==4*WORD_SIZE
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with AA_REG STACK
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kills ALL
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@ -3190,6 +3206,7 @@ with exact STACK
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kills allexceptcon
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gen move_i {post_inc_int, sp}, {indirect_int, regvar($1, reg_pointer)}
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#if WORD_SIZE==4
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pat sil inreg($1)==reg_any
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with store_int-sconsts
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kills allexceptcon
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@ -3199,6 +3216,7 @@ with exact STACK
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kills allexceptcon
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uses AA_REG = {DLOCAL, $1}
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gen move_i {post_inc_int, sp}, {indirect_int, %a}
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#endif
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pat sil
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#if TBL68020
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@ -3238,10 +3256,12 @@ with exact local_addr store_int
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with exact ext_addr store_int
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kills allexceptcon
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gen move %2, {absolute_int, %1.bd+$1}
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#ifndef TBL68020
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#if TBL68000
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#if WORD_SIZE==4
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with regAcon store_int
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kills allexceptcon
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gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
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#endif
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#else TBL68020
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with exact regAcon store_int
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kills allexceptcon
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@ -3509,6 +3529,26 @@ with exact ext_regX store4
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#endif /* FANCY_MODES */
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#endif TBL68020
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#if WORD_SIZE==2
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pat sti $1==6
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with A_REG any4 any2
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kills ALL
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gen move %2, {indirect4, %1}
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move %3, {offsetted2, %1, 4}
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with AA_REG any4 any2
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kills ALL
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gen move %2, {post_inc4, %1}
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move %3, {post_inc2, %1}
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with exact A_REG STACK
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kills ALL
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gen move_l {post_inc4, sp}, {indirect4, %1}
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move_w {post_inc2, sp}, {offsetted2, %1, 4}
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with exact AA_REG STACK
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kills ALL
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gen move_l {post_inc4, sp}, {post_inc4, %1}
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move_w {post_inc2, sp}, {post_inc2, %1}
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#endif
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pat sti $1==8
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#if WORD_SIZE!=2
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leaving sdf 0
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@ -3527,6 +3567,8 @@ with exact ext_addr any4-pre_post any4-pre_post
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move_l %3,{absolute4, %1.bd+4}
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#endif
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#if WORD_SIZE==4
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pat sti $1==3*WORD_SIZE
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with AA_REG STACK
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kills ALL
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@ -3534,8 +3576,6 @@ pat sti $1==3*WORD_SIZE
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move_i {post_inc_int, sp},{post_inc_int,%1}
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move_i {post_inc_int, sp},{post_inc_int,%1}
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/* ??? */
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#if WORD_SIZE==4
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pat sti $1==4*WORD_SIZE
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with AA_REG STACK
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kills ALL
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@ -3713,7 +3753,7 @@ with STACK
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kills ALL
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gen jsr {absolute4, ".mli"}
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yields dl1
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#endif TBL68020
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#endif
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#if WORD_SIZE==2
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pat dvi $1==2
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@ -3756,7 +3796,7 @@ with data4-sconsts4 DD_REG4
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with STACK
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kills ALL
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gen jsr {absolute4, ".dvi"}
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yields dl0
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yields dl2
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#endif TBL68020
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#if WORD_SIZE==2
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@ -4304,6 +4344,18 @@ with D_REG4 yields {regX, 4, %1}
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pat loc sli ads $1==3 && $2==4 && $3==4
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with D_REG4 yields {regX, 8, %1}
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leaving ads 4
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#else
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pat loc sli $1==1 && $2==WORD_SIZE
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with DD_REG
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gen add_i %1, %1 yields %1
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#if WORD_SIZE==2
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pat loc sli $1==1 && $2==4
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with DD_REG4
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gen add_l %1, %1 yields %1
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#endif
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#endif TBL68020
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@ -4420,9 +4472,9 @@ pat loc loc ciu $1==2 && $2==4
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with zero_const
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yields {zero_const4, 0}
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with any
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uses reusing %1, DD_REG4
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uses DD_REG4 = {zero_const4, 0}
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gen move %1,%a.1
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ext_l %a yields %a
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yields %a
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pat loc loc ciu $1==4 && $2==2
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with zero_const4
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@ -5380,11 +5432,11 @@ pat lfr $1==8 yields d1 d0
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pat ret $1==0
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gen return
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pat asp ret $1==0
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pat asp ret $2==0
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gen return
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#if WORD_SIZE==2
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pat ret $1 ==2
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pat ret $1==2
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with any2
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gen move %1, d0
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return
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@ -5539,7 +5591,6 @@ with DD_REG4 AA_REG AA_REG
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bne {slabel, 1b}
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2:
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/* ??? interface */
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#if WORD_SIZE==2
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pat csa $1==2
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#if TBL68020
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@ -5665,7 +5716,7 @@ with STACK
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pat exg !defined($1)
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with any_int STACK
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kills ALL
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gen move_i %1, d0
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gen move %1, d0
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jsr {absolute4, ".exg"}
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pat fil
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@ -5708,10 +5759,11 @@ with STACK
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kills ALL
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gen jsr {absolute4, ".mon"}
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/* used by the ANSI-compiler to indicate volatile */
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pat nop
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with STACK
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kills ALL
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gen jsr {absolute4, ".nop"} /* */
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/* gen jsr {absolute4, ".nop"} */
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#if WORD_SIZE==2
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#ifdef TBL68020
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@ -1151,6 +1151,11 @@ from regAregXcon %bd==0 && %sc==1
|
|||
uses reusing %1, AA_REG = %1.reg
|
||||
gen add_l {dreg4,%1.xreg},%a
|
||||
yields %a
|
||||
|
||||
from regAregXcon %sc==1
|
||||
uses reusing %1, AA_REG = %1.reg
|
||||
gen add_l {dreg4, %1.xreg}, %a
|
||||
yields {regAcon, %a, %1.bd}
|
||||
#endif
|
||||
|
||||
#if WORD_SIZE==2
|
||||
|
|
@ -2841,9 +2846,11 @@ pat ste loe $1==$2 leaving dup WORD_SIZE ste $1
|
|||
pat lil inreg($1)==reg_pointer
|
||||
kills pre_post %reg==regvar($1, reg_pointer)
|
||||
yields {indirect_int, regvar($1, reg_pointer)}
|
||||
#if WORD_SIZE==4
|
||||
pat lil inreg($1)==reg_any
|
||||
uses AA_REG = {DLOCAL, $1}
|
||||
yields {indirect_int, %a}
|
||||
#endif
|
||||
|
||||
pat lil
|
||||
#if TBL68020
|
||||
|
|
@ -3045,6 +3052,16 @@ with exact ext_regX yields {abs_index4, %1.sc, %1.xreg, %1.bd}
|
|||
#endif /* FANCY_MODES */
|
||||
#endif /* TBL68020 */
|
||||
|
||||
#if WORD_SIZE==2
|
||||
pat loi $1==6
|
||||
with AA_REG
|
||||
yields {offsetted2, %1, 4} {indirect4, %1}
|
||||
with exact local_addr
|
||||
yields {offsetted2, lb, %1.bd+4} {offsetted4, lb, %1.bd}
|
||||
with exact ext_addr
|
||||
yields {absolute2, %1.bd + 4} {absolute4, %1.bd}
|
||||
#endif
|
||||
|
||||
pat loi $1==8
|
||||
#if WORD_SIZE!=2
|
||||
leaving ldf 0
|
||||
|
|
@ -3057,6 +3074,7 @@ with exact ext_addr
|
|||
yields {absolute4, %1.bd + 4} {absolute4, %1.bd}
|
||||
#endif
|
||||
|
||||
#if WORD_SIZE==4
|
||||
pat loi $1==3*WORD_SIZE
|
||||
with AA_REG STACK
|
||||
kills ALL
|
||||
|
|
@ -3066,8 +3084,6 @@ with AA_REG STACK
|
|||
move_i {pre_dec_int, %1},{pre_dec_int, sp}
|
||||
move_i {pre_dec_int, %1},{pre_dec_int, sp}
|
||||
|
||||
/* ??? */
|
||||
#if WORD_SIZE==4
|
||||
pat loi $1==4*WORD_SIZE
|
||||
with AA_REG STACK
|
||||
kills ALL
|
||||
|
|
@ -3190,6 +3206,7 @@ with exact STACK
|
|||
kills allexceptcon
|
||||
gen move_i {post_inc_int, sp}, {indirect_int, regvar($1, reg_pointer)}
|
||||
|
||||
#if WORD_SIZE==4
|
||||
pat sil inreg($1)==reg_any
|
||||
with store_int-sconsts
|
||||
kills allexceptcon
|
||||
|
|
@ -3199,6 +3216,7 @@ with exact STACK
|
|||
kills allexceptcon
|
||||
uses AA_REG = {DLOCAL, $1}
|
||||
gen move_i {post_inc_int, sp}, {indirect_int, %a}
|
||||
#endif
|
||||
|
||||
pat sil
|
||||
#if TBL68020
|
||||
|
|
@ -3238,10 +3256,12 @@ with exact local_addr store_int
|
|||
with exact ext_addr store_int
|
||||
kills allexceptcon
|
||||
gen move %2, {absolute_int, %1.bd+$1}
|
||||
#ifndef TBL68020
|
||||
#if TBL68000
|
||||
#if WORD_SIZE==4
|
||||
with regAcon store_int
|
||||
kills allexceptcon
|
||||
gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
|
||||
#endif
|
||||
#else TBL68020
|
||||
with exact regAcon store_int
|
||||
kills allexceptcon
|
||||
|
|
@ -3509,6 +3529,26 @@ with exact ext_regX store4
|
|||
#endif /* FANCY_MODES */
|
||||
#endif TBL68020
|
||||
|
||||
#if WORD_SIZE==2
|
||||
pat sti $1==6
|
||||
with A_REG any4 any2
|
||||
kills ALL
|
||||
gen move %2, {indirect4, %1}
|
||||
move %3, {offsetted2, %1, 4}
|
||||
with AA_REG any4 any2
|
||||
kills ALL
|
||||
gen move %2, {post_inc4, %1}
|
||||
move %3, {post_inc2, %1}
|
||||
with exact A_REG STACK
|
||||
kills ALL
|
||||
gen move_l {post_inc4, sp}, {indirect4, %1}
|
||||
move_w {post_inc2, sp}, {offsetted2, %1, 4}
|
||||
with exact AA_REG STACK
|
||||
kills ALL
|
||||
gen move_l {post_inc4, sp}, {post_inc4, %1}
|
||||
move_w {post_inc2, sp}, {post_inc2, %1}
|
||||
#endif
|
||||
|
||||
pat sti $1==8
|
||||
#if WORD_SIZE!=2
|
||||
leaving sdf 0
|
||||
|
|
@ -3527,6 +3567,8 @@ with exact ext_addr any4-pre_post any4-pre_post
|
|||
move_l %3,{absolute4, %1.bd+4}
|
||||
#endif
|
||||
|
||||
|
||||
#if WORD_SIZE==4
|
||||
pat sti $1==3*WORD_SIZE
|
||||
with AA_REG STACK
|
||||
kills ALL
|
||||
|
|
@ -3534,8 +3576,6 @@ pat sti $1==3*WORD_SIZE
|
|||
move_i {post_inc_int, sp},{post_inc_int,%1}
|
||||
move_i {post_inc_int, sp},{post_inc_int,%1}
|
||||
|
||||
/* ??? */
|
||||
#if WORD_SIZE==4
|
||||
pat sti $1==4*WORD_SIZE
|
||||
with AA_REG STACK
|
||||
kills ALL
|
||||
|
|
@ -3713,7 +3753,7 @@ with STACK
|
|||
kills ALL
|
||||
gen jsr {absolute4, ".mli"}
|
||||
yields dl1
|
||||
#endif TBL68020
|
||||
#endif
|
||||
|
||||
#if WORD_SIZE==2
|
||||
pat dvi $1==2
|
||||
|
|
@ -3756,7 +3796,7 @@ with data4-sconsts4 DD_REG4
|
|||
with STACK
|
||||
kills ALL
|
||||
gen jsr {absolute4, ".dvi"}
|
||||
yields dl0
|
||||
yields dl2
|
||||
#endif TBL68020
|
||||
|
||||
#if WORD_SIZE==2
|
||||
|
|
@ -4304,6 +4344,18 @@ with D_REG4 yields {regX, 4, %1}
|
|||
pat loc sli ads $1==3 && $2==4 && $3==4
|
||||
with D_REG4 yields {regX, 8, %1}
|
||||
leaving ads 4
|
||||
#else
|
||||
|
||||
pat loc sli $1==1 && $2==WORD_SIZE
|
||||
with DD_REG
|
||||
gen add_i %1, %1 yields %1
|
||||
|
||||
#if WORD_SIZE==2
|
||||
pat loc sli $1==1 && $2==4
|
||||
with DD_REG4
|
||||
gen add_l %1, %1 yields %1
|
||||
#endif
|
||||
|
||||
#endif TBL68020
|
||||
|
||||
|
||||
|
|
@ -4420,9 +4472,9 @@ pat loc loc ciu $1==2 && $2==4
|
|||
with zero_const
|
||||
yields {zero_const4, 0}
|
||||
with any
|
||||
uses reusing %1, DD_REG4
|
||||
uses DD_REG4 = {zero_const4, 0}
|
||||
gen move %1,%a.1
|
||||
ext_l %a yields %a
|
||||
yields %a
|
||||
|
||||
pat loc loc ciu $1==4 && $2==2
|
||||
with zero_const4
|
||||
|
|
@ -5380,11 +5432,11 @@ pat lfr $1==8 yields d1 d0
|
|||
pat ret $1==0
|
||||
gen return
|
||||
|
||||
pat asp ret $1==0
|
||||
pat asp ret $2==0
|
||||
gen return
|
||||
|
||||
#if WORD_SIZE==2
|
||||
pat ret $1 ==2
|
||||
pat ret $1==2
|
||||
with any2
|
||||
gen move %1, d0
|
||||
return
|
||||
|
|
@ -5539,7 +5591,6 @@ with DD_REG4 AA_REG AA_REG
|
|||
bne {slabel, 1b}
|
||||
2:
|
||||
|
||||
/* ??? interface */
|
||||
#if WORD_SIZE==2
|
||||
pat csa $1==2
|
||||
#if TBL68020
|
||||
|
|
@ -5665,7 +5716,7 @@ with STACK
|
|||
pat exg !defined($1)
|
||||
with any_int STACK
|
||||
kills ALL
|
||||
gen move_i %1, d0
|
||||
gen move %1, d0
|
||||
jsr {absolute4, ".exg"}
|
||||
|
||||
pat fil
|
||||
|
|
@ -5708,10 +5759,11 @@ with STACK
|
|||
kills ALL
|
||||
gen jsr {absolute4, ".mon"}
|
||||
|
||||
/* used by the ANSI-compiler to indicate volatile */
|
||||
pat nop
|
||||
with STACK
|
||||
kills ALL
|
||||
gen jsr {absolute4, ".nop"} /* */
|
||||
/* gen jsr {absolute4, ".nop"} */
|
||||
|
||||
#if WORD_SIZE==2
|
||||
#ifdef TBL68020
|
||||
|
|
|
|||
|
|
@ -1151,6 +1151,11 @@ from regAregXcon %bd==0 && %sc==1
|
|||
uses reusing %1, AA_REG = %1.reg
|
||||
gen add_l {dreg4,%1.xreg},%a
|
||||
yields %a
|
||||
|
||||
from regAregXcon %sc==1
|
||||
uses reusing %1, AA_REG = %1.reg
|
||||
gen add_l {dreg4, %1.xreg}, %a
|
||||
yields {regAcon, %a, %1.bd}
|
||||
#endif
|
||||
|
||||
#if WORD_SIZE==2
|
||||
|
|
@ -2841,9 +2846,11 @@ pat ste loe $1==$2 leaving dup WORD_SIZE ste $1
|
|||
pat lil inreg($1)==reg_pointer
|
||||
kills pre_post %reg==regvar($1, reg_pointer)
|
||||
yields {indirect_int, regvar($1, reg_pointer)}
|
||||
#if WORD_SIZE==4
|
||||
pat lil inreg($1)==reg_any
|
||||
uses AA_REG = {DLOCAL, $1}
|
||||
yields {indirect_int, %a}
|
||||
#endif
|
||||
|
||||
pat lil
|
||||
#if TBL68020
|
||||
|
|
@ -3045,6 +3052,16 @@ with exact ext_regX yields {abs_index4, %1.sc, %1.xreg, %1.bd}
|
|||
#endif /* FANCY_MODES */
|
||||
#endif /* TBL68020 */
|
||||
|
||||
#if WORD_SIZE==2
|
||||
pat loi $1==6
|
||||
with AA_REG
|
||||
yields {offsetted2, %1, 4} {indirect4, %1}
|
||||
with exact local_addr
|
||||
yields {offsetted2, lb, %1.bd+4} {offsetted4, lb, %1.bd}
|
||||
with exact ext_addr
|
||||
yields {absolute2, %1.bd + 4} {absolute4, %1.bd}
|
||||
#endif
|
||||
|
||||
pat loi $1==8
|
||||
#if WORD_SIZE!=2
|
||||
leaving ldf 0
|
||||
|
|
@ -3057,6 +3074,7 @@ with exact ext_addr
|
|||
yields {absolute4, %1.bd + 4} {absolute4, %1.bd}
|
||||
#endif
|
||||
|
||||
#if WORD_SIZE==4
|
||||
pat loi $1==3*WORD_SIZE
|
||||
with AA_REG STACK
|
||||
kills ALL
|
||||
|
|
@ -3066,8 +3084,6 @@ with AA_REG STACK
|
|||
move_i {pre_dec_int, %1},{pre_dec_int, sp}
|
||||
move_i {pre_dec_int, %1},{pre_dec_int, sp}
|
||||
|
||||
/* ??? */
|
||||
#if WORD_SIZE==4
|
||||
pat loi $1==4*WORD_SIZE
|
||||
with AA_REG STACK
|
||||
kills ALL
|
||||
|
|
@ -3190,6 +3206,7 @@ with exact STACK
|
|||
kills allexceptcon
|
||||
gen move_i {post_inc_int, sp}, {indirect_int, regvar($1, reg_pointer)}
|
||||
|
||||
#if WORD_SIZE==4
|
||||
pat sil inreg($1)==reg_any
|
||||
with store_int-sconsts
|
||||
kills allexceptcon
|
||||
|
|
@ -3199,6 +3216,7 @@ with exact STACK
|
|||
kills allexceptcon
|
||||
uses AA_REG = {DLOCAL, $1}
|
||||
gen move_i {post_inc_int, sp}, {indirect_int, %a}
|
||||
#endif
|
||||
|
||||
pat sil
|
||||
#if TBL68020
|
||||
|
|
@ -3238,10 +3256,12 @@ with exact local_addr store_int
|
|||
with exact ext_addr store_int
|
||||
kills allexceptcon
|
||||
gen move %2, {absolute_int, %1.bd+$1}
|
||||
#ifndef TBL68020
|
||||
#if TBL68000
|
||||
#if WORD_SIZE==4
|
||||
with regAcon store_int
|
||||
kills allexceptcon
|
||||
gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
|
||||
#endif
|
||||
#else TBL68020
|
||||
with exact regAcon store_int
|
||||
kills allexceptcon
|
||||
|
|
@ -3509,6 +3529,26 @@ with exact ext_regX store4
|
|||
#endif /* FANCY_MODES */
|
||||
#endif TBL68020
|
||||
|
||||
#if WORD_SIZE==2
|
||||
pat sti $1==6
|
||||
with A_REG any4 any2
|
||||
kills ALL
|
||||
gen move %2, {indirect4, %1}
|
||||
move %3, {offsetted2, %1, 4}
|
||||
with AA_REG any4 any2
|
||||
kills ALL
|
||||
gen move %2, {post_inc4, %1}
|
||||
move %3, {post_inc2, %1}
|
||||
with exact A_REG STACK
|
||||
kills ALL
|
||||
gen move_l {post_inc4, sp}, {indirect4, %1}
|
||||
move_w {post_inc2, sp}, {offsetted2, %1, 4}
|
||||
with exact AA_REG STACK
|
||||
kills ALL
|
||||
gen move_l {post_inc4, sp}, {post_inc4, %1}
|
||||
move_w {post_inc2, sp}, {post_inc2, %1}
|
||||
#endif
|
||||
|
||||
pat sti $1==8
|
||||
#if WORD_SIZE!=2
|
||||
leaving sdf 0
|
||||
|
|
@ -3527,6 +3567,8 @@ with exact ext_addr any4-pre_post any4-pre_post
|
|||
move_l %3,{absolute4, %1.bd+4}
|
||||
#endif
|
||||
|
||||
|
||||
#if WORD_SIZE==4
|
||||
pat sti $1==3*WORD_SIZE
|
||||
with AA_REG STACK
|
||||
kills ALL
|
||||
|
|
@ -3534,8 +3576,6 @@ pat sti $1==3*WORD_SIZE
|
|||
move_i {post_inc_int, sp},{post_inc_int,%1}
|
||||
move_i {post_inc_int, sp},{post_inc_int,%1}
|
||||
|
||||
/* ??? */
|
||||
#if WORD_SIZE==4
|
||||
pat sti $1==4*WORD_SIZE
|
||||
with AA_REG STACK
|
||||
kills ALL
|
||||
|
|
@ -3713,7 +3753,7 @@ with STACK
|
|||
kills ALL
|
||||
gen jsr {absolute4, ".mli"}
|
||||
yields dl1
|
||||
#endif TBL68020
|
||||
#endif
|
||||
|
||||
#if WORD_SIZE==2
|
||||
pat dvi $1==2
|
||||
|
|
@ -3756,7 +3796,7 @@ with data4-sconsts4 DD_REG4
|
|||
with STACK
|
||||
kills ALL
|
||||
gen jsr {absolute4, ".dvi"}
|
||||
yields dl0
|
||||
yields dl2
|
||||
#endif TBL68020
|
||||
|
||||
#if WORD_SIZE==2
|
||||
|
|
@ -4304,6 +4344,18 @@ with D_REG4 yields {regX, 4, %1}
|
|||
pat loc sli ads $1==3 && $2==4 && $3==4
|
||||
with D_REG4 yields {regX, 8, %1}
|
||||
leaving ads 4
|
||||
#else
|
||||
|
||||
pat loc sli $1==1 && $2==WORD_SIZE
|
||||
with DD_REG
|
||||
gen add_i %1, %1 yields %1
|
||||
|
||||
#if WORD_SIZE==2
|
||||
pat loc sli $1==1 && $2==4
|
||||
with DD_REG4
|
||||
gen add_l %1, %1 yields %1
|
||||
#endif
|
||||
|
||||
#endif TBL68020
|
||||
|
||||
|
||||
|
|
@ -4420,9 +4472,9 @@ pat loc loc ciu $1==2 && $2==4
|
|||
with zero_const
|
||||
yields {zero_const4, 0}
|
||||
with any
|
||||
uses reusing %1, DD_REG4
|
||||
uses DD_REG4 = {zero_const4, 0}
|
||||
gen move %1,%a.1
|
||||
ext_l %a yields %a
|
||||
yields %a
|
||||
|
||||
pat loc loc ciu $1==4 && $2==2
|
||||
with zero_const4
|
||||
|
|
@ -5380,11 +5432,11 @@ pat lfr $1==8 yields d1 d0
|
|||
pat ret $1==0
|
||||
gen return
|
||||
|
||||
pat asp ret $1==0
|
||||
pat asp ret $2==0
|
||||
gen return
|
||||
|
||||
#if WORD_SIZE==2
|
||||
pat ret $1 ==2
|
||||
pat ret $1==2
|
||||
with any2
|
||||
gen move %1, d0
|
||||
return
|
||||
|
|
@ -5539,7 +5591,6 @@ with DD_REG4 AA_REG AA_REG
|
|||
bne {slabel, 1b}
|
||||
2:
|
||||
|
||||
/* ??? interface */
|
||||
#if WORD_SIZE==2
|
||||
pat csa $1==2
|
||||
#if TBL68020
|
||||
|
|
@ -5665,7 +5716,7 @@ with STACK
|
|||
pat exg !defined($1)
|
||||
with any_int STACK
|
||||
kills ALL
|
||||
gen move_i %1, d0
|
||||
gen move %1, d0
|
||||
jsr {absolute4, ".exg"}
|
||||
|
||||
pat fil
|
||||
|
|
@ -5708,10 +5759,11 @@ with STACK
|
|||
kills ALL
|
||||
gen jsr {absolute4, ".mon"}
|
||||
|
||||
/* used by the ANSI-compiler to indicate volatile */
|
||||
pat nop
|
||||
with STACK
|
||||
kills ALL
|
||||
gen jsr {absolute4, ".nop"} /* */
|
||||
/* gen jsr {absolute4, ".nop"} */
|
||||
|
||||
#if WORD_SIZE==2
|
||||
#ifdef TBL68020
|
||||
|
|
|
|||
Loading…
Reference in a new issue