Make sign extension much less horrible.

This commit is contained in:
David Given 2019-02-08 23:16:57 +01:00
parent 0ac145a0d1
commit 0de5001f82
2 changed files with 158 additions and 37 deletions

View file

@ -1000,48 +1000,57 @@ pat loc loc cii $1==$2
pat loc loc cii $1==2 && $2==4 pat loc loc cii $1==2 && $2==4
with hl_or_de with hl_or_de
uses hl_or_de={const2,0}, areg uses hl_or_de, areg
gen mov a,%1.1 gen
ora a mov a, %1.1
jp {label,1f} ral.
lxi %a,{const2,0-1} sbb a
1: yields %a %1 mov %a.1, a
mov %a.2, a
yields %a %1
pat loc loc cii $1==4 && $2==2 pat loc loc cii $1==4 && $2==2
with hl_or_de hl_or_de yields %1 with hl_or_de hl_or_de
yields %1
pat loc loc cii $1==1 && $2==2 pat loc loc cii $1==1 && $2==2
with reg with reg
uses reusing %1, areg=%1, hl_or_de uses reusing %1, areg=%1, hl_or_de
gen move {const1,0},%b.1 gen
move a,%b.2 mov %b.2, a
ora a ral.
jp {label,1f} sbb a
mvi %b.1,{const1,255} mov %b.1, a
1: yields %b yields %b
with hl_or_de with hl_or_de
uses areg=%1.2 uses areg=%1.2
gen move {const1,0},%1.1 gen
ora a ral.
jp {label,1f} sbb a
mvi %1.1,{const1,255} mov %1.1, a
1: yields %1 yields %1
pat loc loc cii $1==1 && $2==4 pat loc loc cii $1==1 && $2==4
with reg with areg
uses hlreg uses hl_or_de, hl_or_de
gen move %1,l yields hl gen
leaving loc $1 loc $2 cii mov %b.2, a
ral.
sbb a
mov %b.1, a
mov %a.2, a
mov %a.1, a
yields %a %b
with hlreg with hlreg
uses dereg, areg uses dereg, areg
gen move {const1,0},%1.1 gen
move l,a mov a, l
ora a ral.
jp {label,1f} sbb a
mvi h,{const1,255} mov h, a
1: mov e, a
mov e,h mov d, a
mov d,h yields de hl yields de hl
pat cii pat cii
kills ALL kills ALL

112
tests/plat/core/cii_e.e Normal file
View file

@ -0,0 +1,112 @@
#
mes 2, EM_WSIZE, EM_PSIZE
exp $_m_a_i_n
pro $_m_a_i_n, 0
oneshort
onebyte
rom 1
moneshort
rom 65535
monebyte
rom 255
/* Positive byte->word */
loe onebyte
loc 1
loc EM_WSIZE
cii
loc 1
cmu EM_WSIZE
zeq *1
loc __LINE__
cal $fail
asp 4
1
/* Negative byte->word */
loe monebyte
loc 1
loc EM_WSIZE
cii
loc -1
cmu EM_WSIZE
zeq *2
loc __LINE__
cal $fail
asp 4
2
#if EM_WSIZE == 2
/* Positive byte->dword */
loe onebyte
loc 1
loc 4
cii
loc 0
loc 1
cmu 4
zeq *3
loc __LINE__
cal $fail
asp 4
3
/* Negative byte->short */
loe monebyte
loc 1
loc 4
cii
loc -1
loc -1
cmu 4
zeq *4
loc __LINE__
cal $fail
asp 4
4
/* Positive word->dword */
loe oneshort
loc 2
loc 4
cii
loc 0
loc 1
cmu 4
zeq *5
loc __LINE__
cal $fail
asp 4
5
/* Negative word->short */
loe moneshort
loc 2
loc 4
cii
loc -1
loc -1
cmu 4
zeq *6
loc __LINE__
cal $fail
asp 4
6
#endif
cal $finished
end