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Make loads and stores in the table nicer; fix a place where it looked like it

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was working but only accidentally.
This commit is contained in:
David Given 2016-10-12 23:12:53 +02:00
parent f06b51c981
commit 216ff5cc43
1 changed files with 45 additions and 23 deletions
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66
mach/proto/mcg/table
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@ -77,7 +77,8 @@ REGISTERS
DECLARATIONS DECLARATIONS
cr; cr;
ubyte_to_be; ubyte;
ushort;
address fragment; address fragment;
@ -127,53 +128,74 @@ PATTERNS
/* Memory operations */ /* Memory operations */
/* Stores */
STORE4(addr:address, value:(int)reg) STORE4(addr:address, value:(int)reg)
emit "stw %value, %addr" emit "stw %value, %addr"
cost 4; cost 4;
STORE2(addr:address, value:(int)reg) STORE2(addr:address, value:(int)ushort)
emit "sth %value, %addr" emit "sth %value, %addr"
cost 4; cost 4;
STORE1(addr:address, value:(int)ubyte_to_be) STORE2(ADD4(left:(int)reg, right:(int)reg), value:(int)ushort)
emit "sthx %value, %left, %right"
cost 4;
STORE1(addr:address, value:(int)ubyte)
emit "stb %value, %addr" emit "stb %value, %addr"
cost 4; cost 4;
STORE1(ADD4(left:(int)reg, right:(int)reg), value:(int)ubyte_to_be) STORE1(ADD4(left:(int)reg, right:(int)reg), value:(int)ubyte)
emit "stbx %value, %left, %right" emit "stbx %value, %left, %right"
cost 4; cost 4;
out:(int)ubyte_to_be = in:(int)reg /* Loads */
emit "! reg -> ubyte"
cost 1;
out:(int)ubyte_to_be = CIU41(value:(int)reg)
emit "! CIU41(reg) -> ubyte"
cost 1;
out:(int)ubyte_to_be = CIU41(CII14(CIU41(value:(int)reg)))
emit "! CIU41(CII14(CIU41(reg))) -> ubyte"
cost 1;
out:(int)reg = LOAD4(addr:address) out:(int)reg = LOAD4(addr:address)
emit "lwz %out, %addr" emit "lwz %out, %addr"
cost 4; cost 4;
out:(int)reg = LOAD2(addr:address) out:(int)ushort = LOAD2(addr:address)
emit "lhz %out, %addr" emit "lhz %out, %addr"
cost 4; cost 4;
out:(int)reg = LOAD1(addr:address) out:(int)ubyte = LOAD1(addr:address)
emit "lbz %out, %addr" emit "lbz %out, %addr"
cost 4; cost 4;
out:(int)reg = CIU14(LOAD1(addr:address)) /* Conversions to ubyte and ushort */
emit "lbz %out, %addr"
out:(int)ubyte = in:(int)reg
emit "mr %out, %in ! reg -> ubyte"
cost 1;
out:(int)ubyte = CIU41(value:(int)reg)
emit "mr %out, %value ! CIU41(reg) -> ubyte"
cost 1;
out:(int)ubyte = CIU41(CII14(CIU41(value:(int)reg)))
emit "mr %out, %value ! CIU41(CII14(CIU41(reg))) -> ubyte"
cost 1;
out:(int)ushort = in:(int)reg
emit "mr %out, %in ! reg -> ushort"
cost 1;
out:(int)ushort = CIU42(value:(int)reg)
emit "mr %out, %value ! CIU42(reg) -> ushort"
cost 1;
out:(int)ushort = CIU42(CII24(CIU42(value:(int)reg)))
emit "mr %out, %value ! CIU42(CII24(CIU42(reg))) -> ushort"
cost 1;
/* Conversions from ubyte and ushort */
out:(int)reg = CIU14(in:(int)ubyte)
emit "mr %out, %in ! CIU14"
cost 4; cost 4;
out:(int)reg = CIU24(LOAD2(addr:address))
emit "lhz %out, %addr"
cost 4;