fixed bug in SIM and SIG
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d260937564
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264773ee06
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@ -2846,9 +2846,11 @@ with STACK
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pat lim yields {absolute4, ".trpim"}
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pat lim yields {absolute4, ".trpim"}
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pat lin
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pat lin
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kills posextern
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gen move {const, $1}, {absolute4, ".lino"}
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gen move {const, $1}, {absolute4, ".lino"}
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pat lni
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pat lni
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kills posextern
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gen add_l {const, 1}, {absolute4, ".lino"}
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gen add_l {const, 1}, {absolute4, ".lino"}
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pat lor $1==0 yields lb
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pat lor $1==0 yields lb
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@ -2901,6 +2903,7 @@ pat rtt leaving ret 0
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pat sig
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pat sig
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with any4
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with any4
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kills posextern
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uses AA_REG
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uses AA_REG
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gen move {absolute4, ".trppc"}, %a
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gen move {absolute4, ".trppc"}, %a
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move %1, {absolute4, ".trppc"}
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move %1, {absolute4, ".trppc"}
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@ -2908,6 +2911,7 @@ with any4
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pat sim
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pat sim
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with any4
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with any4
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kills posextern
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gen move_l %1, {absolute4, ".trpim"}
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gen move_l %1, {absolute4, ".trpim"}
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pat str $1==0
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pat str $1==0
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@ -2846,9 +2846,11 @@ with STACK
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pat lim yields {absolute4, ".trpim"}
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pat lim yields {absolute4, ".trpim"}
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pat lin
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pat lin
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kills posextern
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gen move {const, $1}, {absolute4, ".lino"}
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gen move {const, $1}, {absolute4, ".lino"}
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pat lni
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pat lni
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kills posextern
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gen add_l {const, 1}, {absolute4, ".lino"}
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gen add_l {const, 1}, {absolute4, ".lino"}
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pat lor $1==0 yields lb
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pat lor $1==0 yields lb
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@ -2901,6 +2903,7 @@ pat rtt leaving ret 0
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pat sig
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pat sig
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with any4
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with any4
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kills posextern
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uses AA_REG
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uses AA_REG
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gen move {absolute4, ".trppc"}, %a
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gen move {absolute4, ".trppc"}, %a
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move %1, {absolute4, ".trppc"}
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move %1, {absolute4, ".trppc"}
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@ -2908,6 +2911,7 @@ with any4
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pat sim
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pat sim
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with any4
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with any4
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kills posextern
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gen move_l %1, {absolute4, ".trpim"}
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gen move_l %1, {absolute4, ".trpim"}
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pat str $1==0
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pat str $1==0
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@ -2846,9 +2846,11 @@ with STACK
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pat lim yields {absolute4, ".trpim"}
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pat lim yields {absolute4, ".trpim"}
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pat lin
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pat lin
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kills posextern
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gen move {const, $1}, {absolute4, ".lino"}
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gen move {const, $1}, {absolute4, ".lino"}
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pat lni
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pat lni
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kills posextern
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gen add_l {const, 1}, {absolute4, ".lino"}
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gen add_l {const, 1}, {absolute4, ".lino"}
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pat lor $1==0 yields lb
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pat lor $1==0 yields lb
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@ -2901,6 +2903,7 @@ pat rtt leaving ret 0
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pat sig
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pat sig
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with any4
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with any4
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kills posextern
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uses AA_REG
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uses AA_REG
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gen move {absolute4, ".trppc"}, %a
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gen move {absolute4, ".trppc"}, %a
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move %1, {absolute4, ".trppc"}
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move %1, {absolute4, ".trppc"}
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@ -2908,6 +2911,7 @@ with any4
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pat sim
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pat sim
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with any4
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with any4
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kills posextern
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gen move_l %1, {absolute4, ".trpim"}
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gen move_l %1, {absolute4, ".trpim"}
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pat str $1==0
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pat str $1==0
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@ -2846,9 +2846,11 @@ with STACK
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pat lim yields {absolute4, ".trpim"}
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pat lim yields {absolute4, ".trpim"}
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pat lin
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pat lin
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kills posextern
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gen move {const, $1}, {absolute4, ".lino"}
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gen move {const, $1}, {absolute4, ".lino"}
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pat lni
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pat lni
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kills posextern
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gen add_l {const, 1}, {absolute4, ".lino"}
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gen add_l {const, 1}, {absolute4, ".lino"}
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pat lor $1==0 yields lb
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pat lor $1==0 yields lb
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@ -2901,6 +2903,7 @@ pat rtt leaving ret 0
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pat sig
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pat sig
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with any4
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with any4
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kills posextern
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uses AA_REG
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uses AA_REG
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gen move {absolute4, ".trppc"}, %a
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gen move {absolute4, ".trppc"}, %a
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move %1, {absolute4, ".trppc"}
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move %1, {absolute4, ".trppc"}
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@ -2908,6 +2911,7 @@ with any4
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pat sim
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pat sim
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with any4
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with any4
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kills posextern
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gen move_l %1, {absolute4, ".trpim"}
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gen move_l %1, {absolute4, ".trpim"}
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pat str $1==0
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pat str $1==0
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