Add in floating point support to the code generator.
This commit is contained in:
David Given
parent
83cf1be6a8
commit
26f9b4ceae
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@ -9,7 +9,7 @@
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# Useful pseudoops.
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000000<RS->00000<RD->00000100000 "move" RD=gpr ',' RS=gpr
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000000<RS->00000<RD->00000100000 "mov" RD=gpr ',' RS=gpr
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# Core ALU instructions.
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@ -120,8 +120,9 @@ struct hop* platform_epilogue(void)
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hop_add_insel(hop, "lw ra, 4(fp)");
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hop_add_insel(hop, "lw at, 0(fp)"); /* load old fp */
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hop_add_insel(hop, "addiu sp, fp, %d", current_proc->fp_to_ab);
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hop_add_insel(hop, "move fp, at");
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hop_add_insel(hop, "mov fp, at");
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hop_add_insel(hop, "jr ra");
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hop_add_insel(hop, "nop");
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return hop;
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}
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@ -200,6 +201,7 @@ struct hop* platform_move(struct basicblock* bb, struct hreg* src, struct hreg*
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else
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{
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uint32_t type = src->attrs & TYPE_ATTRS;
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tracef('R', "R: non-converting move from %s to %s of type 0x%x\n", src->id, dest->id, type);
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if (!src->is_stacked && dest->is_stacked)
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{
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@ -251,17 +253,20 @@ struct hop* platform_move(struct basicblock* bb, struct hreg* src, struct hreg*
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switch (type)
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{
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case burm_int_ATTR:
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hop_add_insel(hop, "move %H, %H", dest, src);
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hop_add_insel(hop, "mov %H, %H", dest, src);
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break;
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case burm_long_ATTR:
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hop_add_insel(hop, "move %0H, %0H", dest, src);
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hop_add_insel(hop, "move %1H, %1H", dest, src);
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hop_add_insel(hop, "mov %0H, %0H", dest, src);
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hop_add_insel(hop, "mov %1H, %1H", dest, src);
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break;
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case burm_float_ATTR:
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hop_add_insel(hop, "mov.f %H, %H", dest, src);
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break;
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case burm_double_ATTR:
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hop_add_insel(hop, "fmr %H, %H", dest, src);
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hop_add_insel(hop, "mov.d %H, %H", dest, src);
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break;
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default:
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@ -289,26 +294,31 @@ struct hop* platform_swap(struct basicblock* bb, struct hreg* src, struct hreg*
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switch (src->attrs & TYPE_ATTRS)
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{
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case burm_int_ATTR:
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hop_add_insel(hop, "mr r0, %H", src);
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hop_add_insel(hop, "mr %H, %H", src, dest);
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hop_add_insel(hop, "mr %H, r0", dest);
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hop_add_insel(hop, "mov at, %H", src);
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hop_add_insel(hop, "mov %H, %H", src, dest);
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hop_add_insel(hop, "mov %H, at", dest);
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break;
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case burm_long_ATTR:
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hop_add_insel(hop, "mr r0, %0H", src);
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hop_add_insel(hop, "mr %0H, %0H", src, dest);
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hop_add_insel(hop, "mr %0H, r0", dest);
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hop_add_insel(hop, "mov at, %0H", src);
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hop_add_insel(hop, "mov %0H, %0H", src, dest);
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hop_add_insel(hop, "mov %0H, at", dest);
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hop_add_insel(hop, "mr r0, %1H", src);
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hop_add_insel(hop, "mr %1H, %1H", src, dest);
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hop_add_insel(hop, "mr %1H, r0", dest);
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hop_add_insel(hop, "mov at, %1H", src);
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hop_add_insel(hop, "mov %1H, %1H", src, dest);
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hop_add_insel(hop, "mov %1H, at", dest);
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break;
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case burm_float_ATTR:
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hop_add_insel(hop, "mov.f f31, %H", src);
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hop_add_insel(hop, "mov.f %H, %H", src, dest);
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hop_add_insel(hop, "mov.f %H, f31", dest);
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break;
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case burm_double_ATTR:
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hop_add_insel(hop, "fmr f0, %H", src);
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hop_add_insel(hop, "fmr %H, %H", src, dest);
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hop_add_insel(hop, "fmr %H, f0", dest);
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hop_add_insel(hop, "mov.d f31, %H", src);
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hop_add_insel(hop, "mov.d %H, %H", src, dest);
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hop_add_insel(hop, "mov.d %H, f31", dest);
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break;
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}
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@ -10,22 +10,22 @@ REGISTERS
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* be moved from register to register or spilt).
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*/
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r4 named("r4") int volatile;
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r5 named("r5") int volatile;
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r6 named("r6") int volatile;
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r7 named("r7") int volatile;
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r8 named("r8") int volatile;
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r9 named("r9") int volatile;
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r10 named("r10") int volatile;
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r11 named("r11") int volatile;
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r12 named("r12") int volatile;
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r13 named("r13") int volatile;
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r14 named("r14") int volatile;
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r15 named("r15") int volatile;
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r24 named("r24") int volatile;
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r25 named("r25") int volatile;
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r2 named("r2") int volatile iret;
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r3 named("r3") int volatile;
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r4 int volatile;
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r5 int volatile;
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r6 int volatile;
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r7 int volatile;
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r8 int volatile;
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r9 int volatile;
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r10 int volatile;
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r11 int volatile;
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r12 int volatile;
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r13 int volatile;
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r14 int volatile;
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r15 int volatile;
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r24 int volatile;
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r25 int volatile;
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r2 int volatile iret;
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r3 int volatile;
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r17 named("r16") int;
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r18 named("r18") int;
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@ -44,10 +44,74 @@ REGISTERS
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r24r25 named("r24", "r25") aliases(r24, r25) long volatile;
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r2r3 named("r2", "r3") aliases(r2, r3) long volatile lret;
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zero named("zero") zero int volatile;
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f0 float volatile fret;
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f1 float volatile;
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f2 float volatile;
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f3 float volatile;
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f4 float volatile;
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f5 float volatile;
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f6 float volatile;
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f7 float volatile;
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f8 float volatile;
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f9 float volatile;
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f10 float volatile;
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f11 float volatile;
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f12 float volatile;
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f13 float volatile;
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f14 float volatile;
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f15 float volatile;
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f16 float volatile;
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f17 float volatile;
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f18 float volatile;
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f19 float volatile;
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f20 float;
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f21 float;
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f22 float;
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f23 float;
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f24 float;
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f25 float;
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f26 float;
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f27 float;
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f28 float;
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f29 float;
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f30 float;
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/* f31 is used by the compiler as a temporary. */
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d0 named("f0") aliases(f0) double volatile dret;
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d1 named("f1") aliases(f1) double volatile;
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d2 named("f2") aliases(f2) double volatile;
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d3 named("f3") aliases(f3) double volatile;
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d4 named("f4") aliases(f4) double volatile;
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d5 named("f5") aliases(f5) double volatile;
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d6 named("f6") aliases(f6) double volatile;
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d7 named("f7") aliases(f7) double volatile;
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d8 named("f8") aliases(f8) double volatile;
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d9 named("f9") aliases(f9) double volatile;
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d10 named("f10") aliases(f10) double volatile;
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d11 named("f11") aliases(f11) double volatile;
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d12 named("f12") aliases(f12) double volatile;
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d13 named("f13") aliases(f13) double volatile;
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d14 named("f14") aliases(f14) double volatile;
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d15 named("f15") aliases(f15) double volatile;
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d16 named("f16") aliases(f16) double volatile;
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d17 named("f17") aliases(f17) double volatile;
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d18 named("f18") aliases(f18) double volatile;
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d19 named("f19") aliases(f19) double volatile;
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d20 named("f20") aliases(f20) double;
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d21 named("f21") aliases(f21) double;
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d22 named("f22") aliases(f22) double;
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d23 named("f23") aliases(f23) double;
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d24 named("f24") aliases(f24) double;
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d25 named("f25") aliases(f25) double;
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d26 named("f26") aliases(f26) double;
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d27 named("f27") aliases(f27) double;
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d28 named("f28") aliases(f28) double;
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d29 named("f29") aliases(f29) double;
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d30 named("f30") aliases(f30) double;
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f0 float;
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d0 double;
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DECLARATIONS
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@ -81,6 +145,16 @@ PATTERNS
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emit "sw %in.1, 4(sp)"
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cost 12;
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PUSH.F(in:(float)reg)
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emit "addiu sp, sp, -4"
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emit "swc1 %in, 0(sp)"
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cost 8;
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PUSH.D(in:(double)reg)
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emit "addiu sp, sp, -8"
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emit "sdc1 %in, 0(sp)"
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cost 8;
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out:(int)reg = POP.I
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emit "lw %out, 0(sp)"
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emit "addiu sp, sp, 4"
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@ -92,14 +166,32 @@ PATTERNS
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emit "addiu sp, sp, 8"
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cost 12;
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out:(float)reg = POP.F
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emit "lwc1 %out, 0(sp)"
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emit "addiu sp, sp, 4"
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cost 8;
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out:(double)reg = POP.D
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emit "ldc1 %out, 0(sp)"
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emit "addiu sp, sp, 8"
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cost 8;
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SETRET.I(in:(iret)reg)
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emit "! setret4"
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emit "! setret.i"
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cost 1;
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SETRET.L(in:(lret)reg)
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emit "! setret8"
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emit "! setret.l"
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cost 1;
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SETRET.F(in:(fret)reg)
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emit "! setret.f"
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cost 1;
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SETRET.D(in:(dret)reg)
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emit "! setret.d"
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cost 1;
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STACKADJUST.I(delta:CONST.I)
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when signed_constant(%delta, 16)
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emit "addiu sp, sp, $delta"
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@ -114,11 +206,11 @@ PATTERNS
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cost 4;
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out:(int)reg = GETFP.I
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emit "move %out, fp"
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emit "mov %out, fp"
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cost 4;
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SETFP.I(in:(int)reg)
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emit "move fp, %in"
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emit "mov fp, %in"
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cost 4;
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out:(int)reg = CHAINFP.I(in:(int)reg)
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@ -138,11 +230,11 @@ PATTERNS
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cost 1;
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out:(int)reg = GETSP.I
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emit "move %out, sp"
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emit "mov %out, sp"
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cost 4;
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SETSP.I(in:(int)reg)
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emit "move sp, %in"
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emit "mov sp, %in"
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cost 4;
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out:(int)reg = ANY.I
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@ -174,6 +266,14 @@ PATTERNS
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emit "sb %value, %addr"
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cost 4;
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STORE.F(addr:address, value:(float)reg)
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emit "swc1 %value, %addr"
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cost 4;
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STORE.D(addr:address, value:(double)reg)
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emit "sdc1 %value, %addr"
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cost 4;
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/* Loads */
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out:(int)reg = LOAD.I(addr:address)
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@ -186,7 +286,7 @@ PATTERNS
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out:(long)reg = LOAD.L(addr:address)
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emit "lw at, 4+%addr"
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emit "lw %out.1, 0+%addr"
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emit "move %out.0, at"
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emit "mov %out.0, at"
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cost 12;
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out:(int)ushort0 = LOADH.I(addr:address)
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@ -197,6 +297,14 @@ PATTERNS
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emit "lb %out, %addr"
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cost 4;
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out:(float)reg = LOAD.F(addr:address)
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emit "lwc1 %out, %addr"
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cost 4;
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out:(double)reg = LOAD.D(addr:address)
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emit "ldc1 %out, %addr"
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cost 4;
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/* ubyte intrinsics */
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out:(int)ubyteX = in:(int)ubyte0
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@ -262,7 +370,7 @@ PATTERNS
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cost 1;
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out:(long)reg = FROMSI.L(in:(int)reg)
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emit "move %out.0, %in"
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emit "mov %out.0, %in"
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emit "sra %out.1, %in, 31"
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cost 8;
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@ -272,16 +380,16 @@ PATTERNS
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cost 8;
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out:(lret)reg = FROMIPAIR.L(in1:(int)reg, in2:(int)reg)
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emit "move %out.0, %in1"
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emit "move %out.1, %in2"
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emit "mov %out.0, %in1"
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emit "mov %out.1, %in2"
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cost 8;
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out:(int)reg = FROML0.I(in:(long)reg)
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emit "move %out, %in.0"
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emit "mov %out, %in.0"
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cost 4;
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out:(int)reg = FROML1.I(in:(long)reg)
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emit "move %out, %in.1"
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emit "mov %out, %in.1"
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cost 4;
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@ -419,7 +527,7 @@ PATTERNS
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out:(int)reg = COMPARESI.I(left:(int)reg, right:(int)reg)
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emit "slt at, %left, %right"
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emit "bne at, zero, 1f"
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emit "li %out, -1"
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emit "li %out, -1" /* delay slot */
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emit "slt %out, %right, %left"
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emit "1:"
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cost 20;
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@ -427,17 +535,26 @@ PATTERNS
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out:(int)reg = COMPAREUI.I(left:(int)reg, right:(int)reg)
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emit "sltu at, %left, %right"
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emit "bne at, zero, 1f"
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emit "li %out, -1"
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emit "li %out, -1" /* delay slot */
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emit "sltu %out, %right, %left"
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emit "1:"
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cost 20;
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out:(int)reg = COMPARED.I(left:(double)reg, right:(double)reg)
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emit "c.lt.d 0, %left, %right"
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emit "bc1t 0, 1f"
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emit "li %out, -1" /* delay slot */
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emit "c.lt.d 0, %right, %left"
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emit "li %out, 1"
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emit "movf %out, zero, 0"
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cost 28;
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/* Booleans */
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/* If 0 then 1, else 0 */
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out:(int)reg = IFEQ.I(in:(int)reg)
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emit "sleu %out, %in, zero"
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cost 4;;
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cost 4;
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/* If -1 then 1, else 0 */
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out:(int)reg = IFLT.I(in:(int)reg)
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@ -557,10 +674,55 @@ PATTERNS
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emit "li %out, $value"
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cost 4;
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out:(zero)reg = value:CONST.I
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when specific_constant(%value, 0)
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cost 1;
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/* FPU operations */
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/* Doubles */
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out:(double)reg = ADDF.D(left:(double)reg, right:(double)reg)
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emit "add.d %out, %left, %right"
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cost 4;
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out:(double)reg = SUBF.D(left:(double)reg, right:(double)reg)
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emit "sub.d %out, %left, %right"
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cost 4;
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out:(double)reg = MULF.D(left:(double)reg, right:(double)reg)
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emit "mul.d %out, %left, %right"
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cost 4;
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out:(double)reg = DIVF.D(left:(double)reg, right:(double)reg)
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emit "div.d %out, %left, %right"
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cost 4;
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out:(double)reg = FROMSI.D(in:(int)reg)
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emit "mtc1 %out, %in"
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emit "cvt.d.w %out, %out"
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cost 4;
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/* Floats */
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out:(float)reg = ADDF.F(left:(float)reg, right:(float)reg)
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emit "add.d %out, %left, %right"
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cost 4;
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out:(float)reg = SUBF.F(left:(float)reg, right:(float)reg)
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emit "sub.d %out, %left, %right"
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cost 4;
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out:(float)reg = MULF.F(left:(float)reg, right:(float)reg)
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emit "mul.d %out, %left, %right"
|
||||
cost 4;
|
||||
|
||||
out:(float)reg = DIVF.F(left:(float)reg, right:(float)reg)
|
||||
emit "div.d %out, %left, %right"
|
||||
cost 4;
|
||||
|
||||
out:(float)reg = FROMSI.F(in:(int)reg)
|
||||
emit "mtc1 %out, %in"
|
||||
emit "cvt.s.w %out, %out"
|
||||
cost 4;
|
||||
|
||||
/* vim: set sw=4 ts=4 expandtab : */
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue