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Add in floating point support to the code generator.

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This commit is contained in:
David Given 2018-09-03 22:06:05 +02:00
parent 83cf1be6a8
commit 26f9b4ceae
3 changed files with 227 additions and 55 deletions
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2
mach/mips/as/instructions.dat
View file

@ -9,7 +9,7 @@
# Useful pseudoops. # Useful pseudoops.
000000<RS->00000<RD->00000100000 "move" RD=gpr ',' RS=gpr 000000<RS->00000<RD->00000100000 "mov" RD=gpr ',' RS=gpr
# Core ALU instructions. # Core ALU instructions.

44
mach/mips/mcg/platform.c
View file

@ -120,8 +120,9 @@ struct hop* platform_epilogue(void)
hop_add_insel(hop, "lw ra, 4(fp)"); hop_add_insel(hop, "lw ra, 4(fp)");
hop_add_insel(hop, "lw at, 0(fp)"); /* load old fp */ hop_add_insel(hop, "lw at, 0(fp)"); /* load old fp */
hop_add_insel(hop, "addiu sp, fp, %d", current_proc->fp_to_ab); hop_add_insel(hop, "addiu sp, fp, %d", current_proc->fp_to_ab);
hop_add_insel(hop, "move fp, at"); hop_add_insel(hop, "mov fp, at");
hop_add_insel(hop, "jr ra"); hop_add_insel(hop, "jr ra");
hop_add_insel(hop, "nop");
return hop; return hop;
} }
@ -200,6 +201,7 @@ struct hop* platform_move(struct basicblock* bb, struct hreg* src, struct hreg*
else else
{ {
uint32_t type = src->attrs & TYPE_ATTRS; uint32_t type = src->attrs & TYPE_ATTRS;
tracef('R', "R: non-converting move from %s to %s of type 0x%x\n", src->id, dest->id, type);
if (!src->is_stacked && dest->is_stacked) if (!src->is_stacked && dest->is_stacked)
{ {
@ -251,17 +253,20 @@ struct hop* platform_move(struct basicblock* bb, struct hreg* src, struct hreg*
switch (type) switch (type)
{ {
case burm_int_ATTR: case burm_int_ATTR:
hop_add_insel(hop, "move %H, %H", dest, src); hop_add_insel(hop, "mov %H, %H", dest, src);
break; break;
case burm_long_ATTR: case burm_long_ATTR:
hop_add_insel(hop, "move %0H, %0H", dest, src); hop_add_insel(hop, "mov %0H, %0H", dest, src);
hop_add_insel(hop, "move %1H, %1H", dest, src); hop_add_insel(hop, "mov %1H, %1H", dest, src);
break; break;
case burm_float_ATTR: case burm_float_ATTR:
hop_add_insel(hop, "mov.f %H, %H", dest, src);
break;
case burm_double_ATTR: case burm_double_ATTR:
hop_add_insel(hop, "fmr %H, %H", dest, src); hop_add_insel(hop, "mov.d %H, %H", dest, src);
break; break;
default: default:
@ -289,26 +294,31 @@ struct hop* platform_swap(struct basicblock* bb, struct hreg* src, struct hreg*
switch (src->attrs & TYPE_ATTRS) switch (src->attrs & TYPE_ATTRS)
{ {
case burm_int_ATTR: case burm_int_ATTR:
hop_add_insel(hop, "mr r0, %H", src); hop_add_insel(hop, "mov at, %H", src);
hop_add_insel(hop, "mr %H, %H", src, dest); hop_add_insel(hop, "mov %H, %H", src, dest);
hop_add_insel(hop, "mr %H, r0", dest); hop_add_insel(hop, "mov %H, at", dest);
break; break;
case burm_long_ATTR: case burm_long_ATTR:
hop_add_insel(hop, "mr r0, %0H", src); hop_add_insel(hop, "mov at, %0H", src);
hop_add_insel(hop, "mr %0H, %0H", src, dest); hop_add_insel(hop, "mov %0H, %0H", src, dest);
hop_add_insel(hop, "mr %0H, r0", dest); hop_add_insel(hop, "mov %0H, at", dest);
hop_add_insel(hop, "mr r0, %1H", src); hop_add_insel(hop, "mov at, %1H", src);
hop_add_insel(hop, "mr %1H, %1H", src, dest); hop_add_insel(hop, "mov %1H, %1H", src, dest);
hop_add_insel(hop, "mr %1H, r0", dest); hop_add_insel(hop, "mov %1H, at", dest);
break; break;
case burm_float_ATTR: case burm_float_ATTR:
hop_add_insel(hop, "mov.f f31, %H", src);
hop_add_insel(hop, "mov.f %H, %H", src, dest);
hop_add_insel(hop, "mov.f %H, f31", dest);
break;
case burm_double_ATTR: case burm_double_ATTR:
hop_add_insel(hop, "fmr f0, %H", src); hop_add_insel(hop, "mov.d f31, %H", src);
hop_add_insel(hop, "fmr %H, %H", src, dest); hop_add_insel(hop, "mov.d %H, %H", src, dest);
hop_add_insel(hop, "fmr %H, f0", dest); hop_add_insel(hop, "mov.d %H, f31", dest);
break; break;
} }

236
mach/mips/mcg/table
View file

@ -10,22 +10,22 @@ REGISTERS
* be moved from register to register or spilt). * be moved from register to register or spilt).
*/ */
r4 named("r4") int volatile; r4 int volatile;
r5 named("r5") int volatile; r5 int volatile;
r6 named("r6") int volatile; r6 int volatile;
r7 named("r7") int volatile; r7 int volatile;
r8 named("r8") int volatile; r8 int volatile;
r9 named("r9") int volatile; r9 int volatile;
r10 named("r10") int volatile; r10 int volatile;
r11 named("r11") int volatile; r11 int volatile;
r12 named("r12") int volatile; r12 int volatile;
r13 named("r13") int volatile; r13 int volatile;
r14 named("r14") int volatile; r14 int volatile;
r15 named("r15") int volatile; r15 int volatile;
r24 named("r24") int volatile; r24 int volatile;
r25 named("r25") int volatile; r25 int volatile;
r2 named("r2") int volatile iret; r2 int volatile iret;
r3 named("r3") int volatile; r3 int volatile;
r17 named("r16") int; r17 named("r16") int;
r18 named("r18") int; r18 named("r18") int;
@ -44,10 +44,74 @@ REGISTERS
r24r25 named("r24", "r25") aliases(r24, r25) long volatile; r24r25 named("r24", "r25") aliases(r24, r25) long volatile;
r2r3 named("r2", "r3") aliases(r2, r3) long volatile lret; r2r3 named("r2", "r3") aliases(r2, r3) long volatile lret;
zero named("zero") zero int volatile; f0 float volatile fret;
f1 float volatile;
f2 float volatile;
f3 float volatile;
f4 float volatile;
f5 float volatile;
f6 float volatile;
f7 float volatile;
f8 float volatile;
f9 float volatile;
f10 float volatile;
f11 float volatile;
f12 float volatile;
f13 float volatile;
f14 float volatile;
f15 float volatile;
f16 float volatile;
f17 float volatile;
f18 float volatile;
f19 float volatile;
f20 float;
f21 float;
f22 float;
f23 float;
f24 float;
f25 float;
f26 float;
f27 float;
f28 float;
f29 float;
f30 float;
/* f31 is used by the compiler as a temporary. */
d0 named("f0") aliases(f0) double volatile dret;
d1 named("f1") aliases(f1) double volatile;
d2 named("f2") aliases(f2) double volatile;
d3 named("f3") aliases(f3) double volatile;
d4 named("f4") aliases(f4) double volatile;
d5 named("f5") aliases(f5) double volatile;
d6 named("f6") aliases(f6) double volatile;
d7 named("f7") aliases(f7) double volatile;
d8 named("f8") aliases(f8) double volatile;
d9 named("f9") aliases(f9) double volatile;
d10 named("f10") aliases(f10) double volatile;
d11 named("f11") aliases(f11) double volatile;
d12 named("f12") aliases(f12) double volatile;
d13 named("f13") aliases(f13) double volatile;
d14 named("f14") aliases(f14) double volatile;
d15 named("f15") aliases(f15) double volatile;
d16 named("f16") aliases(f16) double volatile;
d17 named("f17") aliases(f17) double volatile;
d18 named("f18") aliases(f18) double volatile;
d19 named("f19") aliases(f19) double volatile;
d20 named("f20") aliases(f20) double;
d21 named("f21") aliases(f21) double;
d22 named("f22") aliases(f22) double;
d23 named("f23") aliases(f23) double;
d24 named("f24") aliases(f24) double;
d25 named("f25") aliases(f25) double;
d26 named("f26") aliases(f26) double;
d27 named("f27") aliases(f27) double;
d28 named("f28") aliases(f28) double;
d29 named("f29") aliases(f29) double;
d30 named("f30") aliases(f30) double;
f0 float;
d0 double;
DECLARATIONS DECLARATIONS
@ -81,6 +145,16 @@ PATTERNS
emit "sw %in.1, 4(sp)" emit "sw %in.1, 4(sp)"
cost 12; cost 12;
PUSH.F(in:(float)reg)
emit "addiu sp, sp, -4"
emit "swc1 %in, 0(sp)"
cost 8;
PUSH.D(in:(double)reg)
emit "addiu sp, sp, -8"
emit "sdc1 %in, 0(sp)"
cost 8;
out:(int)reg = POP.I out:(int)reg = POP.I
emit "lw %out, 0(sp)" emit "lw %out, 0(sp)"
emit "addiu sp, sp, 4" emit "addiu sp, sp, 4"
@ -92,14 +166,32 @@ PATTERNS
emit "addiu sp, sp, 8" emit "addiu sp, sp, 8"
cost 12; cost 12;
out:(float)reg = POP.F
emit "lwc1 %out, 0(sp)"
emit "addiu sp, sp, 4"
cost 8;
out:(double)reg = POP.D
emit "ldc1 %out, 0(sp)"
emit "addiu sp, sp, 8"
cost 8;
SETRET.I(in:(iret)reg) SETRET.I(in:(iret)reg)
emit "! setret4" emit "! setret.i"
cost 1; cost 1;
SETRET.L(in:(lret)reg) SETRET.L(in:(lret)reg)
emit "! setret8" emit "! setret.l"
cost 1; cost 1;
SETRET.F(in:(fret)reg)
emit "! setret.f"
cost 1;
SETRET.D(in:(dret)reg)
emit "! setret.d"
cost 1;
STACKADJUST.I(delta:CONST.I) STACKADJUST.I(delta:CONST.I)
when signed_constant(%delta, 16) when signed_constant(%delta, 16)
emit "addiu sp, sp, $delta" emit "addiu sp, sp, $delta"
@ -114,11 +206,11 @@ PATTERNS
cost 4; cost 4;
out:(int)reg = GETFP.I out:(int)reg = GETFP.I
emit "move %out, fp" emit "mov %out, fp"
cost 4; cost 4;
SETFP.I(in:(int)reg) SETFP.I(in:(int)reg)
emit "move fp, %in" emit "mov fp, %in"
cost 4; cost 4;
out:(int)reg = CHAINFP.I(in:(int)reg) out:(int)reg = CHAINFP.I(in:(int)reg)
@ -138,11 +230,11 @@ PATTERNS
cost 1; cost 1;
out:(int)reg = GETSP.I out:(int)reg = GETSP.I
emit "move %out, sp" emit "mov %out, sp"
cost 4; cost 4;
SETSP.I(in:(int)reg) SETSP.I(in:(int)reg)
emit "move sp, %in" emit "mov sp, %in"
cost 4; cost 4;
out:(int)reg = ANY.I out:(int)reg = ANY.I
@ -174,6 +266,14 @@ PATTERNS
emit "sb %value, %addr" emit "sb %value, %addr"
cost 4; cost 4;
STORE.F(addr:address, value:(float)reg)
emit "swc1 %value, %addr"
cost 4;
STORE.D(addr:address, value:(double)reg)
emit "sdc1 %value, %addr"
cost 4;
/* Loads */ /* Loads */
out:(int)reg = LOAD.I(addr:address) out:(int)reg = LOAD.I(addr:address)
@ -186,7 +286,7 @@ PATTERNS
out:(long)reg = LOAD.L(addr:address) out:(long)reg = LOAD.L(addr:address)
emit "lw at, 4+%addr" emit "lw at, 4+%addr"
emit "lw %out.1, 0+%addr" emit "lw %out.1, 0+%addr"
emit "move %out.0, at" emit "mov %out.0, at"
cost 12; cost 12;
out:(int)ushort0 = LOADH.I(addr:address) out:(int)ushort0 = LOADH.I(addr:address)
@ -197,6 +297,14 @@ PATTERNS
emit "lb %out, %addr" emit "lb %out, %addr"
cost 4; cost 4;
out:(float)reg = LOAD.F(addr:address)
emit "lwc1 %out, %addr"
cost 4;
out:(double)reg = LOAD.D(addr:address)
emit "ldc1 %out, %addr"
cost 4;
/* ubyte intrinsics */ /* ubyte intrinsics */
out:(int)ubyteX = in:(int)ubyte0 out:(int)ubyteX = in:(int)ubyte0
@ -262,7 +370,7 @@ PATTERNS
cost 1; cost 1;
out:(long)reg = FROMSI.L(in:(int)reg) out:(long)reg = FROMSI.L(in:(int)reg)
emit "move %out.0, %in" emit "mov %out.0, %in"
emit "sra %out.1, %in, 31" emit "sra %out.1, %in, 31"
cost 8; cost 8;
@ -272,16 +380,16 @@ PATTERNS
cost 8; cost 8;
out:(lret)reg = FROMIPAIR.L(in1:(int)reg, in2:(int)reg) out:(lret)reg = FROMIPAIR.L(in1:(int)reg, in2:(int)reg)
emit "move %out.0, %in1" emit "mov %out.0, %in1"
emit "move %out.1, %in2" emit "mov %out.1, %in2"
cost 8; cost 8;
out:(int)reg = FROML0.I(in:(long)reg) out:(int)reg = FROML0.I(in:(long)reg)
emit "move %out, %in.0" emit "mov %out, %in.0"
cost 4; cost 4;
out:(int)reg = FROML1.I(in:(long)reg) out:(int)reg = FROML1.I(in:(long)reg)
emit "move %out, %in.1" emit "mov %out, %in.1"
cost 4; cost 4;
@ -419,7 +527,7 @@ PATTERNS
out:(int)reg = COMPARESI.I(left:(int)reg, right:(int)reg) out:(int)reg = COMPARESI.I(left:(int)reg, right:(int)reg)
emit "slt at, %left, %right" emit "slt at, %left, %right"
emit "bne at, zero, 1f" emit "bne at, zero, 1f"
emit "li %out, -1" emit "li %out, -1" /* delay slot */
emit "slt %out, %right, %left" emit "slt %out, %right, %left"
emit "1:" emit "1:"
cost 20; cost 20;
@ -427,17 +535,26 @@ PATTERNS
out:(int)reg = COMPAREUI.I(left:(int)reg, right:(int)reg) out:(int)reg = COMPAREUI.I(left:(int)reg, right:(int)reg)
emit "sltu at, %left, %right" emit "sltu at, %left, %right"
emit "bne at, zero, 1f" emit "bne at, zero, 1f"
emit "li %out, -1" emit "li %out, -1" /* delay slot */
emit "sltu %out, %right, %left" emit "sltu %out, %right, %left"
emit "1:" emit "1:"
cost 20; cost 20;
out:(int)reg = COMPARED.I(left:(double)reg, right:(double)reg)
emit "c.lt.d 0, %left, %right"
emit "bc1t 0, 1f"
emit "li %out, -1" /* delay slot */
emit "c.lt.d 0, %right, %left"
emit "li %out, 1"
emit "movf %out, zero, 0"
cost 28;
/* Booleans */ /* Booleans */
/* If 0 then 1, else 0 */ /* If 0 then 1, else 0 */
out:(int)reg = IFEQ.I(in:(int)reg) out:(int)reg = IFEQ.I(in:(int)reg)
emit "sleu %out, %in, zero" emit "sleu %out, %in, zero"
cost 4;; cost 4;
/* If -1 then 1, else 0 */ /* If -1 then 1, else 0 */
out:(int)reg = IFLT.I(in:(int)reg) out:(int)reg = IFLT.I(in:(int)reg)
@ -557,10 +674,55 @@ PATTERNS
emit "li %out, $value" emit "li %out, $value"
cost 4; cost 4;
out:(zero)reg = value:CONST.I
when specific_constant(%value, 0)
cost 1;
/* FPU operations */
/* Doubles */
out:(double)reg = ADDF.D(left:(double)reg, right:(double)reg)
emit "add.d %out, %left, %right"
cost 4;
out:(double)reg = SUBF.D(left:(double)reg, right:(double)reg)
emit "sub.d %out, %left, %right"
cost 4;
out:(double)reg = MULF.D(left:(double)reg, right:(double)reg)
emit "mul.d %out, %left, %right"
cost 4;
out:(double)reg = DIVF.D(left:(double)reg, right:(double)reg)
emit "div.d %out, %left, %right"
cost 4;
out:(double)reg = FROMSI.D(in:(int)reg)
emit "mtc1 %out, %in"
emit "cvt.d.w %out, %out"
cost 4;
/* Floats */
out:(float)reg = ADDF.F(left:(float)reg, right:(float)reg)
emit "add.d %out, %left, %right"
cost 4;
out:(float)reg = SUBF.F(left:(float)reg, right:(float)reg)
emit "sub.d %out, %left, %right"
cost 4;
out:(float)reg = MULF.F(left:(float)reg, right:(float)reg)
emit "mul.d %out, %left, %right"
cost 4;
out:(float)reg = DIVF.F(left:(float)reg, right:(float)reg)
emit "div.d %out, %left, %right"
cost 4;
out:(float)reg = FROMSI.F(in:(int)reg)
emit "mtc1 %out, %in"
emit "cvt.s.w %out, %out"
cost 4;
/* vim: set sw=4 ts=4 expandtab : */ /* vim: set sw=4 ts=4 expandtab : */