Reorder registers. Fix problem with ret 8.
Afterc5bb3be, ncg began to allocate regvars from r13 up. I reorder the regvars so ncg again allocates them from r31 down. I also reorder the other registers. This exposed a bug in my rule for ret 8. It was wrong if item %2 was in r3, because I moved %1 to r3 before %2 to r4. Fix it by adding back an individual register class for r3 (called REG3 here, GPR3 inc5bb3be). Also fix my typo in mach.c that made a syntax error in assembly.
This commit is contained in:
George Koehler
parent
23c365c939
commit
2c266c631a
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@ -226,7 +226,7 @@ f_regsave(void)
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for (reg = 31; reg >= 0; reg--)
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if (savedf[reg] >= 0)
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fprintf(codefile, "lfd f%rd, %ld(fp)\n",
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fprintf(codefile, "lfd f%d, %ld(fp)\n",
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reg, savedf[reg]);
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for (reg = 31; reg >= 0; reg--)
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@ -31,45 +31,51 @@ SL_OFFSET = 8 /* Offset of static link */
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PROPERTIES
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GPR /* any GPR */
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REG /* any allocatable GPR */
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FPR(8) /* any FPR */
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FREG(8) /* any allocatable FPR */
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FSREG /* any allocatable single-precision FPR */
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SPR /* any SPR */
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CR /* any CR */
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GPR /* general-purpose register */
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REG /* allocatable GPR */
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REG3 /* coercion to r3 */
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FPR(8) /* floating-point register */
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FREG(8) /* allocatable FPR */
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FSREG /* allocatable single-precision FPR */
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SPR /* special-purpose register */
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CR /* condition register */
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REGISTERS
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/* Reverse order to encourage ncg to allocate them from r31 down */
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/*
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* When ncg allocates regvars, it seems to start with the last
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* register in the first class. To encourage ncg to allocate
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* them from r31 down, we list them in one class as
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* r13, r14, ..., r31: GPR, REG regvar(reg_any).
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*/
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r31, r30, r29, r28, r27, r26,
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r25, r24, r23, r22, r21, r20,
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r19, r18, r17, r16, r15, r14,
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r13 : GPR, REG regvar(reg_any).
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r0, sp, fp : GPR.
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r3 : GPR, REG, REG3.
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r12, r11, r10, r9, r8, r7,
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r6, r5, r4, r3 : GPR, REG.
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r4, r5, r6, r7, r8, r9, r10, r11, r12
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: GPR, REG.
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fp, sp, r0 : GPR.
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f31, f30, f29, f28, f27, f26,
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f25, f24, f23, f22, f21, f20,
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f19, f18, f17, f16, f15, f14 : FPR, FREG regvar(reg_float).
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f13, f12, f11, f10, f9, f8
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f7, f6, f5, f4, f3, f2, f1 : FPR, FREG.
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r13, r14, r15, r16, r17, r18, r19, r20, r21, r22, r23, r24,
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r25, r26, r27, r28, r29, r30, r31
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: GPR, REG regvar(reg_any).
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f0 : FPR.
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fs13("f13")=f13, fs12("f12")=f12,
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fs11("f11")=f11, fs10("f10")=f10,
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fs9("f9")=f9, fs8("f8")=f8,
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fs7("f7")=f7, fs6("f6")=f6,
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fs5("f5")=f5, fs4("f4")=f4,
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fs3("f3")=f3, fs2("f2")=f2,
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fs1("f1")=f1 : FSREG.
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f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13
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: FPR, FREG.
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f14, f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25,
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f26, f27, f28, f29, f30, f31
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: FPR, FREG regvar(reg_float).
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fs1("f1")=f1, fs2("f2")=f2, fs3("f3")=f3, fs4("f4")=f4,
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fs5("f5")=f5, fs6("f6")=f6, fs7("f7")=f7, fs8("f8")=f8,
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fs9("f9")=f9, fs10("f10")=f10, fs11("f11")=f11, fs12("f12")=f12,
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fs13("f13")=f13
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: FSREG.
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lr, ctr : SPR.
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cr0 : CR.
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@ -970,10 +976,9 @@ PATTERNS
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los 4
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pat los $1==4 /* Load arbitrary size */
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with REG STACK
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with REG3 STACK
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kills ALL
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gen
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move %1, r3
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bl {LABEL, ".los4"}
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pat sti $1==INT8 /* Store byte indirect */
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@ -1063,10 +1068,9 @@ PATTERNS
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sts 4
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pat sts $1==4 /* Store arbitrary size */
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with REG STACK
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with REG3 STACK
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kills ALL
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gen
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move %1, r3
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bl {LABEL, ".sts4"}
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@ -1792,10 +1796,9 @@ PATTERNS
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yields r3
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pat lab topeltsize($1)==4 && fallthrough($1)
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with REG STACK
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with REG3 STACK
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kills ALL
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gen
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move %1, r3
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labeldef $1
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yields r3
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@ -1806,9 +1809,8 @@ PATTERNS
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labeldef $1
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pat bra topeltsize($1)==4 /* Unconditional jump with TOS GPRister */
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with REG STACK
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with REG3 STACK
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gen
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move %1, r3
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b {LABEL, $1}
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pat bra topeltsize($1)!=4 /* Unconditional jump without TOS GPRister */
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@ -1852,17 +1854,13 @@ PATTERNS
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blr.
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pat ret $1==4 /* Return from procedure, word */
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with REG
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gen move %1, r3
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with REG3
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leaving ret 0
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pat ret $1==8 /* Return from proc, double-word */
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with REG REG
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gen
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move %1, r3
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move %2, r4
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leaving
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ret 0
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with REG3 REG
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gen move %2, r4
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leaving ret 0
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pat blm /* Block move constant length */
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leaving
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@ -1920,10 +1918,9 @@ PATTERNS
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ste ".ignmask"
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pat trp /* Raise EM trap */
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with REG
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with REG3
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kills ALL
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gen
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move %1, r3
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bl {LABEL, ".trap"}
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pat sig /* Set trap handler */
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