added rcsid

man/a.out.5

@@ -1,3 +1,4 @@
+\" $Header$
 .TH A.OUT 5
 .SH NAME
 a.out \- universal assembler load format

man/arch.1

@@ -1,3 +1,4 @@
+\" $Header$
 .TH ARCH 1
 .SH NAME
 arch \- archive and library maintainer

man/arch.5

@@ -1,3 +1,4 @@
+\" $Header$
 .TH ARCH 5
 .SH NAME
 arch \- archive (library) file format

man/em.1

@@ -1,3 +1,4 @@
+\" $Header$
 .TH EM I
 .ad
 .SH NAME

man/em_cg.6

@@ -1,3 +1,4 @@
+\" $Header$
 .TH EM_CG VI
 .ad
 .SH NAME

man/em_decode.6

@@ -1,3 +1,4 @@
+\" $Header$
 .TH EM_DECODE VI
 .ad
 .SH NAME

man/eminform.1

@@ -1,3 +1,4 @@
+\" $Header$
 .tr ~
 .TH EMINFORM I
 .ad

man/i86_as.1

@@ -0,0 +1,140 @@
+\" $Header$
+.TH I86_AS 1
+.ad
+.SH NAME
+i86_as \- assembler for Intel 8086
+.SH SYNOPSIS
+/usr/em/lib/i86_as [options] argument ...
+.SH DESCRIPTION
+This assembler is made with the general framework
+described in \fIuni_ass\fP(6).
+.SH SYNTAX
+.IP segments
+An address on the Intel 8086 consists of two pieces:
+a segment number and an offset. A memory address is computed as
+the segment number shifted left 4 bits + the offset.
+Assembly language addresses only give the offset, with the exception of
+the address of an inter-segment jump or call (see `addressing modes' below).
+For each segment type (.org, .text, .data, or .bss) the segment number
+must be given with the .sbase pseudo-instruction.
+The syntax is:
+.br
+	.sbase <segment-id> expression
+.br
+with segment-id one of .org, .text, .data, or .bss.
+Example:
+.br
+	.sbase .text 0x1000
+
+.IP registers
+The Intel 8086 has the following 16-bit registers:
+.br
+Four general registers: ax (accumulator), bx (base), cx (count), and dx (data).
+The upper halves and lower halves of these registers are separately
+addressable as ah, bh, ch, dh, and al, bl, cl, dl respectively.
+.br
+Two pointer registers: sp (stack pointer) and bp (base pointer).
+.br
+Two index registers: si (source index) and di (destination index).
+.br
+Four segment registers: cs (code), ds (data), ss (stack), and es (extra).
+.IP "addressing modes"
+.nf
+.ta 8 16 24 32 40 48
+syntax		meaning
+
+expr		the value of `expr' is immediate data or
+		an address offset. There is no special
+		notation for immediate data.
+
+register	one of the aforementioned general registers
+		or their upper or lower halves, or one of the
+		four segment registers.
+
+(expr)		the value of expr is the address of the operand.
+
+(reg)
+expr (reg)	the value of `expr' (if present) + the contents of
+		`reg' (which must be a pointer or an index register)
+		is the address of the operand.
+
+(preg) (ireg)
+expr (preg) (ireg)
+		the value of `expr' (if present) + the contents of
+		`preg' (which must be a pointer register) + the
+		contents of `ireg' (which must be an index register)
+		is the address of the operand.
+
+The next addressing mode is only allowed with the instructions
+"callf" or "jmpf".
+
+expr : expr	the value of the first `expr' is a segment number,
+		the value of the second `expr' is an address offset.
+		The (absolute) address of the operand is computed
+		as described above.
+.fi
+
+.IP instructions
+Each time an address is computed the assembler decide which segment register
+to use. You can override the assembler's choice by prefixing the instruction
+with one of eseg, cseg, sseg, or dseg; these prefixes indicate that the
+assembler should choose es, cs, ss, or ds instead.
+.SH "SEE ALSO"
+uni_ass(6),
+ack(1),
+.br
+MCS-86 assembly language reference manual, 1978, Intel Corporation
+.SH EXAMPLE
+.nf
+.ta 8 16 24 32 40 48
+An example of Intel 8086 assembly language:
+
+	_panic:
+		push	bp
+		mov	bp,sp
+	.data
+	_35:
+	.word	24944
+	.word	26990
+	.word	14947
+	.word	32
+	.text
+	call _disable
+	mov ax,_35
+	push ax
+	call _str
+	pop si
+	push 4(bp)
+	call _str
+	pop si
+	call _nlcr
+	call _exit
+	mov sp,bp
+	pop bp
+	ret
+	.extern _nopanic
+	_nopanic:
+		push	bp
+		mov	bp,sp
+	.data
+	_38:
+	.word	28526
+	.word	24944
+	.word	26990
+	.word	14947
+	.word	32
+	.text
+	mov ax,_38
+	push ax
+	call _str
+	pop si
+	push 4(bp)
+	call _str
+	pop si
+	push 6(bp)
+	call _octal
+	pop si
+	mov sp,bp
+	pop bp
+	ret
+.fi

man/libmon.7

@@ -1,3 +1,4 @@
+\" $Header$
 .TH LIBMON VII
 .ad
 .SH NAME

man/libpc.7

@@ -1,3 +1,4 @@
+\" $Header$
 .TH LIBPC VII
 .ad
 .SH NAME

man/m68k2_as.1

@@ -0,0 +1,100 @@
+\" $Header$
+.TH M68K2_AS 1
+.ad
+.SH NAME
+m68k2_as \- assembler for Motorola 68000
+.SH SYNOPSIS
+/usr/em/lib/m68k2_as [options] argument ...
+.br
+/usr/em/lib/m68k4_as [options] argument ...
+.SH DESCRIPTION
+This assembler is made with the general framework
+described in \fIuni_ass\fP(6).
+.SH SYNTAX
+.IP registers
+The 68000 has the following registers:
+seven data-registers (d1 - d7), seven address-registers (a1 - a6, sp)
+of which sp is the system stack pointer, a program counter (pc),
+a status register (sr), and a condition codes register (ccr) which is actually
+just the low order byte of the status register.
+.IP "addressing modes"
+.nf
+.ta 8 16 24 32 40 48
+syntax		meaning (name)
+
+reg		contents of `reg' is operand, where `reg' is
+		one of the registers mentioned above (register direct)
+
+(areg)		contents of `areg' is address of operand, where
+		`areg' is an address-register
+		(address register indirect)
+
+(areg)+		same as (areg), but after the address is used,
+		`areg' is incremented by the operand length
+		(postincrement)
+
+-(areg)		same as (areg), but before the address is used,
+		`areg' is decremented by the operand length
+		(predecrement)
+
+expr(areg)
+expr(pc)	`expr' + the contents of the register yields the
+		address of the operand (displacement)
+
+expr(areg, ireg)
+expr(pc, ireg)	`expr' + the contents of the register + the contents
+		of `ireg' yields the address of the operand. `ireg' is
+		an address- or a data-register.
+		`ireg' may be followed by .w or .l indicating whether
+		the size of the index is a word or a long
+		(displacement with index)
+
+expr		`expr' is the address of the operand
+		(absolute address)
+
+#expr		`expr' is the operand (immediate)
+.fi
+
+Some instructions have as operand a register list. This list consists of 
+one or more ranges of registers separated by '/'s. A register range consists
+of either one register (e.g. d3) or two registers separated by a '-'
+(e.g. a2-a4, or d4-d5). The two registers must be in the same set (address-
+or data-registers) and the first must have a lower number than the second.
+.IP instructions
+Some instructions can have a byte, word, or longword operand.
+This may be indicated by prepending the mnemonic with .b, .w, or .l
+respectively. Default is .w.
+.SH "SEE ALSO"
+uni_ass(6),
+ack(1),
+.br
+MC68000 16-bit microprocessor User's manual, Motorola Inc, 1979 
+.SH EXAMPLE
+.sp 2
+.nf
+.ta 8 16 24 32 40 48 56 64
+	.define	.cii
+	
+		.text
+	.cii:
+		movem.l	a0/d0/d1,.savreg
+		move.l	(sp)+,a0	! return address
+		move	(sp)+,d0	! destination size
+		sub	(sp)+,d0	! destination - source size
+		bgt	1f
+		sub	d0,sp		! pop extra bytes
+		bra	3f
+	1:
+		move	(sp),d1
+		ext.l	d1
+		swap	d1
+		asr	#1,d0
+	2:
+		move.w	d1,-(sp)
+		sub	#1,d0
+		bgt	2b
+	3:
+		move.l	a0,-(sp)
+		movem.l	.savreg,a0/d0/d1
+		rts
+.fi

man/macro.v7

@@ -1,3 +1,4 @@
+\" $Header$
 .de TH
 .PD
 .lc

man/pc_prlib.7

@@ -1,3 +1,4 @@
+\" $Header$
 .TH PC_PRLIB VII
 .ad
 .SH NAME

man/pdp_as.1

@@ -0,0 +1,138 @@
+\" $Header$
+.TH PDP_AS 1
+.ad
+.SH NAME
+pdp_as \- assembler for PDP 11
+.SH SYNOPSIS
+/usr/em/lib/pdp_as [options] argument ...
+.SH DESCRIPTION
+This assembler is made with the general framework
+described in \fIuni_ass\fP(6).
+.SH SYNTAX
+.IP registers
+The pdp11 has seven general registers, numbered r0 through r7. 
+Of these, r6 is the stack pointer and can also be referenced to by `sp',
+r7 is the program counter and has `pc' as synonym. There are also six
+floating-point registers fr0 through fr5, but the names r0 through r5 can
+also be used. From the context will be derived what kind of register is meant.
+.IP "addressing modes"
+.nf
+.ta 8 16 24 32 40 48
+syntax		meaning (name)
+
+reg		contents of register reg is operand.
+		(register)
+
+(reg)		contents of reg is address of operand.
+		(register deferred)
+
+(reg)+		as (reg), but after the operand is fetched
+		the contents of reg is incremented by the
+		size of the operand. (auto-increment)
+
+*(reg)+		contents of reg points to address of the operand.
+		after the operand is fetched, reg is incremented
+		by two. (auto-increment deferred)
+
+-(reg)		as (reg), but before the operand is fetched
+		the contents of reg is decremented by the
+		size of the operand. (auto-decrement)
+
+*-(reg)		before the operand is fetched, reg is decremented
+		by two. then the contents of reg points to the
+		address of the operand. (auto-decrement deferred)
+
+expr(reg)	value of expr + contents of reg yields address
+		of operand. (index)
+
+*expr(reg)	value of expr + contents of reg yields pointer
+		to address of operand. (index deferred)
+
+$expr		the value of expr is the operand. (immediate)
+
+*$expr		the value of expr is the address of the operand.
+		(absolute)
+
+expr		expr is address of operand. (relative)
+
+*expr		expr points to the address of the operand.
+		(relative deferred)
+
+.fi
+.IP "condition code instructions"
+Two or more of the "clear" instructions (clc, cln, clv, clz), or
+two or more of the "set" instructions (sec, sen, sev, sez) may be
+or-ed together with `|' to yield a instruction that clears or sets two or more
+of the condition-bits. Scc and ccc are not predefined.
+.IP "extended branches"
+The assembler recognizes conditional branches with a "j" substituted for
+the "b". When the target is too remote for a simple branch, a converse branch
+over a jmp to the target is generated. Likewise jbr assembles into either br
+or jmp.
+.IP "floating-point instructions"
+The names of several floating-point instructions differ from the names
+in the handbook mentioned below. Synonyms ending in "d" for instructions ending
+in "f" are not recognized. Some instructions have different names; the mapping
+is as below.
+.nf
+.ta 8 16 24 32 40 48
+
+handbook		pdp_as
+
+ldcif, ldclf,
+ldcid, ldcld		movif
+
+stcfi, stcfl,
+stcdi, stcdl		movfi
+
+ldcdf, ldcfd		movof
+
+stcdf, stcfd		movfo
+
+ldexp			movie
+
+stexp			movei
+
+ldd, ldf		movf
+
+std, stf		movf
+
+.fi
+The movf instruction assembles into stf, when the first operand is one of the
+first three floating-point registers, otherwise it assembles into ldf.
+.IP sys
+This instruction is synonymous with trap.
+.SH EXAMPLE
+An example of pdp11 assembly code.
+.nf
+.ta 8 16 24 32 40 48
+
+!this is the routine that reads numbers into r0
+!the number is terminated by any non digit
+!the non digit is left in r1
+innum:	clr r3		!r3 will accumulate the number
+inloop:	jsr pc,_getchar	!read a character into r0
+	cmp r0,$0121	!is it a Q?
+	jeq quit
+	cmp r0,$48	!is the character a digit? 
+	jlt indone	!digits 0-9 have codes 060-071 octal
+	cmp r0,$56
+	jgt indone
+	mul $10,r3	!r3 = 10 * r3
+	sub $48,r3	!convert ascii code to numerical value
+	add r0,r3	!r3 = old sum * 10 + new digi
+	jbr inloop
+
+indone:	mov r0,r1	!put the first non digit into r1
+	mov r3,r0	!put the number read into r0
+	rts pc		!return to caller
+
+.fi
+.SH "SEE ALSO"
+uni_ass(6),
+ack(1),
+.br
+PDP11/60 processor handbook, Digital Equipment Corporation, 1977
+.SH BUGS
+You cannot use *reg in place of (reg). Likewise *(reg) is not understood as
+*0(reg).

man/z80_as.1

@@ -0,0 +1,66 @@
+\" $Header$
+.TH z80_AS 1
+.ad
+.SH NAME
+z80_as \- assembler for Zilog z80
+.SH SYNOPSIS
+/usr/em/lib/z80_as [options] argument ...
+.SH DESCRIPTION
+This assembler is made with the general framework
+described in \fIuni_ass\fP(6).
+.SH SYNTAX
+.IP registers
+The z80 has six general-purpose 8-bit registers: b, c, d, e, h, l;
+an 8-bit accumulator: a; an 8-bit flag register: f; an 8-bit interrupt
+vector: i; an 8-bit memory refresh register: r; two 16-bit index registers:
+ix, iy; a 16-bit stack pointer: sp; and a 16-bit program counter: pc.
+The general-purpose registers can be paired to form three registers pairs of
+16 bits each: bc, de, hl.
+An alternate set of registers is provided that duplicates the accumulator,
+the flag register, and the general-purpose registers. The "exx"-instruction
+exchanges the contents of the two sets of general-purpose registers; the
+contents of the accumulator and flag register can be exchanged with the contents
+of their alternates by the "ex af, af2"-instruction.
+.IP "addressing modes"
+.nf
+.ta 8 16 24 32 40 48
+syntax		meaning
+
+expr		dependent on the instruction, the
+		value of `expr' can be immediate
+		data or the address of the operand.
+		There is no special notation for
+		immediate data.
+
+(ireg + expr)
+(ireg - expr)	the contents of ireg (which must be
+		one of the index-registers) + or -
+		the - one byte - value of `expr'
+		yield the address of the operand.
+
+(expr)		the value of `expr' is the address of
+		the operand.
+
+reg		the contents of `reg' - one of the above-
+		mentioned registers - is the operand.
+
+(reg)		the contents of `reg' - one of the 16-bit
+		registers except pc - is the address of
+		the operand.
+
+nz, z, nc, c,
+po, pe, p, m	the letters indicate a condition-code:
+		nonzero, zero, carry, no carry,
+		parity odd, parity even, sign positive,
+		sign negative respectively. Used by conditional
+		jump, call, and return instructions.
+
+.fi
+.IP instructions
+The jr-instruction will automatically be replaced by a jp-instruction if the
+target is too remote.
+.SH "SEE ALSO"
+uni_ass(6),
+ack(1),
+.br
+Z80 Users Manual, Joseph J. Carr, Reston Publishing Company, 1980

util/ack/ack.1.X

@@ -1,3 +1,4 @@
+\" $Header$
 .TH ACK I
 .ad
 .SH NAME

util/ass/em_ass.6

@@ -1,3 +1,4 @@
+\" $Header$
 .TH EM_ASS VI
 .ad
 .SH NAME

util/misc/em_decode.6

@@ -1,3 +1,4 @@
+\" $Header$
 .TH EM_DECODE VI
 .ad
 .SH NAME

util/opt/em_opt.6

@@ -1,3 +1,4 @@
+\" $Header$
 .TH EM_OPT VI
 .ad
 .SH NAME