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fixes from Nigel Hall

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This commit is contained in:
ceriel 1988-03-09 18:07:05 +00:00
parent 41007486bf
commit 304f03a836
2 changed files with 197 additions and 156 deletions
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3
mach/ns/ncg/mach.h
View file

@ -9,8 +9,9 @@
#define newilb(x) fprintf(codefile,"%s:\n",x) #define newilb(x) fprintf(codefile,"%s:\n",x)
#define newdlb(x) fprintf(codefile,"%s:\n",x) #define newdlb(x) fprintf(codefile,"%s:\n",x)
#define newplb(x) fprintf(codefile,".align 2\n%s:\n",x)
#define dlbdlb(x,y) fprintf(codefile,"%s = %s\n",x,y) #define dlbdlb(x,y) fprintf(codefile,"%s = %s\n",x,y)
#define newlbss(l,x) fprintf(codefile,"%s:.space\t%ld\n",l,x); #define newlbss(l,x) fprintf(codefile,".comm\t%s,%ld\n",l,x)
#define cst_fmt "%ld" #define cst_fmt "%ld"
#define off_fmt "%ld" #define off_fmt "%ld"

188
mach/ns/ncg/table
View file

@ -7,8 +7,23 @@ rcsid = "$Header$"
* * * *
* Author: Annita Wilschut. * * Author: Annita Wilschut. *
* * * *
* Corrections: Nigel Hall *
* *
*****************************************************************/ *****************************************************************/
/* The handling of arrays was not complete. Tables extended
* in order to handle access to other lexical levels between
* local and global. Corrections to ordering of tokens made.
*
* The token length was added to cope with the length field
* of MOVMi instructions. The lengths adjusted by division by 4.
*
* The compare procedures did not return a result. Caused
* an extra word to be popped off the stack. The "cmi txx ior" &
* "txx and" sequences needed their branch criterion inverting.
*
*/
/* /*
* Deze tabel implementeert, naast gewone, ook floating point * Deze tabel implementeert, naast gewone, ook floating point
* instructies. Bij gebrek aan een floating point processor * instructies. Bij gebrek aan een floating point processor
@ -16,7 +31,7 @@ rcsid = "$Header$"
* getest. Wanneer NOFLOAT "aan" is worden er zeker geen * getest. Wanneer NOFLOAT "aan" is worden er zeker geen
* floating point instructies gegenereerd. Na verwijdering van * floating point instructies gegenereerd. Na verwijdering van
* alle ifdef's worden er bij de vertaling van een programma dat * alle ifdef's worden er bij de vertaling van een programma dat
* geen floating point gebruikt, hoogst waarschhijnlijk ook * geen floating point gebruikt, hoogst waarschijnlijk ook
* geen floating point instructies gegenereerd. Dit is echter niet * geen floating point instructies gegenereerd. Dit is echter niet
* uitgebreid getest. * uitgebreid getest.
*/ */
@ -38,6 +53,7 @@ PROGRAMCOUNTER
STACKPOINTER STACKPOINTER
STATICBASE STATICBASE
LOCALBASE LOCALBASE
PROCREG /* processor register - used by LPRi & SPRi */
REGISTERS REGISTERS
@ -50,10 +66,10 @@ f23("f2")=f2+f3,
f45("f4")=f4+f5, f45("f4")=f4+f5,
f67("f6")=f6+f7 : DFREG. f67("f6")=f6+f7 : DFREG.
r01("r0")=r0+r1,r23("r2")=r2+r3 : REGPAIR. r01("r0")=r0+r1,r23("r2")=r2+r3 : REGPAIR.
sp : STACKPOINTER, MEMREG. sp : STACKPOINTER, MEMREG, PROCREG.
pc : PROGRAMCOUNTER. pc : PROGRAMCOUNTER.
fp : LOCALBASE, MEMREG. fp : LOCALBASE, MEMREG, PROCREG.
sb : STATICBASE, MEMREG. sb : STATICBASE, MEMREG, PROCREG.
TOKENS TOKENS
@ -94,6 +110,8 @@ memregrelcon4 = { MEMREG reg; ADDR disp1; ADDR disp2;} 4 .
label = {ADDR disp; } 4 disp . label = {ADDR disp; } 4 disp .
regrelsid = {INT ind; REG reg1; REG reg2; } 4 ind "(" reg1
")[" reg2 ":d]" .
memregrelsid = {INT ind; MEMREG reg1; REG reg2; } 4 ind "(" reg1 memregrelsid = {INT ind; MEMREG reg1; REG reg2; } 4 ind "(" reg1
")[" reg2 ":d]" . ")[" reg2 ":d]" .
abssid = {ADDR disp; REG reg; } 4 "@" disp "[" reg ":d]" . abssid = {ADDR disp; REG reg; } 4 "@" disp "[" reg ":d]" .
@ -107,7 +125,7 @@ SETS
src1 = regrel1 + memregrel1 + memrel1 + absolute1 . src1 = regrel1 + memregrel1 + memrel1 + absolute1 .
src2 = regrel2 + memregrel2 + memrel2 + absolute2 . src2 = regrel2 + memregrel2 + memrel2 + absolute2 .
src4 = REG + const4 + LOCAL + regrel4 + memrel4 + src4 = REG + const4 + LOCAL + regrel4 + memrel4 +
memregrel4 + memregrelsid + abssid + absolute4 + memregrel4 + regrelsid + memregrelsid + abssid + absolute4 +
addr_external. addr_external.
con4 = regcon4 + memregcon4 + memregrelcon4 . con4 = regcon4 + memregcon4 + memregrelcon4 .
tossrc4 = TOS + src4 . tossrc4 = TOS + src4 .
@ -123,17 +141,17 @@ tosdst1 = TOS + dst1 .
dst2 = src2 . dst2 = src2 .
tosdst2 = TOS + dst2 . tosdst2 = TOS + dst2 .
dst4 = REG + LOCAL + regrel4 + memregrel4 + memrel4 + dst4 = REG + LOCAL + regrel4 + memregrel4 + memrel4 +
absolute4 + memregrelsid + abssid . absolute4 + regrelsid + memregrelsid + abssid .
tosdst4 = TOS + dst4 . tosdst4 = TOS + dst4 .
fdst4 = FREG + LOCAL + regrel4 + memregrel4 + memrel4 + fdst4 = FREG + LOCAL + regrel4 + memregrel4 + memrel4 +
absolute4 + memregrelsid + abssid . absolute4 + regrelsid + memregrelsid + abssid .
tosfdst4 = TOS + fdst4 . tosfdst4 = TOS + fdst4 .
fdst8 = fsrc8 . fdst8 = fsrc8 .
tosfdst8 = tosfsrc8 . tosfdst8 = tosfsrc8 .
regrel = regrel1 + regrel2 + regrel4 +regrel8 . regrel = regrel1 + regrel2 + regrel4 +regrel8 .
memregrel = memregrel1 + memregrel2 + memregrel4 +memregrel8 . memregrel = memregrel1 + memregrel2 + memregrel4 +memregrel8 .
memrel = memrel1 + memrel2 + memrel4 +memrel8 . memrel = memrel1 + memrel2 + memrel4 +memrel8 .
rel = regrel + memregrel + memrel + memregrelsid rel = regrel + memregrel + memrel + regrelsid + memregrelsid
+ fprelsid + sprelsid . + fprelsid + sprelsid .
absolute = absolute1 + absolute2 + absolute4 + absolute8 + abssid . absolute = absolute1 + absolute2 + absolute4 + absolute8 + abssid .
regs = REG + FREG + DFREG + MEMREG + REGPAIR . regs = REG + FREG + DFREG + MEMREG + REGPAIR .
@ -213,7 +231,7 @@ sfsd tosdst4:wo .
tbitd tossrc4:ro, tosdst4:ro . tbitd tossrc4:ro, tosdst4:ro .
cbitd tossrc4:ro, tosdst4:rw . cbitd tossrc4:ro, tosdst4:rw .
sbitd tossrc4:ro, tosdst4:rw . sbitd tossrc4:ro, tosdst4:rw .
movmd tosdst4:ro, tosdst4:rw, const4 . movmd tossrc4:ro, tosdst4:rw, const4 .
indexd REG, tossrc4:ro, tossrc4:ro . indexd REG, tossrc4:ro, tossrc4:ro .
brxx label . brxx label .
beq label . beq label .
@ -234,7 +252,8 @@ jsr tosdst4+label .
ret const4:ro . ret const4:ro .
adjspd tossrc4:ro . adjspd tossrc4:ro .
exit label . exit label .
sprd MEMREG:rw, tossrc4:ro . lprd PROCREG:rw, tossrc4:ro .
sprd PROCREG:ro, tossrc4:rw .
@ -1652,6 +1671,10 @@ with REG
leaving adi 2 leaving adi 2
pat lae aar $2==4 && rom($1,3)==4 && rom($1,1)==0 pat lae aar $2==4 && rom($1,3)==4 && rom($1,1)==0
with REG REG
uses REG
gen addr {regrelsid, 0, %2, %1}, %a
yields %a
with REG addr_local with REG addr_local
uses REG uses REG
gen addr {memregrelsid, %2.ind, fp, %1}, %a gen addr {memregrelsid, %2.ind, fp, %1}, %a
@ -1663,6 +1686,11 @@ uses REG
with leaving lae $1 aar $2 with leaving lae $1 aar $2
pat lae aar $2==4 && rom($1,3)==4 && rom($1,1)!=0 pat lae aar $2==4 && rom($1,3)==4 && rom($1,1)!=0
with REG REG
uses REG
gen subd {const4, rom($1,1)}, %1
addr {regrelsid, 0, %2, %1}, %a
yields %a
with REG addr_local with REG addr_local
uses REG uses REG
gen subd {const4, rom($1,1)}, %1 gen subd {const4, rom($1,1)}, %1
@ -1676,47 +1704,57 @@ uses REG
with leaving lae $1 aar $2 with leaving lae $1 aar $2
pat lae lar $2==4 && rom($1,3)==4 && rom($1,1)==0 pat lae lar $2==4 && rom($1,3)==4 && rom($1,1)==0
with REG REG yields {regrelsid, 0, %2, %1}
with REG addr_local yields {memregrelsid, %2.ind, fp, %1} with REG addr_local yields {memregrelsid, %2.ind, fp, %1}
with REG addr_external yields {abssid, %2.disp, %1} with REG addr_external yields {abssid, %2.disp, %1}
with leaving lae $1 lar $2 with leaving lae $1 lar $2
pat lae lar $2==4 && rom($1,3)==4 && rom($1,1)!=0 pat lae lar $2==4 && rom($1,3)==4 && rom($1,1)!=0
with REG REG
gen subd {const4, rom($1,1)}, %1 yields {regrelsid, 0, %2, %1}
with REG addr_local with REG addr_local
gen subd {const4, rom($1,1)}, %1 gen subd {const4, rom($1,1)}, %1 yields {memregrelsid, %2.ind, fp, %1}
yields {memregrelsid, %2.ind, fp, %1}
with REG addr_external with REG addr_external
gen subd {const4, rom($1,1)}, %1 gen subd {const4, rom($1,1)}, %1 yields {abssid, %2.disp, %1}
yields {abssid, %2.disp, %1}
with leaving lae $1 lar $2 with leaving lae $1 lar $2
pat lae sar $2==4 && rom($1,3)==4 && rom($1,1)==0 pat lae sar $2==4 && rom($1,3)==4 && rom($1,1)==0
with src4 REG addr_local with REG REG src4
kills allmincon kills allmincon
gen move %1, {memregrelsid, %3.ind, fp, %2} gen movd %3, {regrelsid, 0, %2, %1}
with src4 REG addr_external with REG addr_local src4
kills allmincon kills allmincon
gen move %1, {abssid, %3.disp, %2} gen move %3, {memregrelsid, %2.ind, fp, %1}
with REG addr_external src4
kills allmincon
gen move %3, {abssid, %2.disp, %1}
with leaving lae $1 sar $2 with leaving lae $1 sar $2
pat lae lar $2==4 && rom($1,3)==4 && rom($1,1)!=0 pat lae sar $2==4 && rom($1,3)==4 && rom($1,1)!=0
with src4 REG addr_local with REG REG src4
kills allmincon kills allmincon
gen subd {const4, rom($1,1)}, %2 gen subd {const4, rom($1,1)}, %1
move %1, {memregrelsid, %3.ind, fp, %2} movd %3, {regrelsid, 0, %2, %1}
with src4 REG addr_external with REG addr_local src4
kills allmincon kills allmincon
gen subd {const4, rom($1,1)}, %2 gen subd {const4, rom($1,1)}, %1
move %1, {abssid, %3.disp, %2} move %3, {memregrelsid, %2.ind, fp, %1}
with REG addr_external src4
kills allmincon
gen subd {const4, rom($1,1)}, %1
move %3, {abssid, %2.disp, %1}
with leaving lae $1 sar $2 with leaving lae $1 sar $2
pat lae aar $2==4 && rom($1,1)==0 pat lae aar $2==4 && rom($1,1)==0
with src4 REG with REG src4
gen indexd %2, {const4, rom($1,3)-1}, %1 yields %2 gen indexd %1, {const4, rom($1,3)-1}, %2
yields %1
pat lae aar $2==4 && rom($1,1)!=0 pat lae aar $2==4 && rom($1,1)!=0
with REG REG with REG src4
gen subd {const4,rom($1,1)}, %1 gen subd {const4, rom($1,1)}, %1
indexd %2, {const4, rom($1,3)-1}, %1 yields %2 indexd %1, {const4, rom($1,3)-1}, %2
yields %1
pat lae sar defined(rom($1,3)) pat lae sar defined(rom($1,3))
leaving lae $1 leaving lae $1
@ -1761,45 +1799,45 @@ gen jsr {absolute4, ".sar"}
proc cmitxxand proc cmitxxand
with src4 src4 REG with src4 src4 REG
gen cmpd %2, %1 gen cmpd %1, %2
brxx* {label, "1f"} brxx* {label, "1f"}
xord %3, %3 movqd {const4, 0}, %3
1: 1: yields %3
proc cmitxxior proc cmitxxior
with src4 src4 REG with src4 src4 REG
gen cmpd %2, %1 gen cmpd %1, %2
brxx* {label, "1f"} brxx* {label, "1f"}
sbitd {const4, 0}, %3 sbitd {const4, 0}, %3
1: 1: yields %3
proc txxand proc txxand
with src4 REG with src4 REG
gen cmpd {const4, 0}, %1 gen cmpqd {const4, 0}, %1
brxx* {label, "1f"} brxx* {label, "1f"}
xord %2, %2 movqd {const4, 0}, %2
1: 1: yields %2
proc txxior proc txxior
with src4 REG with src4 REG
gen cmpd {const4, 0}, %1 gen cmpqd {const4, 0}, %1
brxx* {label, "1f"} brxx* {label, "1f"}
sbitd {const4, 0}, %2 sbitd {const4, 0}, %2
1: 1: yields %2
pat cmi tlt and $1==4 && $3==4 call cmitxxand("blt") pat cmi tlt and $1==4 && $3==4 call cmitxxand("bgt")
pat cmi tle and $1==4 && $3==4 call cmitxxand("ble") pat cmi tle and $1==4 && $3==4 call cmitxxand("bge")
pat cmi teq and $1==4 && $3==4 call cmitxxand("beq") pat cmi teq and $1==4 && $3==4 call cmitxxand("beq")
pat cmi tne and $1==4 && $3==4 call cmitxxand("bne") pat cmi tne and $1==4 && $3==4 call cmitxxand("bne")
pat cmi tge and $1==4 && $3==4 call cmitxxand("bge") pat cmi tge and $1==4 && $3==4 call cmitxxand("ble")
pat cmi tgt and $1==4 && $3==4 call cmitxxand("bgt") pat cmi tgt and $1==4 && $3==4 call cmitxxand("blt")
pat cmi tlt ior $1==4 && $3==4 call cmitxxior("blt") pat cmi tlt ior $1==4 && $3==4 call cmitxxior("ble")
pat cmi tle ior $1==4 && $3==4 call cmitxxior("ble") pat cmi tle ior $1==4 && $3==4 call cmitxxior("blt")
pat cmi teq ior $1==4 && $3==4 call cmitxxior("beq") pat cmi teq ior $1==4 && $3==4 call cmitxxior("bne")
pat cmi tne ior $1==4 && $3==4 call cmitxxior("bne") pat cmi tne ior $1==4 && $3==4 call cmitxxior("beq")
pat cmi tge ior $1==4 && $3==4 call cmitxxior("bge") pat cmi tge ior $1==4 && $3==4 call cmitxxior("bgt")
pat cmi tgt ior $1==4 && $3==4 call cmitxxior("bgt") pat cmi tgt ior $1==4 && $3==4 call cmitxxior("bge")
pat tlt and $2==4 call txxand("bgt") pat tlt and $2==4 call txxand("bgt")
pat tle and $2==4 call txxand("bge") pat tle and $2==4 call txxand("bge")
@ -1808,12 +1846,12 @@ pat tne and $2==4 call txxand("bne")
pat tge and $2==4 call txxand("ble") pat tge and $2==4 call txxand("ble")
pat tgt and $2==4 call txxand("blt") pat tgt and $2==4 call txxand("blt")
pat tlt ior $2==4 call txxior("bgt") pat tlt ior $2==4 call txxior("ble")
pat tle ior $2==4 call txxior("bge") pat tle ior $2==4 call txxior("blt")
pat teq ior $2==4 call txxior("beq") pat teq ior $2==4 call txxior("bne")
pat tne ior $2==4 call txxior("bne") pat tne ior $2==4 call txxior("beq")
pat tge ior $2==4 call txxior("ble") pat tge ior $2==4 call txxior("bgt")
pat tgt ior $2==4 call txxior("blt") pat tgt ior $2==4 call txxior("bge")
pat cmi $1==4 pat cmi $1==4
with src4 REG with src4 REG
@ -1826,10 +1864,10 @@ uses REG = {const4, 0}
gen cmpf %1, %2 gen cmpf %1, %2
beq {label, "1f"} beq {label, "1f"}
bgt {label, "2f"} bgt {label, "2f"}
movd {const4, 1}, %a movqd {const4, 1}, %a
br {label, "1f"} br {label, "1f"}
2: 2:
movd {const4, 0-1}, %a movqd {const4, 0-1}, %a
1: yields %a 1: yields %a
pat cmf $1==8 pat cmf $1==8
@ -1838,10 +1876,10 @@ uses REG = {const4, 0}
gen cmpl %1, %2 gen cmpl %1, %2
beq {label, "1f"} beq {label, "1f"}
bgt {label, "2f"} bgt {label, "2f"}
movd {const4, 1}, %a movqd {const4, 1}, %a
br {label, "1f"} br {label, "1f"}
2: 2:
movd {const4, 0-1}, %a movqd {const4, 0-1}, %a
1: yields %a 1: yields %a
#else #else
@ -2053,26 +2091,26 @@ with const4 STACK
pat blm $1==0 pat blm $1==0
pat blm $1==4 pat blm $1==4
with REG REG with tosdst4 tossrc4
kills allmincon kills allmincon
gen move {regrel4, %2, 0}, {regrel4, %1, 0} gen movd %2, %1
pat blm $1>4 && $1<=16 pat blm $1>4 && $1<=16
with REG REG with REG REG
kills allmincon kills allmincon
gen movmd %2, %1, {const4, $1} gen movmd {regrel4, %2, 0}, {regrel4, %1, 0}, {const4, $1/4}
with exact addr_external addr_external with exact addr_external addr_external
kills allmincon kills allmincon
gen movmd {absolute4, %2.disp}, {absolute4, %1.disp}, {const4, $1} gen movmd {absolute4, %2.disp}, {absolute4, %1.disp}, {const4, $1/4}
with exact addr_external addr_local with exact addr_external addr_local
kills allmincon kills allmincon
gen movmd {LOCAL, %2.ind}, {absolute4, %1.disp}, {const4, $1} gen movmd {LOCAL, %2.ind}, {absolute4, %1.disp}, {const4, $1/4}
with exact addr_local addr_external with exact addr_local addr_external
kills allmincon kills allmincon
gen movmd {absolute4, %2.disp}, {LOCAL, %1.ind}, {const4, $1} gen movmd {absolute4, %2.disp}, {LOCAL, %1.ind}, {const4, $1/4}
with exact addr_local addr_local with exact addr_local addr_local
kills allmincon kills allmincon
gen movmd {LOCAL, %2.ind}, {LOCAL, %1.ind}, {const4, $1} gen movmd {LOCAL, %2.ind}, {LOCAL, %1.ind}, {const4, $1/4}
pat blm $1>16 pat blm $1>16
with REG REG with REG REG
@ -2201,21 +2239,23 @@ uses REG
pat sim pat sim
with src24 with src24
kills ALL
gen movw %1, {absolute2, ".ignmask"} gen movw %1, {absolute2, ".ignmask"}
pat str $1==0 pat str $1==0
with src4 with src4 STACK
kills ALL gen lprd fp, %1
gen sprd fp, %1
pat str $1==1 pat str $1==1
with src4 with src4 STACK
kills ALL gen lprd sp, %1
gen sprd sp, %1
pat str $1==2 pat str $1==2
with src4 with src4
gen move %1, {absolute4, ".reghp"} kills ALL
gen movd %1, {TOS}
jsr {absolute4, ".strhp"}
adjspd {const4, 0-4}
pat trp pat trp
kills ALL kills ALL