Latest version from Albert Koelmans
This commit is contained in:
ceriel
parent
8a00e32bc8
commit
33dc73d4c4
6 changed files with 394 additions and 132 deletions
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@ -1,12 +1,13 @@
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/* $Header; mach0.c, v1.1 20-Oct-88 AJM */
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/* $Header; mach0.c, v1.2 06-Mar-89 AJM */
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#define LISTING
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#define ASLD
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#define THREE_PASS
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#define DEBUG 0
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/*
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#define WORDS_REVERSED
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#define BYTES_REVERSED
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*/
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#undef valu_t
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#define valu_t long
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@ -44,4 +45,6 @@
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#define CMP 0x01500000
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#define TEQ 0x01300000
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#define TST 0x01100000
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#define LDR 0x04100000
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#define STR 0x04000000
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@ -1 +1,3 @@
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/* $Header; mach1.c, v1.1 06-Mar-89 AJM */
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extern word_t opcode;
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extern int success; /* LDR/STR address failure flag */
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@ -1,4 +1,4 @@
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/* $Header: mach2.c, V1.3 2-Nov-88 AJM */
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/* $Header: mach2.c, V1.4 15-Mar-89 AJM */
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%token <y_word> COND
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%token <y_word> LINK
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%token <y_word> BRANCH
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@ -20,5 +20,5 @@
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%token <y_word> MLA
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%type <y_word> optlink optcond opts optt optp optb optexc reglist rlist
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%type <y_word> optsign optpsr optshift shftcnt address offset
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%type <y_word> optsign optpsr optshift shftcnt address offset aoptshift
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%type <y_expr> operand
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@ -1,4 +1,4 @@
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/* $Header: mach3.c, v1.5 2-Nov-88 AJM */
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/* $Header: mach3.c, v2.0 23-Feb-89 AJM */
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0, COND, 0x00000000, ".EQ",
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0, COND, 0x10000000, ".NE",
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@ -77,6 +77,7 @@
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0, REG, 13, "R13",
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0, REG, 14, "R14",
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0, REG, 15, "R15",
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0, REG, 15, "PC",
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0, SHIFT, 0x00000000, "LSL",
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0, SHIFT, 0x00000000, "ASL",
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@ -97,10 +98,10 @@
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0, BDT, 0x08100000, "LDMDA",
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0, BDT, 0x09900000, "LDMIB",
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0, BDT, 0x08900000, "LDMIA",
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0, BDT, 0x08100000, "LDMFD",
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0, BDT, 0x08900000, "LDMFA",
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0, BDT, 0x09100000, "LDMED",
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0, BDT, 0x09900000, "LDMEA",
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0, BDT, 0x08900000, "LDMFD",
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0, BDT, 0x08100000, "LDMFA",
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0, BDT, 0x09900000, "LDMED",
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0, BDT, 0x09100000, "LDMEA",
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0, BDT, 0x09000000, "STMDB",
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0, BDT, 0x08000000, "STMDA",
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0, BDT, 0x09800000, "STMIB",
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@ -112,7 +113,7 @@
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0, SWI, 0x0F000000, "SWI",
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0, ADR, 0, "ADR",
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0, ADR, 0x00000000, "ADR",
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0, MUL, 0x00000090, "MUL",
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0, MLA, 0x00200090, "MLA",
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@ -1,4 +1,4 @@
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/* $Header: mach4.c, v1.5 2-Nov-88 AJM */
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/* $Header: mach4.c, v1.9 15-Mar-89 AJM */
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operation : BRANCH optlink expr
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{branch($1, $2, $3.val);}
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@ -9,13 +9,13 @@ operation : BRANCH optlink expr
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| DATA3 optcond opts optp REG ',' operand
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{data($1,$2|$3|$4|$5<<16,$7.val,$7.typ);}
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| SDT optcond optb optt REG ',' address
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{emit4($1|$2|$3|$4|$5<<12|$7);}
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{strldr($1,$2|$3|$4|$5<<12,$7);}
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| BDT optcond REG optexc ',' reglist optpsr
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{emit4($1|$2|$3<<16|$4|$6|$7);}
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| SWI optcond expr
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{emit4($1|$2|$3.val);}
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| ADR optcond REG ',' expr
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{calcadr($2, $3, $5.val, $5.typ);}
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{calcadr($2,$3,$5.val,$5.typ);}
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| MUL optcond REG ',' REG ',' REG
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{emit4($1|$2|$3<<16|$5|$7<<8);}
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| MLA optcond REG ',' REG ',' REG ',' REG
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@ -76,6 +76,14 @@ optshift : ',' SHIFT shftcnt
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{$$ = 0;}
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;
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aoptshift : ',' SHIFT '#' expr
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{$$ = $2|calcshft($4.val, $4.typ, $<y_word>0);}
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| ',' RRX
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{$$ = $2;}
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{$$ = 0;}
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;
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shftcnt : '#' expr
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{$$ = calcshft($2.val, $2.typ, $<y_word>0);}
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| REG
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@ -83,18 +91,18 @@ shftcnt : '#' expr
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;
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address : expr
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{$$ = 0x01000000|calcaddress($1.val,$1.typ,$<y_word>-1);}
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{success = 0; $$ = $1.val;}
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| '[' REG ']'
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{$$ = 0x01000000|$2<<16;}
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{success = 1; $$ = 0x01000000|$2<<16;}
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| '[' REG ',' offset ']' optexc
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{$$ = $2<<16|$4|$6|0x01000000;}
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{success = 1; $$ = $2<<16|$4|$6|0x01000000;}
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| '[' REG ']' ',' offset
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{$$ = $2<<16|$5;}
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{success = 1; $$ = $2<<16|$5;}
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;
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offset : '#' expr
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{$$ = calcoffset($2.val);}
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| optsign REG optshift
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| optsign REG aoptshift
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{$$ = 0x02000000|$1|$2|$3;}
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;
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@ -113,4 +121,9 @@ rlist : REG
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{$$ = 1<<$1;}
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| rlist ',' REG
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{$$ = $1|1<<$3;}
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| REG '-' REG
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{
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for ($$ = 0; $1 <= $3; $1++)
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$$ |= (1<<$1);
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}
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;
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@ -1,4 +1,4 @@
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/* $Header: mach5.c, v1.6 3-Nov-88 AJM */
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/* $Header: mach5.c, v3.3 25-Apr-89 AJM */
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branch(brtyp, link, val)
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word_t brtyp;
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@ -7,7 +7,7 @@ valu_t val;
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{
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valu_t offset;
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offset = val - DOTVAL - 8;
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offset = val - DOTVAL - 8; /* Allow for pipeline */
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if ((offset & 0xFC000000) != 0 && (offset & 0xFC000000) != 0xFC000000){
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serror("offset out of range");
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}
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@ -22,16 +22,31 @@ valu_t val;
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short typ;
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{
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valu_t tmpval;
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int adrflag = 0;
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if (typ == S_REG){
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if (typ == S_REG){ /* The argument is a register */
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emit4(opc|ins|val);
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return;
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}
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ins |= 0x02000000;
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/* Do a bit of optimisation here, since the backend might produce instructions
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of the type MOV R0, R0, #0. We can ignore these. */
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if (((opc == ADD) || (opc == SUB)) && (val == 0)){ /* ADD or SUB 0 ? */
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if ((ins & 0x000F0000) == ((ins & 0x0000F000) << 4)) /* Same reg ? */
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return; /* Don't emit anything */
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}
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/* No optimisation, so carry on ... */
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ins |= 0x02000000; /* The argument is an immediate value */
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tmpval = val;
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if (typ == S_ABS){
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if (opc == 0xff){ /* This is an ADR */
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adrflag = 1;
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opc = MOV;
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}
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if (typ == S_ABS){ /* An absolute value */
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if (calcimm(&opc, &tmpval, typ)){
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emit4(opc|ins|tmpval);
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return;
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@ -39,50 +54,44 @@ short typ;
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}
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tmpval = val;
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if (small(calcimm(&opc, &tmpval, typ),12)){
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if (!adrflag){ /* Don't do this for ADRs */
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if (oursmall(calcimm(&opc, &tmpval, typ), 12)){
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emit4(opc|ins|tmpval);
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return;
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}
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}
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if (opc == MOV && typ != S_ABS)
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{
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if (small((val & 0xF0000000) == 0xF0000000, 8)){
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emit4(0xE51F0004 | (ins & 0xF000));
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emit4(val);
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if (opc == MOV || opc == MVN || opc == ADD || opc == SUB){
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if (!bflag && pass == PASS_3){ /* Debugging info */
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/* warning("MOV/ADD extension"); */
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/* if (dflag)
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printf("value: %lx\n", val);*/
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}
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if (oursmall((val & 0xFFFF0000) == 0, 8)){
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putaddr(opc, ins, val, 2);
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return;
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}
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if (small(1,4)){
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emit4(0xE51F0000 | (ins & 0xF000));
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emit4(0xEA000000);
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emit4(val);
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if (oursmall((val & 0xFF000000) == 0, 4)){
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putaddr(opc, ins, val, 3);
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return;
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}
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DOTVAL += 16;
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putaddr(opc, ins, val, 4);
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return;
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}
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if (opc == ADD && typ != S_ABS)
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{
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if (small((val & 0xF0000000) == 0xF0000000, 4)){
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emit4(0xE51F0004 | (ins & 0xF000));
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emit4(val);
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emit4(0xE2800000 | (ins&0xFF000) | (ins&0xF000)>>12);
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return;
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}
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emit4(0xE51F0000 | (ins & 0xF000));
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emit4(0xEA000000);
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emit4(val);
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emit4(0xE2800000 | (ins&0xFF000) | (ins&0xF000)>>12);
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return;
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}
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/* default: */
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if (pass == PASS_1)
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DOTVAL += 16;
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DOTVAL += 16; /* Worst case we can emit */
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else
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serror("immediate value out of range");
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return;
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}
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/* Calculate an immediate value. This is not as easy as it sounds, because
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the ARM uses an 8-bit value and 4-bit shift to encode the value into a
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12-bit field. Unfortunately this means that some numbers may not fit at
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all. */
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calcimm(opc,val,typ)
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word_t *opc;
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valu_t *val;
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@ -90,78 +99,83 @@ short typ;
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{
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int i = 0;
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if (typ == S_UND) return 0;
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if (typ == S_UND)
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return(0); /* Can't do anything with an undefined label */
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if ((*val & 0xFFFFFF00) == 0) return 1;
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if ((*val & 0xFFFFFF00) == 0) /* Value is positive, but < 256, */
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return(1); /* so doesn't need a shift */
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if ((~*val & 0xFFFFFF00) == 0){
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if (*opc == AND)
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{
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if ((~*val & 0xFFFFFF00) == 0){ /* Value is negative, but < 256, */
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if (*opc == AND) /* so no shift required, only */
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{ /* inversion */
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*val = ~*val;
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*opc = BIC;
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return 1;
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return(1);
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}
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if (*opc == MOV)
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{
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*val = ~*val;
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*opc = MVN;
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return 1;
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return(1);
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}
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if (*opc == ADC)
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{
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*val = ~*val;
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*opc = SBC;
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return 1;
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return(1);
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}
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}
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if ((-1**val & 0xFFFFFF00) == 0 ){
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if ((-1**val & 0xFFFFFF00) == 0){ /* Same idea ... */
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if (*opc == ADD)
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{
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*val *= -1;
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*opc = SUB;
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return 1;
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return(1);
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}
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if (*opc == CMP)
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{
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*val *= -1;
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*opc = CMN;
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return 1;
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return(1);
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}
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}
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do{
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rotateleft2(&*val);
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do{ /* Now we need to shift */
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rotateleft2(&*val); /* Rotate left by two bits */
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i++;
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if((*val & 0xFFFFFF00) == 0){
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*val = *val|i<<8;
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return 1;
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if((*val & 0xFFFFFF00) == 0){ /* Got a value < 256 */
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*val = *val|i<<8; /* OR in the shift */
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return(1);
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}
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if ((~*val & 0xFFFFFF00) == 0){
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if (*opc == AND)
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if ((~*val & 0xFFFFFF00) == 0){ /* If negative, carry out */
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if (*opc == AND) /* inversion as before */
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{
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*val = ~*val|i<<8;
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*opc = BIC;
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return 1;
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return(1);
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}
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if (*opc == MOV)
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{
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*val = ~*val|i<<8;
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*opc = MVN;
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return 1;
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return(1);
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}
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if (*opc == ADC)
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{
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*val = ~*val|i<<8;
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*opc = SBC;
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return 1;
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return(1);
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}
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}
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}while(i<15);
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return 0;
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return(0); /* Failed if can't encode it after 16 rotates */
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}
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/* Calculate an offset in an address */
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word_t
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calcoffset(val)
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valu_t val;
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@ -175,68 +189,150 @@ valu_t val;
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return(0);
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}
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word_t
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calcaddress (val,typ,reg)
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valu_t val;
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short typ;
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word_t reg;
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{
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int tmpval;
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if (typ == S_UND){
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DOTVAL += 8;
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return 0;
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/* This routine deals with STR and LDR instructions */
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strldr(opc, ins, val)
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long opc, ins;
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valu_t val;
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{
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long reg, reg2; /* The registers we are using */
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long tmpval;
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/* If the expression was a register, then just output it and save 24
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bytes */
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if (success){
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emit4(opc|ins|val);
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return;
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}
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reg = ins & 0x0000F000; /* Extract register from instruction */
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if (opc == LDR){
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tmpval = val - DOTVAL - 8;
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if(small((tmpval & 0xFFFFF000) == 0, 8))
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return(val|0x008F0000);
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if (oursmall((tmpval & 0xFFFFF000) == 0, 16)){ /* If it's +ve */
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emit4(opc|ins|tmpval|0x018F0000); /* PC rel, up bit */
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return;
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}
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tmpval *= -1;
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if(small((tmpval & 0xFFFFF000) == 0, 8))
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return(val|0x000F0000);
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emit4(0xE51F0004 | reg << 12);
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emit4(val | 0xF0000000);
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return(reg << 16);
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if (oursmall((tmpval & 0xFFFFF000) == 0, 16)){ /* If it's -ve */
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emit4(opc|ins|tmpval|0x010F0000); /* PC rel, no up bit */
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return;
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}
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if (!bflag && pass == PASS_3){ /* Debugging info */
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/* warning("LDR address extension"); */
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if (dflag)
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printf("value: %lx\n", val);
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}
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opc = 0x03A00000; /* Set opc for putaddr */
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if (oursmall((val & 0xFFFF0000) == 0, 8)){
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putaddr(opc, ins & 0xFFBFFFFF, val, 2);
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emit4(0x05100000|ins|reg<<4);
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return;
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}
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if (oursmall((val & 0xFF000000) == 0, 4)){
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putaddr(opc, ins & 0xFFBFFFFF, val, 3);
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emit4(0x05100000|ins|reg<<4);
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return;
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}
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putaddr(opc, ins & 0xFFBFFFFF, val, 4);
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emit4(0x05100000|ins|reg<<4);
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return;
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}
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/* If the failure was an STR instruction, things are a bit more complicated as
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we can't overwrite the register before we store its value. We therefore
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need to use another register as well, which must be saved and restored.
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This register is saved on a stack pointed to by R12. Apart from this
|
||||
complication, the scheme is similar to the LDR above. */
|
||||
|
||||
if (opc == STR){
|
||||
reg2 = reg >> 12; /* Use R6 as the second register, */
|
||||
reg2 = (reg2 == 6 ? 0 : 6); /* or R0 if we can't */
|
||||
|
||||
tmpval = val - DOTVAL - 8;
|
||||
if (oursmall((tmpval & 0xFFFFF000) == 0, 24)){ /* If it's +ve */
|
||||
emit4(opc|ins|tmpval|0x018F0000); /* PC rel, up bit */
|
||||
return;
|
||||
}
|
||||
|
||||
tmpval *= -1;
|
||||
if (oursmall((tmpval & 0xFFFFF000) == 0, 24)){ /* If it's -ve */
|
||||
emit4(opc|ins|tmpval|0x010F0000); /* PC rel, no up bit */
|
||||
return;
|
||||
}
|
||||
|
||||
if (!bflag && pass == PASS_3){ /* Debugging info */
|
||||
/* warning("STR address extension"); */
|
||||
if (dflag)
|
||||
printf("value: %lx\n", val);
|
||||
}
|
||||
|
||||
opc = 0x03A00000; /* Set opc for putaddr */
|
||||
|
||||
if (oursmall((val & 0xFFFF0000) == 0, 8)){
|
||||
emit4(0xE92C0000|1<<reg2);
|
||||
putaddr(opc, (ins & 0xFFBF0FFF)|reg2<<12, val, 2);
|
||||
emit4(0x05000000|ins|reg2<<16);
|
||||
emit4(0xE8BC0000|1<<reg2);
|
||||
return;
|
||||
}
|
||||
if (oursmall((val & 0xFF000000) == 0, 4)){
|
||||
emit4(0xE92C0000|1<<reg2);
|
||||
putaddr(opc, (ins & 0xFFBF0FFF)|reg2<<12, val, 3);
|
||||
emit4(0x05000000|ins|reg2<<16);
|
||||
emit4(0xE8BC0000|1<<reg2);
|
||||
return;
|
||||
}
|
||||
emit4(0xE92C0000|1<<reg2);
|
||||
putaddr(opc, (ins & 0xFFBF0FFF)|reg2<<12, val, 4);
|
||||
emit4(0x05000000|ins|reg2<<16);
|
||||
emit4(0xE8BC0000|1<<reg2);
|
||||
return;
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
word_t
|
||||
|
||||
/* This routine deals with ADR instructions. The ARM does not have a
|
||||
'calculate effective address' instruction, so we use ADD, SUB, MOV or
|
||||
MVN instead. ADR is not a genuine instruction, but is provided to make
|
||||
life easier. At present these are all calculated by using a MOV and
|
||||
successive ADDs. Even if the address will fit into a single MOV, we
|
||||
still use two instructions; the second is a no-op. This is to cure the
|
||||
optimisation problem with mobile addresses ! */
|
||||
|
||||
|
||||
calcadr(ins, reg, val, typ)
|
||||
word_t ins, reg;
|
||||
valu_t val;
|
||||
short typ;
|
||||
{
|
||||
valu_t tmpval = val;
|
||||
word_t opc;
|
||||
int i = 0;
|
||||
word_t opc = 0xff; /* Dummy opc used as a flag for data() */
|
||||
|
||||
if (typ != S_ABS){
|
||||
tmpval = val-DOTVAL-8;
|
||||
if (tmpval > 0) {
|
||||
if (small((tmpval & 0xFFFFFF00) == 0),12){
|
||||
emit4(ins|ADD|0x020F0000|reg<<12|tmpval);
|
||||
return 0;
|
||||
}
|
||||
/* First check that the address is in range */
|
||||
|
||||
if (val < 0)
|
||||
tmpval = ~tmpval; /* Invert negative addresses for check */
|
||||
|
||||
if ((tmpval & 0xFC000000) && (typ != S_UND)){
|
||||
serror("adr address out of range");
|
||||
return;
|
||||
}
|
||||
|
||||
tmpval *= -1;
|
||||
if (small((tmpval & 0xFFFFFF00) == 0), 12){
|
||||
emit4(ins|SUB|0x020F0000|reg<<12|tmpval);
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
/* Can't do it PC relative, so use an absolute MOV instead */
|
||||
|
||||
tmpval = val;
|
||||
opc = MOV;
|
||||
if (calcimm(&opc, &tmpval, typ)){
|
||||
emit4(ins|opc|0x020F0000|reg<<12|tmpval);
|
||||
return 0;
|
||||
}
|
||||
data (opc, ins|reg<<12, val, typ);
|
||||
return;
|
||||
|
||||
/* Failed */
|
||||
if (pass == PASS_1)
|
||||
DOTVAL += 16;
|
||||
else
|
||||
serror("illegal ADR argument");
|
||||
return ;
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -246,9 +342,15 @@ valu_t val;
|
|||
short typ;
|
||||
word_t styp;
|
||||
{
|
||||
if (typ=S_UND) return 0;
|
||||
if (val & 0xFFFFFFE0) serror("shiftcount out of range");
|
||||
if (styp && !val) warning("shiftcount 0");
|
||||
if (typ == S_UND)
|
||||
return(0);
|
||||
|
||||
if (val & 0xFFFFFFE0)
|
||||
serror("shiftcount out of range");
|
||||
|
||||
if (styp && !val)
|
||||
warning("shiftcount 0");
|
||||
|
||||
return((val & 0x1F)<<7);
|
||||
}
|
||||
|
||||
|
|
@ -265,3 +367,144 @@ long *x;
|
|||
}
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
This routine overcomes the 12-bit encoding problem by outputting a number
|
||||
a byte at a time. For a MOV, it first uses a MOV, then successive ADDs.
|
||||
It will not use any more ADDs than needed to completely output the number.
|
||||
A similar approach is used for ADDs and SUBs.
|
||||
There is a problem here with optimisation in the third pass; if the
|
||||
instruction needed two ADDs in the second pass, but only one in the third
|
||||
pass, then the second ADD is replaced with a no-op. We cannot emit one
|
||||
less instruction, because that will upset other addresses.
|
||||
*/
|
||||
|
||||
putaddr(opc, ins, val, count)
|
||||
long opc, ins, val;
|
||||
int count;
|
||||
{
|
||||
long tmpval = val;
|
||||
long reg = ins & 0x0000F000;
|
||||
|
||||
emit4(opc|ins|(val & 0x000000FF));
|
||||
|
||||
tmpval = (val & 0x0000FF00) >> 8 | 0x00000C00;
|
||||
|
||||
/* Decide what to use for the additional instructions */
|
||||
|
||||
if (opc == 0x03a00000) /* This one is for strldr */
|
||||
opc = 0x02800000;
|
||||
|
||||
if (opc == MOV)
|
||||
opc = ADD;
|
||||
|
||||
if (opc == MVN)
|
||||
opc = SUB;
|
||||
|
||||
if ((tmpval & 0x000000FF) != 0)
|
||||
emit4(opc|ins|reg<<4|tmpval);
|
||||
else
|
||||
emit4(0xF0000000); /* No-op if a zero argument */
|
||||
|
||||
if (count == 3 || count == 4){ /* Must use three or more instructions */
|
||||
if ((val & 0xFFFF0000) != 0){
|
||||
tmpval = (val & 0x00FF0000) >> 16 | 0x00000800;
|
||||
emit4(opc|ins|reg<<4|tmpval);
|
||||
}
|
||||
else
|
||||
emit4(0xF0000000); /* No-op */
|
||||
}
|
||||
|
||||
if (count == 4){ /* Must use four instructions */
|
||||
if ((val & 0xFF000000) != 0){
|
||||
tmpval = (val & 0xFF000000) >> 24 | 0x00000400;
|
||||
emit4(opc|ins|reg<<4|tmpval);
|
||||
}
|
||||
else
|
||||
emit4(0xF0000000); /* No-op */
|
||||
}
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
/* The following piece of code is stolen from comm7.c; it needs some minor
|
||||
fixes for the ARM, so it is included here rather than altering the existing
|
||||
code. It maintains a bit table to say whether or not an optimisation is
|
||||
possible. The original had some problems:
|
||||
(a). It assumed that the memory returned by malloc() was cleared to zero.
|
||||
This is true on a Sun, but not under Minix; small() should really
|
||||
use calloc() instead.
|
||||
(b). It assumed that if an optimisation was possible in pass 2, it must
|
||||
also be possible in pass 3, and produced an assertion error if it
|
||||
wasn't. This is OK for optimising things like long or short branch
|
||||
instructions on a 68000, but not for ADRs on the ARM. A previous
|
||||
optimisation may place an address out of 12-bit encoding range on
|
||||
pass 3, when it was in range on pass 2. However we have to be
|
||||
careful here .....
|
||||
*/
|
||||
|
||||
#define PBITTABSZ 128
|
||||
static char *pbittab[PBITTABSZ];
|
||||
|
||||
oursmall(fitsmall, gain)
|
||||
{
|
||||
register bit;
|
||||
register char *p;
|
||||
|
||||
if (DOTSCT == NULL)
|
||||
nosect();
|
||||
if (bflag)
|
||||
return(0);
|
||||
if (nbits == BITCHUNK) {
|
||||
bitindex++;
|
||||
nbits = 0;
|
||||
if (bitindex == PBITTABSZ) {
|
||||
static int w_given;
|
||||
if (pass == PASS_1 && ! w_given) {
|
||||
w_given = 1;
|
||||
warning("bit table overflow");
|
||||
}
|
||||
return(0);
|
||||
}
|
||||
if (pbittab[bitindex] == 0 && pass == PASS_1) {
|
||||
if ((pbittab[bitindex] = malloc(MEMINCR)) == 0) {
|
||||
static int w2_given;
|
||||
|
||||
if (!w2_given) {
|
||||
w2_given = 1;
|
||||
warning("out of space for bit table");
|
||||
}
|
||||
}
|
||||
}
|
||||
if (pbittab[bitindex] == 0)
|
||||
return (0);
|
||||
}
|
||||
bit = 1 << (nbits&7);
|
||||
p = pbittab[bitindex]+(nbits>>3);
|
||||
nbits++;
|
||||
|
||||
switch (pass) {
|
||||
case PASS_1:
|
||||
*p = 0;
|
||||
return(0);
|
||||
case PASS_2:
|
||||
if (fitsmall) {
|
||||
DOTGAIN += gain;
|
||||
*p |= bit;
|
||||
}
|
||||
return(fitsmall);
|
||||
case PASS_3:
|
||||
if (!(fitsmall || (*p & bit) == 0)){
|
||||
printf("line: %ld - small failed\n", lineno);
|
||||
printf("fitsmall: %d bit: %d\n", fitsmall, (*p & bit));
|
||||
if (fitsmall)
|
||||
return(0);
|
||||
else
|
||||
serror("This one is fatal!");
|
||||
}
|
||||
return(*p & bit);
|
||||
}
|
||||
/*NOTREACHED*/
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue