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Add some more opcodes; rearrange the registers to be more PowerPC-friendly.

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This commit is contained in:
David Given 2016-10-09 14:45:13 +02:00
parent cfe5312fcc
commit 36cddd6afb
2 changed files with 83 additions and 48 deletions
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96
mach/proto/mcg/table
View file

@ -1,6 +1,18 @@
REGISTERS
/* Reverse order because registers are assigned from top down. */
/* Registers are allocated top down; the order here is odd in order to make
* sure that non-volatile registers get allocated from r31 (or f31) down. */
r12 bytes4 int volatile;
r11 bytes4 int volatile;
r10 bytes4 int volatile;
r9 bytes4 int volatile;
r8 bytes4 int volatile;
r7 bytes4 int volatile;
r6 bytes4 int volatile;
r5 bytes4 int volatile;
r4 bytes4 int volatile;
r3 bytes4 int ret volatile;
r31 bytes4 int;
r30 bytes4 int;
@ -20,52 +32,42 @@ REGISTERS
r16 bytes4 int;
r15 bytes4 int;
r14 bytes4 int;
r13 bytes4 int;
r12 bytes4 int;
r11 bytes4 int;
r10 bytes4 int;
r9 bytes4 int;
r8 bytes4 int;
r7 bytes4 int;
r6 bytes4 int;
r5 bytes4 int;
r4 bytes4 int;
r3 bytes4 int ret;
f31 bytes4 bytes8 float;
f30 bytes4 bytes8 float;
f29 bytes4 bytes8 float;
f28 bytes4 bytes8 float;
f27 bytes4 bytes8 float;
f26 bytes4 bytes8 float;
f25 bytes4 bytes8 float;
f24 bytes4 bytes8 float;
f23 bytes4 bytes8 float;
f22 bytes4 bytes8 float;
f21 bytes4 bytes8 float;
f20 bytes4 bytes8 float;
f19 bytes4 bytes8 float;
f18 bytes4 bytes8 float;
f17 bytes4 bytes8 float;
f16 bytes4 bytes8 float;
f15 bytes4 bytes8 float;
f14 bytes4 bytes8 float;
f13 bytes4 bytes8 float;
f12 bytes4 bytes8 float;
f11 bytes4 bytes8 float;
f10 bytes4 bytes8 float;
f9 bytes4 bytes8 float;
f8 bytes4 bytes8 float;
f7 bytes4 bytes8 float;
f6 bytes4 bytes8 float;
f5 bytes4 bytes8 float;
f4 bytes4 bytes8 float;
f3 bytes4 bytes8 float;
f2 bytes4 bytes8 float;
f1 bytes4 bytes8 float;
f0 bytes4 bytes8 float;
f14 bytes4 float volatile;
f13 bytes4 float volatile;
f12 bytes4 float volatile;
f11 bytes4 float volatile;
f10 bytes4 float volatile;
f9 bytes4 float volatile;
f8 bytes4 float volatile;
f7 bytes4 float volatile;
f6 bytes4 float volatile;
f5 bytes4 float volatile;
f4 bytes4 float volatile;
f3 bytes4 float volatile;
f2 bytes4 float volatile;
f1 bytes4 float volatile;
f0 bytes4 float volatile;
cr0 cr;
f31 bytes4 float;
f30 bytes4 float;
f29 bytes4 float;
f28 bytes4 float;
f27 bytes4 float;
f26 bytes4 float;
f25 bytes4 float;
f24 bytes4 float;
f23 bytes4 float;
f22 bytes4 float;
f21 bytes4 float;
f20 bytes4 float;
f19 bytes4 float;
f18 bytes4 float;
f17 bytes4 float;
f16 bytes4 float;
f15 bytes4 float;
cr0 cr;
DECLARATIONS
@ -302,6 +304,10 @@ PATTERNS
emit "divw %out, %left, %right"
cost 4;
out:(int)reg = ASL4(left:(int)reg, right:(int)reg)
emit "slw %out, %left, %right"
cost 4;
out:(int)reg = NEG4(left:(int)reg)
emit "neg %out, %left"
cost 4;

29
mach/proto/mcg/treebuilder.c
View file

@ -376,6 +376,10 @@ static void insn_ivalue(int opcode, arith value)
case op_mli: simple_alu2(opcode, value, IR_MUL); break;
case op_dvi: simple_alu2(opcode, value, IR_DIV); break;
case op_rmi: simple_alu2(opcode, value, IR_MOD); break;
case op_sli: simple_alu2(opcode, value, IR_ASL); break;
case op_sri: simple_alu2(opcode, value, IR_ASR); break;
case op_slu: simple_alu2(opcode, value, IR_LSL); break;
case op_sru: simple_alu2(opcode, value, IR_LSR); break;
case op_ngi: simple_alu1(opcode, value, IR_NEG); break;
case op_and: simple_alu2(opcode, value, IR_AND); break;
@ -414,6 +418,31 @@ static void insn_ivalue(int opcode, arith value)
);
break;
case op_lil:
push(
new_ir1(
IR_LOAD, EM_wordsize,
new_ir1(
IR_LOAD, EM_wordsize,
new_localir(value)
)
)
);
break;
case op_sil:
appendir(
new_ir2(
IR_STORE, EM_wordsize,
new_ir1(
IR_LOAD, EM_wordsize,
new_localir(value)
),
pop(EM_wordsize)
)
);
break;
case op_inl:
change_by(new_localir(value), 1);
break;