From 3c1d2d79f0817602ac5aa8e8ee7069960d90cc6d Mon Sep 17 00:00:00 2001 From: George Koehler Date: Mon, 30 Jan 2017 16:15:02 -0500 Subject: [PATCH] Remove type quad, use type word_t in PowerPC as. Type word_t is for encoding the machine instructions. It only needs 32 bits for PowerPC. It was long (which can have 32 or 64 bits), and there was a second type quad (which was uint32_t). Switch word_t to uint32_t and replace quad with word_t. Also change valu_t and ADDR_T away from long. --- mach/powerpc/as/mach0.c | 8 +++---- mach/powerpc/as/mach1.c | 4 ++-- mach/powerpc/as/mach4.c | 46 ++++++++++++++++++++--------------------- mach/powerpc/as/mach5.c | 12 +++++------ 4 files changed, 34 insertions(+), 36 deletions(-) diff --git a/mach/powerpc/as/mach0.c b/mach/powerpc/as/mach0.c index 3246828fc..1c2051753 100644 --- a/mach/powerpc/as/mach0.c +++ b/mach/powerpc/as/mach0.c @@ -11,15 +11,13 @@ #define DEBUG 0 #undef valu_t -#define valu_t long +#define valu_t int32_t #undef ADDR_T -#define ADDR_T long +#define ADDR_T uint32_t #undef word_t -#define word_t long - -typedef uint32_t quad; +#define word_t uint32_t #undef ALIGNWORD #define ALIGNWORD 4 diff --git a/mach/powerpc/as/mach1.c b/mach/powerpc/as/mach1.c index c1651fcfe..a1977f466 100644 --- a/mach/powerpc/as/mach1.c +++ b/mach/powerpc/as/mach1.c @@ -5,5 +5,5 @@ #include -extern quad emit_hi(struct expr_t* expr, bool is_signed); -extern quad emit_lo(struct expr_t* expr); +extern word_t emit_hi(struct expr_t* expr, bool is_signed); +extern word_t emit_lo(struct expr_t* expr); diff --git a/mach/powerpc/as/mach4.c b/mach/powerpc/as/mach4.c index 7fca36e42..7464dcb6a 100644 --- a/mach/powerpc/as/mach4.c +++ b/mach/powerpc/as/mach4.c @@ -94,7 +94,7 @@ operation | OP_LI32 li32 /* emitted in subrule */ | OP_clrlsldi c GPR ',' GPR ',' u6 ',' u6 { - quad mb = ($7 - $9) & 0x3f; + word_t mb = ($7 - $9) & 0x3f; fit($9 <= $7); emit4($1 | $2 | ($5<<21) | ($3<<16) | SH6($9) | MB6(mb)); } @@ -104,41 +104,41 @@ operation } | OP_clrrdi c GPR ',' GPR ',' u6 { - quad me = 63 - $7; + word_t me = 63 - $7; emit4($1 | $2 | ($5<<21) | ($3<<16) | SH6(0) | MB6(me)); } | OP_extldi c GPR ',' GPR ',' u6 ',' u6 { - quad me = ($7 - 1) & 0x3f; + word_t me = ($7 - 1) & 0x3f; fit($7 > 0); emit4($1 | $2 | ($5<<21) | ($3<<16) | SH6($9) | MB6(me)); } | OP_extrdi c GPR ',' GPR ',' u6 ',' u6 { - quad sh = ($9 + $7) & 0x3f; - quad mb = (64 - $7) & 0x3f; + word_t sh = ($9 + $7) & 0x3f; + word_t mb = (64 - $7) & 0x3f; fit($7 > 0); emit4($1 | $2 | ($5<<21) | ($3<<16) | SH6(sh) | MB6(mb)); } | OP_rotrdi c GPR ',' GPR ',' u6 { - quad sh = (64 - $7) & 0x3f; + word_t sh = (64 - $7) & 0x3f; emit4($1 | $2 | ($5<<21) | ($3<<16) | SH6(sh) | MB6(0)); } | OP_sldi c GPR ',' GPR ',' u6 { - quad me = 63 - $7; + word_t me = 63 - $7; emit4($1 | $2 | ($5<<21) | ($3<<16) | SH6($7) | MB6(me)); } | OP_srdi c GPR ',' GPR ',' u6 { - quad sh = (64 - $7) & 0x3f; + word_t sh = (64 - $7) & 0x3f; emit4($1 | $2 | ($5<<21) | ($3<<16) | SH6(sh) | MB6($7)); } | OP_clrlslwi c GPR ',' GPR ',' u5 ',' u5 { - quad mb = ($7 - $9) & 0x1f; - quad me = 31 - $9; + word_t mb = ($7 - $9) & 0x1f; + word_t me = 31 - $9; fit($9 <= $7); emit4($1 | $2 | ($5<<21) | ($3<<16) | ($9<<11) | (mb<<6) | (me<<1)); @@ -150,56 +150,56 @@ operation } | OP_clrrwi c GPR ',' GPR ',' u5 { - quad me = 31 - $7; + word_t me = 31 - $7; emit4($1 | $2 | ($5<<21) | ($3<<16) | (0<<11) | (0<<6) | (me<<1)); } | OP_extlwi c GPR ',' GPR ',' u5 ',' u5 { - quad me = ($7 - 1) & 0x1f; + word_t me = ($7 - 1) & 0x1f; fit($7 > 0); emit4($1 | $2 | ($5<<21) | ($3<<16) | ($9<<11) | (0<<6) | (me<<1)); } | OP_extrwi c GPR ',' GPR ',' u5 ',' u5 { - quad sh = ($9 + $7) & 0x1f; - quad mb = (32 - $7) & 0x1f; + word_t sh = ($9 + $7) & 0x1f; + word_t mb = (32 - $7) & 0x1f; fit($7 > 0); emit4($1 | $2 | ($5<<21) | ($3<<16) | (sh<<11) | (mb<<6) | (31<<1)); } | OP_inslwi c GPR ',' GPR ',' u5 ',' u5 { - quad sh = (32 - $9) & 0x1f; - quad me = ($9 + $7 - 1) & 0x1f; + word_t sh = (32 - $9) & 0x1f; + word_t me = ($9 + $7 - 1) & 0x1f; fit($7 > 0); emit4($1 | $2 | ($5<<21) | ($3<<16) | (sh<<11) | ($9<<6) | (me<<1)); } | OP_insrwi c GPR ',' GPR ',' u5 ',' u5 { - quad sh = (32 - $9 - $7) & 0x1f; - quad me = ($9 + $7 - 1) & 0x1f; + word_t sh = (32 - $9 - $7) & 0x1f; + word_t me = ($9 + $7 - 1) & 0x1f; fit($7 > 0); emit4($1 | $2 | ($5<<21) | ($3<<16) | (sh<<11) | ($9<<6) | (me<<1)); } | OP_rotrwi c GPR ',' GPR ',' u5 { - quad sh = (32 - $7) & 0x1f; + word_t sh = (32 - $7) & 0x1f; emit4($1 | $2 | ($5<<21) | ($3<<16) | (sh<<11) | (0<<6) | (31<<1)); } | OP_slwi c GPR ',' GPR ',' u5 { - quad me = 31 - $7; + word_t me = 31 - $7; emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11) | (0<<6) | (me<<1)); } | OP_srwi c GPR ',' GPR ',' u5 { - quad sh = (32 - $7) & 0x1f; + word_t sh = (32 - $7) & 0x1f; emit4($1 | $2 | ($5<<21) | ($3<<16) | (sh<<11) | ($7<<6) | (31<<1)); } @@ -367,8 +367,8 @@ bda li32 : GPR ',' expr { - quad type = $3.typ & S_TYP; - quad val = $3.val; + word_t type = $3.typ & S_TYP; + word_t val = $3.val; if ((type == S_ABS) && (val <= 0xffff)) emit4((14<<26) | ($1<<21) | (0<<16) | val); /* addi */ else diff --git a/mach/powerpc/as/mach5.c b/mach/powerpc/as/mach5.c index e3e23f272..87d514053 100644 --- a/mach/powerpc/as/mach5.c +++ b/mach/powerpc/as/mach5.c @@ -1,10 +1,10 @@ -quad emit_hi(struct expr_t* expr, bool is_signed) +word_t emit_hi(struct expr_t* expr, bool is_signed) { /* If this is a symbol reference, discard the symbol and keep only the * offset part. */ - quad type = expr->typ & S_TYP; - quad val = expr->val; + word_t type = expr->typ & S_TYP; + word_t val = expr->val; uint16_t hi = val >> 16; uint16_t lo = val & 0xffff; @@ -23,10 +23,10 @@ quad emit_hi(struct expr_t* expr, bool is_signed) return hi; } -quad emit_lo(struct expr_t* expr) +word_t emit_lo(struct expr_t* expr) { - quad type = expr->typ & S_TYP; - quad val = expr->val; + word_t type = expr->typ & S_TYP; + word_t val = expr->val; /* If the assembler stored a symbol for relocation later, we need to * abandon it (because the relocation was generated by emit_ha). */