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Don't write out constant data as big-endian! Some other cleanups.

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--HG--
branch : dtrg-videocore
This commit is contained in:
David Given 2013-05-25 00:33:38 +01:00
parent 98e745d04c
commit 472f778342
3 changed files with 15 additions and 20 deletions
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1
mach/vc4/as/mach0.c
View file

@ -30,4 +30,3 @@ typedef unsigned long quad;
#undef VALWIDTH #undef VALWIDTH
#define VALWIDTH 8 #define VALWIDTH 8
#define FIXUPFLAGS (RELBR | RELWR)

28
mach/vc4/ncg/mach.c
View file

@ -10,9 +10,7 @@
int framesize; int framesize;
/* /* Write out a constant data section. */
* machine dependent back end routines for the Zilog Z80.
*/
con_part(int sz, word w) con_part(int sz, word w)
{ {
@ -20,19 +18,12 @@ con_part(int sz, word w)
part_size++; part_size++;
if (part_size == TEM_WSIZE) if (part_size == TEM_WSIZE)
part_flush(); part_flush();
if (sz == 1) { if (sz == 1 || sz == 2) {
w &= 0xFF; w &= (sz == 1 ? 0xFF : 0xFFFF);
w <<= 8*(3-part_size); w <<= 8 * part_size;
part_word |= w;
} else if (sz == 2) {
w &= 0xFFFF;
if (part_size == 0) {
/* Shift 8 for m68k2, 16 otherwise */
w <<= 4 * TEM_WSIZE;
}
part_word |= w; part_word |= w;
} else { } else {
assert(sz == TEM_WSIZE); assert(sz == 4);
part_word = w; part_word = w;
} }
part_size += sz; part_size += sz;
@ -40,7 +31,6 @@ con_part(int sz, word w)
con_mult(word sz) con_mult(word sz)
{ {
if (argval != 4) if (argval != 4)
fatal("bad icon/ucon size"); fatal("bad icon/ucon size");
fprintf(codefile,".data4 %s\n", str); fprintf(codefile,".data4 %s\n", str);
@ -48,9 +38,9 @@ con_mult(word sz)
#define CODE_GENERATOR #define CODE_GENERATOR
#define IEEEFLOAT #define IEEEFLOAT
#define FL_MSL_AT_LOW_ADDRESS 1 #define FL_MSL_AT_LOW_ADDRESS 0
#define FL_MSW_AT_LOW_ADDRESS 1 #define FL_MSW_AT_LOW_ADDRESS 0
#define FL_MSB_AT_LOW_ADDRESS 1 #define FL_MSB_AT_LOW_ADDRESS 0
#include <con_float> #include <con_float>
void prolog(full nlocals) void prolog(full nlocals)
@ -149,7 +139,7 @@ static void saveloadregs(const char* op)
if (minreg != 32) if (minreg != 32)
{ {
fprintf(codefile, "! saving registers %d to %d\n", minreg, maxreg); fprintf(codefile, "! saving registers %d to %d\n", minreg, maxreg);
assert(minreg == 6); assert((minreg == 6) || (minreg == 16));
fprintf(codefile, "%s r6-r%d\n", op, maxreg); fprintf(codefile, "%s r6-r%d\n", op, maxreg);
} }

6
mach/vc4/ncg/table
View file

@ -221,6 +221,12 @@ STACKINGRULES
comment {LABEL, "push stackable"} comment {LABEL, "push stackable"}
push %1 push %1
from OP+GPRI to STACK
uses GPR0
gen
move %1, %a
push %a
from OP+GPRI to STACK from OP+GPRI to STACK
gen gen
comment {LABEL, "push via scratch"} comment {LABEL, "push via scratch"}