From 48e3aab72858159e9537de9655bab8d6a0a9d97c Mon Sep 17 00:00:00 2001 From: George Koehler Date: Mon, 30 Jan 2017 15:47:09 -0500 Subject: [PATCH] Swap RA and RS when assembling "and", "or", and such instructions. They must use OP_RA_RS_RB_C instead of OP_RS_RA_RB_C. The code generator often sets RS and RA to the same register, so swapping them causes no change in many programs. I also rename OP_RS_RA_UI_CC to OP_RA_RS_UI_CC, and OP_RS_RA_C to OP_RA_RS_C, because they already swap RA and RS. --- mach/powerpc/as/mach2.c | 6 +++--- mach/powerpc/as/mach3.c | 38 +++++++++++++++++++------------------- mach/powerpc/as/mach4.c | 6 +++--- 3 files changed, 25 insertions(+), 25 deletions(-) diff --git a/mach/powerpc/as/mach2.c b/mach/powerpc/as/mach2.c index 555b92c38..4065334e6 100644 --- a/mach/powerpc/as/mach2.c +++ b/mach/powerpc/as/mach2.c @@ -51,6 +51,7 @@ %token OP_LIA %token OP_LIL %token OP_LI32 +%token OP_RA_RS_C %token OP_RA_RS_RB_C %token OP_RA_RS_RB_MB5_ME5_C %token OP_RA_RS_RB_MB6_C @@ -58,17 +59,16 @@ %token OP_RA_RS_SH5_MB5_ME5_C %token OP_RA_RS_SH6_C %token OP_RA_RS_SH6_MB6_C +%token OP_RA_RS_UI +%token OP_RA_RS_UI_CC %token OP_RS_FXM %token OP_RS_RA -%token OP_RS_RA_C %token OP_RS_RA_D %token OP_RS_RA_DS %token OP_RS_RA_NB %token OP_RS_RA_RB %token OP_RS_RA_RB_C %token OP_RS_RA_RA_C -%token OP_RS_RA_UI -%token OP_RS_RA_UI_CC %token OP_RS_RB %token OP_RS_SPR %token OP_RS_SR diff --git a/mach/powerpc/as/mach3.c b/mach/powerpc/as/mach3.c index 16c1e6ae0..91b088a6a 100644 --- a/mach/powerpc/as/mach3.c +++ b/mach/powerpc/as/mach3.c @@ -498,25 +498,25 @@ 0, OP_TOX_RA_SI, 3<<26 | 31<<21, "twui", /* page 62 */ -0, OP_RS_RA_UI_CC, 28<<26, "andi", /* C compulsory */ -0, OP_RS_RA_UI_CC, 29<<26, "andis", /* C compulsory */ -0, OP_RS_RA_UI, 24<<26, "ori", -0, OP_RS_RA_UI, 25<<26, "oris", -0, OP_RS_RA_UI, 26<<26, "xori", -0, OP_RS_RA_UI, 27<<26, "xoris", -0, OP_RS_RA_RB_C, 31<<26 | 28<<1, "and", -0, OP_RS_RA_RB_C, 31<<26 | 444<<1, "or", -0, OP_RS_RA_RB_C, 31<<26 | 316<<1, "xor", -0, OP_RS_RA_RB_C, 31<<26 | 476<<1, "nand", -0, OP_RS_RA_RB_C, 31<<26 | 124<<1, "nor", -0, OP_RS_RA_RB_C, 31<<26 | 284<<1, "eqv", -0, OP_RS_RA_RB_C, 31<<26 | 60<<1, "andc", -0, OP_RS_RA_RB_C, 31<<26 | 412<<1, "orc", -0, OP_RS_RA_C, 31<<26 | 954<<1, "extsb", -0, OP_RS_RA_C, 31<<26 | 922<<1, "extsh", -0, OP_RS_RA_C, 31<<26 | 986<<1, "extsw", -0, OP_RS_RA_C, 31<<26 | 58<<1, "cntlzd", -0, OP_RS_RA_C, 31<<26 | 26<<1, "cntlzw", +0, OP_RA_RS_UI_CC, 28<<26, "andi", /* C compulsory */ +0, OP_RA_RS_UI_CC, 29<<26, "andis", /* C compulsory */ +0, OP_RA_RS_UI, 24<<26, "ori", +0, OP_RA_RS_UI, 25<<26, "oris", +0, OP_RA_RS_UI, 26<<26, "xori", +0, OP_RA_RS_UI, 27<<26, "xoris", +0, OP_RA_RS_RB_C, 31<<26 | 28<<1, "and", +0, OP_RA_RS_RB_C, 31<<26 | 444<<1, "or", +0, OP_RA_RS_RB_C, 31<<26 | 316<<1, "xor", +0, OP_RA_RS_RB_C, 31<<26 | 476<<1, "nand", +0, OP_RA_RS_RB_C, 31<<26 | 124<<1, "nor", +0, OP_RA_RS_RB_C, 31<<26 | 284<<1, "eqv", +0, OP_RA_RS_RB_C, 31<<26 | 60<<1, "andc", +0, OP_RA_RS_RB_C, 31<<26 | 412<<1, "orc", +0, OP_RA_RS_C, 31<<26 | 954<<1, "extsb", +0, OP_RA_RS_C, 31<<26 | 922<<1, "extsh", +0, OP_RA_RS_C, 31<<26 | 986<<1, "extsw", +0, OP_RA_RS_C, 31<<26 | 58<<1, "cntlzd", +0, OP_RA_RS_C, 31<<26 | 26<<1, "cntlzw", /* extended m using logic */ 0, OP_RS_RA_RA_C, 31<<26 | 444<<1, "mr", diff --git a/mach/powerpc/as/mach4.c b/mach/powerpc/as/mach4.c index 99f7f4537..7fca36e42 100644 --- a/mach/powerpc/as/mach4.c +++ b/mach/powerpc/as/mach4.c @@ -42,6 +42,7 @@ operation | OP_FRT_RA_D FPR ',' e16 '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); } | OP_FRT_RA_RB FPR ',' GPR ',' GPR { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); } | OP_FRT_C c FPR { emit4($1 | $2 | ($3<<21)); } + | OP_RA_RS_C c GPR ',' GPR { emit4($1 | $2 | ($5<<21) | ($3<<16)); } | OP_RA_RS_RB_C c GPR ',' GPR ',' GPR { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11)); } | OP_RA_RS_RB_MB5_ME5_C c GPR ',' GPR ',' GPR ',' u5 ',' u5 @@ -58,6 +59,8 @@ operation { emit4($1 | $2 | ($5<<21) | ($3<<16) | SH6($7)); } | OP_RA_RS_SH6_MB6_C c GPR ',' GPR ',' u6 ',' u6 { emit4($1 | $2 | ($5<<21) | ($3<<16) | SH6($7) | MB6($9)); } + | OP_RA_RS_UI GPR ',' GPR ',' e16 { emit4($1 | ($4<<21) | ($2<<16) | $6); } + | OP_RA_RS_UI_CC C GPR ',' GPR ',' e16 { emit4($1 | ($5<<21) | ($3<<16) | $7); } | OP_RT GPR { emit4($1 | ($2<<21)); } | OP_RT_RA_C c GPR ',' GPR { emit4($1 | $2 | ($3<<21) | ($5<<16)); } | OP_RT_RA_D GPR ',' e16 '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); } @@ -73,12 +76,9 @@ operation | OP_RT_SI GPR ',' e16 { emit4($1 | ($2<<21) | $4); } | OP_RT_SPR GPR ',' spr_num { emit4($1 | ($2<<21) | ($4<<11)); } | OP_RS_FXM u7 ',' GPR { emit4($1 | ($4<<21) | ($2<<12)); } - | OP_RS_RA_C c GPR ',' GPR { emit4($1 | $2 | ($5<<21) | ($3<<16)); } | OP_RS_RA_D GPR ',' e16 '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); } | OP_RS_RA_DS GPR ',' ds '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); } | OP_RS_RA_NB GPR ',' GPR ',' nb { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); } - | OP_RS_RA_UI GPR ',' GPR ',' e16 { emit4($1 | ($4<<21) | ($2<<16) | $6); } - | OP_RS_RA_UI_CC C GPR ',' GPR ',' e16 { emit4($1 | ($5<<21) | ($3<<16) | $7); } | OP_RS_RA_RB GPR ',' GPR ',' GPR { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); } | OP_RS_RA_RB_C c GPR ',' GPR ',' GPR { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11)); } | OP_RS_RA_RA_C c GPR ',' GPR { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($5<<11)); }