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Archival checkin (semi-working code).

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dtrg 2007-11-02 18:56:58 +00:00
parent 54ce3f451b 58e5e12ead
commit 4dd1ff6d80
40 changed files with 3866 additions and 0 deletions
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6
mach/powerpc/as/.distr Normal file
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mach0.c
mach1.c
mach2.c
mach3.c
mach4.c
mach5.c

31
mach/powerpc/as/mach0.c Normal file
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/*
* $Source$
* $State$
*/
#define THREE_PASS /* branch and offset optimization */
#define BYTES_REVERSED /* high order byte has lowest address */
#define WORDS_REVERSED /* high order word has lowest address */
#define LISTING /* enable listing facilities */
#define RELOCATION /* generate relocatable code */
#define DEBUG 0
#undef valu_t
#define valu_t long
#undef ADDR_T
#define ADDR_T long
#undef word_t
#define word_t long
#undef ALIGNWORD
#define ALIGNWORD 4
#undef ALIGNSECT
#define ALIGNSECT 4
#undef VALWIDTH
#define VALWIDTH 8
#define FIXUPFLAGS (RELBR | RELWR)

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mach/powerpc/as/mach1.c Normal file
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/*
* $Source$
* $State$
*/

89
mach/powerpc/as/mach2.c Normal file
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/*
* $Source$
* $State$
*/
%token <y_word> GPR
%token <y_word> SPR
%token <y_word> FPR
%token <y_word> CR
%token <y_word> C
%token <y_word> OP
%token <y_word> OP_BF
%token <y_word> OP_BF_BFA
%token <y_word> OP_BF_FRA_FRB
%token <y_word> OP_BF_L_RA_RB
%token <y_word> OP_BF_L_RA_SI
%token <y_word> OP_BF_L_RA_UI
%token <y_word> OP_BF_U_C
%token <y_word> OP_BO_BI_BDA
%token <y_word> OP_BO_BI_BDL
%token <y_word> OP_BO_BI_BH
%token <y_word> OP_BT_C
%token <y_word> OP_BT_BA_BB
%token <y_word> OP_FLM_FRB_C
%token <y_word> OP_FRS_RA_D
%token <y_word> OP_FRS_RA_RB
%token <y_word> OP_FRT_C
%token <y_word> OP_FRT_FRA_FRB_C
%token <y_word> OP_FRT_FRA_FRC_FRB_C
%token <y_word> OP_FRT_FRA_FRC_C
%token <y_word> OP_FRT_FRB_C
%token <y_word> OP_FRT_RA_D
%token <y_word> OP_FRT_RA_RB
%token <y_word> OP_L
%token <y_word> OP_LEV
%token <y_word> OP_LIA
%token <y_word> OP_LIL
%token <y_word> OP_L_RB
%token <y_word> OP_RA_RB
%token <y_word> OP_RB
%token <y_word> OP_RS
%token <y_word> OP_RS_FXM
%token <y_word> OP_RS_L
%token <y_word> OP_RS_RA
%token <y_word> OP_RS_RA_C
%token <y_word> OP_RS_RA_D
%token <y_word> OP_RS_RA_DS
%token <y_word> OP_RS_RA_NB
%token <y_word> OP_RS_RA_RB
%token <y_word> OP_RS_RA_RB_C
%token <y_word> OP_RS_RA_RB_MB5_ME5_C
%token <y_word> OP_RS_RA_RB_MB6_C
%token <y_word> OP_RS_RA_RB_ME6_C
%token <y_word> OP_RS_RA_SH_MB5_ME5_C
%token <y_word> OP_RS_RA_SH_MB6_SH_C
%token <y_word> OP_RS_RA_SH_ME6_SH_C
%token <y_word> OP_RS_RA_SH5_C
%token <y_word> OP_RS_RA_SH6_C
%token <y_word> OP_RS_RA_UI
%token <y_word> OP_RS_RA_UI_CC
%token <y_word> OP_RS_RB
%token <y_word> OP_RS_SPR
%token <y_word> OP_RS_SR
%token <y_word> OP_RT
%token <y_word> OP_RT_FXM
%token <y_word> OP_RT_RA_C
%token <y_word> OP_RT_RA_D
%token <y_word> OP_RT_RA_DS
%token <y_word> OP_RT_RA_NB
%token <y_word> OP_RT_RA_RB
%token <y_word> OP_RT_RA_RB_C
%token <y_word> OP_RT_RA_SI
%token <y_word> OP_RT_RA_SI_addic
%token <y_word> OP_RT_RB
%token <y_word> OP_RT_SPR
%token <y_word> OP_RT_SR
%token <y_word> OP_RT_TBR
%token <y_word> OP_TH_RA_RB
%token <y_word> OP_TO_RA_RB
%token <y_word> OP_TO_RA_SI
%token <y_word> OP_la
/* Other token types */
%type <y_word> c
%type <y_word> e16 u8 u7 u6 u5 u4 u2 u1
%type <y_word> nb ds bda bdl lia lil

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/*
* $Source$
* $State$
*/
/* Integer registers */
0, GPR, 0, "r0",
0, GPR, 1, "r1",
0, GPR, 1, "sp",
0, GPR, 2, "r2",
0, GPR, 2, "fp",
0, GPR, 3, "r3",
0, GPR, 4, "r4",
0, GPR, 5, "r5",
0, GPR, 6, "r6",
0, GPR, 7, "r7",
0, GPR, 8, "r8",
0, GPR, 9, "r9",
0, GPR, 10, "r10",
0, GPR, 11, "r11",
0, GPR, 12, "r12",
0, GPR, 13, "r13",
0, GPR, 14, "r14",
0, GPR, 15, "r15",
0, GPR, 16, "r16",
0, GPR, 17, "r17",
0, GPR, 18, "r18",
0, GPR, 19, "r19",
0, GPR, 20, "r20",
0, GPR, 21, "r21",
0, GPR, 22, "r22",
0, GPR, 23, "r23",
0, GPR, 24, "r24",
0, GPR, 25, "r25",
0, GPR, 26, "r26",
0, GPR, 27, "r27",
0, GPR, 28, "r28",
0, GPR, 29, "r29",
0, GPR, 30, "r30",
0, GPR, 31, "r31",
/* Floating-point registers */
0, FPR, 0, "f0",
0, FPR, 1, "f1",
0, FPR, 2, "f2",
0, FPR, 3, "f3",
0, FPR, 4, "f4",
0, FPR, 5, "f5",
0, FPR, 6, "f6",
0, FPR, 7, "f7",
0, FPR, 8, "f8",
0, FPR, 9, "f9",
0, FPR, 10, "f10",
0, FPR, 11, "f11",
0, FPR, 12, "f12",
0, FPR, 13, "f13",
0, FPR, 14, "f14",
0, FPR, 15, "f15",
0, FPR, 16, "f16",
0, FPR, 17, "f17",
0, FPR, 18, "f18",
0, FPR, 19, "f19",
0, FPR, 20, "f20",
0, FPR, 21, "f21",
0, FPR, 22, "f22",
0, FPR, 23, "f23",
0, FPR, 24, "f24",
0, FPR, 25, "f25",
0, FPR, 26, "f26",
0, FPR, 27, "f27",
0, FPR, 28, "f28",
0, FPR, 29, "f29",
0, FPR, 30, "f30",
0, FPR, 31, "f31",
/* Special registers */
0, SPR, 32, "xer",
0, SPR, 256, "lr",
0, SPR, 288, "ctr",
/* Condition registers */
0, CR, 0, "cr0",
0, CR, 1, "cr1",
0, CR, 2, "cr2",
0, CR, 3, "cr3",
0, CR, 4, "cr4",
0, CR, 5, "cr5",
0, CR, 6, "cr6",
0, CR, 7, "cr7",
/* Condition code flag */
0, C, 0, ".",
/* Special instructions */
0, OP_la, 0, "la",
/* Branch processor instructions (page 20) */
0, OP_LIL, 18<<26 | 0<<1 | 0<<0, "b",
0, OP_LIA, 18<<26 | 1<<1 | 0<<0, "ba",
0, OP_LIL, 18<<26 | 0<<1 | 1<<0, "bl",
0, OP_LIA, 18<<26 | 1<<1 | 1<<0, "bla",
0, OP_BO_BI_BDL, 16<<26 | 0<<1 | 0<<0, "bc",
0, OP_BO_BI_BDA, 16<<26 | 1<<1 | 0<<0, "bca",
0, OP_BO_BI_BDL, 16<<26 | 0<<1 | 1<<0, "bcl",
0, OP_BO_BI_BDA, 16<<26 | 1<<1 | 1<<0, "bcla",
0, OP_BO_BI_BH, 19<<26 | 16<<1 | 0<<0, "bclr",
0, OP_BO_BI_BH, 19<<26 | 16<<1 | 1<<0, "bclrl",
0, OP_BO_BI_BH, 19<<26 | 528<<1 | 0<<0, "bcctr",
0, OP_BO_BI_BH, 19<<26 | 528<<1 | 1<<0, "bcctrl",
0, OP_LEV, 17<<26 | 1<<1, "sc",
0, OP_BT_BA_BB, 19<<26 | 257<<1, "crand",
0, OP_BT_BA_BB, 19<<26 | 449<<1, "cror",
0, OP_BT_BA_BB, 19<<26 | 193<<1, "crxor",
0, OP_BT_BA_BB, 19<<26 | 225<<1, "crnand",
0, OP_BT_BA_BB, 19<<26 | 33<<1, "crnor",
0, OP_BT_BA_BB, 19<<26 | 289<<1, "crneqv",
0, OP_BT_BA_BB, 19<<26 | 129<<1, "crandc",
0, OP_BT_BA_BB, 19<<26 | 417<<1, "crorc",
0, OP_BF_BFA, 19<<26 | 0<<1, "mcrf",
/* Fixed point instructions (page 29) */
0, OP_RT_RA_D, 34<<26, "lbz",
0, OP_RT_RA_RB, 31<<26 | 87<<1, "lbzx",
0, OP_RT_RA_D, 35<<26, "lbzu",
0, OP_RT_RA_RB, 31<<26 | 119<<1, "lbzux",
0, OP_RT_RA_D, 40<<26, "lhz",
0, OP_RT_RA_RB, 31<<26 | 279<<1, "lhzx",
0, OP_RT_RA_D, 41<<26, "lhzu",
0, OP_RT_RA_RB, 31<<26 | 311<<1, "lhzux",
0, OP_RT_RA_D, 42<<26, "lha",
0, OP_RT_RA_RB, 31<<26 | 343<<1, "lhax",
0, OP_RT_RA_D, 43<<26, "lhau",
0, OP_RT_RA_RB, 31<<26 | 375<<1, "lhaux",
0, OP_RT_RA_D, 32<<26, "lwz",
0, OP_RT_RA_RB, 31<<26 | 23<<1, "lwzx",
0, OP_RT_RA_D, 33<<26, "lwzu",
0, OP_RT_RA_RB, 31<<26 | 55<<1, "lwzux",
0, OP_RT_RA_DS, 58<<26 | 2<<0, "lwa",
0, OP_RT_RA_RB, 31<<26 | 341<<1, "lwax",
0, OP_RT_RA_RB, 31<<26 | 363<<1, "lwaux",
0, OP_RT_RA_DS, 58<<26, "ld",
0, OP_RT_RA_RB, 31<<26 | 21<<1, "ldx",
0, OP_RT_RA_DS, 58<<26 | 1<<0, "ldu",
0, OP_RT_RA_RB, 31<<26 | 53<<1, "ldux",
0, OP_RS_RA_D, 38<<26, "stb",
0, OP_RS_RA_RB, 31<<26 | 215<<1, "stbx",
0, OP_RS_RA_D, 39<<26, "stbu",
0, OP_RS_RA_RB, 31<<26 | 247<<1, "stbux",
0, OP_RS_RA_D, 44<<26, "sth",
0, OP_RS_RA_RB, 31<<26 | 407<<1, "sthx",
0, OP_RS_RA_D, 45<<26, "sthu",
0, OP_RS_RA_RB, 31<<26 | 439<<1, "sthux",
0, OP_RS_RA_D, 36<<26, "stw",
0, OP_RS_RA_RB, 31<<26 | 151<<1, "stwx",
0, OP_RS_RA_D, 37<<26, "stwu",
0, OP_RS_RA_RB, 31<<26 | 183<<1, "stwux",
0, OP_RS_RA_DS, 62<<26, "std",
0, OP_RS_RA_RB, 31<<26 | 149<<1, "stdx",
0, OP_RS_RA_DS, 62<<26 | 1<<0, "stdu",
0, OP_RS_RA_RB, 31<<26 | 181<<1, "stdux",
/* page 42 */
0, OP_RT_RA_RB, 31<<26 | 790<<1, "lhbrx",
0, OP_RT_RA_RB, 31<<26 | 534<<1, "lwbrx",
0, OP_RS_RA_RB, 31<<26 | 918<<1, "sthbrx",
0, OP_RS_RA_RB, 31<<26 | 662<<1, "stwbrx",
/* page 44 */
0, OP_RT_RA_D, 46<<26, "lmw",
0, OP_RS_RA_D, 47<<26, "stmw",
/* page 45 */
0, OP_RT_RA_NB, 31<<26 | 597<<1, "lswi",
0, OP_RT_RA_RB, 31<<26 | 533<<1, "lswx",
0, OP_RS_RA_NB, 31<<26 | 725<<1, "stswi",
0, OP_RS_RA_RB, 31<<26 | 661<<1, "stswx",
/* page 49 */
0, OP_RT_RA_SI, 14<<26, "addi",
0, OP_RT_RA_SI, 15<<26, "addis",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 266<<1, "add",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 266<<1, "addo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 40<<1, "subf",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 40<<1, "subfo",
0, OP_RT_RA_SI_addic, 12<<26, "addic", /* special case C */
0, OP_RT_RA_SI, 8<<26, "subfic",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 138<<1, "adde",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 138<<1, "addeo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 136<<1, "subfe",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 136<<1, "subfeo",
0, OP_RT_RA_C, 31<<26 | 0<<10 | 234<<1, "addme",
0, OP_RT_RA_C, 31<<26 | 1<<10 | 234<<1, "addmeo",
0, OP_RT_RA_C, 31<<26 | 0<<10 | 232<<1, "subfme",
0, OP_RT_RA_C, 31<<26 | 1<<10 | 232<<1, "subfmeo",
0, OP_RT_RA_C, 31<<26 | 0<<10 | 202<<1, "addze",
0, OP_RT_RA_C, 31<<26 | 1<<10 | 202<<1, "addzeo",
0, OP_RT_RA_C, 31<<26 | 0<<10 | 200<<1, "subfze",
0, OP_RT_RA_C, 31<<26 | 1<<10 | 200<<1, "subfzeo",
0, OP_RT_RA_C, 31<<26 | 0<<10 | 104<<1, "neg",
0, OP_RT_RA_C, 31<<26 | 1<<10 | 104<<1, "nego",
/* page 54 */
0, OP_RT_RA_SI, 7<<26, "mulli",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 233<<1, "mulld",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 233<<1, "mulldo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 235<<1, "mullw",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 235<<1, "mullwo",
0, OP_RT_RA_RB_C, 31<<26 | 73<<1, "mulhd",
0, OP_RT_RA_RB_C, 31<<26 | 75<<1, "mulhw",
0, OP_RT_RA_RB_C, 31<<26 | 9<<1, "mulhdu",
0, OP_RT_RA_RB_C, 31<<26 | 11<<1, "mulhwu",
/* page 56 */
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 489<<1, "divd",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 489<<1, "divdo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 491<<1, "divw",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 491<<1, "divwo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 457<<1, "divdu",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 457<<1, "divduo",
0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 459<<1, "divwu",
0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 459<<1, "divwuo",
/* page 58 */
0, OP_BF_L_RA_SI, 11<<26, "cmpi",
0, OP_BF_L_RA_RB, 31<<26 | 0<<1, "cmp",
0, OP_BF_L_RA_UI, 10<<26, "cmpli",
0, OP_BF_L_RA_RB, 31<<26 | 32<<1, "cmpl",
/* page 60 */
0, OP_TO_RA_SI, 2<<26, "tdi",
0, OP_TO_RA_SI, 3<<26, "twi",
0, OP_TO_RA_RB, 31<<26 | 68<<1, "td",
0, OP_TO_RA_RB, 31<<26 | 4<<1, "tw",
/* page 62 */
0, OP_RS_RA_UI_CC, 28<<26, "andi", /* C compulsory */
0, OP_RS_RA_UI_CC, 29<<26, "andis", /* C compulsory */
0, OP_RS_RA_UI, 24<<26, "ori",
0, OP_RS_RA_UI, 25<<26, "oris",
0, OP_RS_RA_UI, 26<<26, "xori",
0, OP_RS_RA_UI, 27<<26, "xoris",
0, OP_RS_RA_RB_C, 31<<26 | 28<<1, "and",
0, OP_RS_RA_RB_C, 31<<26 | 444<<1, "or",
0, OP_RS_RA_RB_C, 31<<26 | 316<<1, "xor",
0, OP_RS_RA_RB_C, 31<<26 | 476<<1, "nand",
0, OP_RS_RA_RB_C, 31<<26 | 124<<1, "nor",
0, OP_RS_RA_RB_C, 31<<26 | 284<<1, "eqv",
0, OP_RS_RA_RB_C, 31<<26 | 60<<1, "andc",
0, OP_RS_RA_RB_C, 31<<26 | 412<<1, "orc",
0, OP_RS_RA_C, 31<<26 | 954<<1, "extsb",
0, OP_RS_RA_C, 31<<26 | 922<<1, "extsh",
0, OP_RS_RA_C, 31<<26 | 986<<1, "extsw",
0, OP_RS_RA_C, 31<<26 | 58<<1, "cntlzd",
0, OP_RS_RA_C, 31<<26 | 26<<1, "cntlzw",
/* page 69 */
0, OP_RS_RA_SH_MB6_SH_C, 30<<26 | 0<<2, "rldicl",
0, OP_RS_RA_SH_ME6_SH_C, 30<<26 | 1<<2, "rldicr",
0, OP_RS_RA_SH_MB6_SH_C, 30<<26 | 2<<2, "rldic",
0, OP_RS_RA_SH_MB5_ME5_C, 21<<26, "rlwinm",
0, OP_RS_RA_RB_MB6_C, 30<<26 | 8<<1, "rldcl",
0, OP_RS_RA_RB_ME6_C, 30<<26 | 9<<1, "rldcr",
0, OP_RS_RA_RB_MB5_ME5_C, 23<<26, "rlwnm",
0, OP_RS_RA_SH_MB6_SH_C, 30<<26 | 3<<2, "rldimi",
0, OP_RS_RA_SH_MB5_ME5_C, 20<<26, "rlwimi",
/* page 74 */
0, OP_RS_RA_RB_C, 31<<26 | 27<<1, "sld",
0, OP_RS_RA_RB_C, 31<<26 | 24<<1, "slw",
0, OP_RS_RA_RB_C, 31<<26 | 539<<1, "srd",
0, OP_RS_RA_RB_C, 31<<26 | 536<<1, "srw",
0, OP_RS_RA_SH6_C, 31<<26 | 413<<2, "sradi",
0, OP_RS_RA_SH5_C, 31<<26 | 824<<1, "srawi",
0, OP_RS_RA_RB_C, 31<<26 | 794<<1, "srad",
0, OP_RS_RA_RB_C, 31<<26 | 792<<1, "sraw",
/* page 78 */
0, OP_RS_SPR, 31<<26 | 467<<1, "mtspr",
0, OP_RT_SPR, 31<<26 | 339<<1, "mfspr",
0, OP_RS_FXM, 31<<26 | 0<<21 | 144<<1, "mtcrf",
0, OP_RT, 31<<26 | 0<<21 | 19<<1, "mfcr",
/* Floating point instructions (page 83) */
0, OP_FRT_RA_D, 48<<26, "lfs",
0, OP_FRT_RA_RB, 31<<26 | 535<<1, "lfsx",
0, OP_FRT_RA_D, 49<<26, "lfsu",
0, OP_FRT_RA_RB, 31<<26 | 567<<1, "lfsux",
0, OP_FRT_RA_D, 50<<26, "lfd",
0, OP_FRT_RA_RB, 31<<26 | 599<<1, "lfdx",
0, OP_FRT_RA_D, 51<<26, "lfdu",
0, OP_FRT_RA_RB, 31<<26 | 631<<1, "lfdux",
0, OP_FRS_RA_D, 52<<26, "stfs",
0, OP_FRS_RA_RB, 31<<26 | 663<<1, "stfsx",
0, OP_FRS_RA_D, 53<<26, "stfsu",
0, OP_FRS_RA_RB, 31<<26 | 695<<1, "stfsux",
0, OP_FRS_RA_D, 54<<26, "stfd",
0, OP_FRS_RA_RB, 31<<26 | 727<<1, "stfdx",
0, OP_FRS_RA_D, 55<<26, "stfdu",
0, OP_FRS_RA_RB, 31<<26 | 759<<1, "stfdux",
0, OP_FRS_RA_RB, 31<<26 | 983<<1, "stfiwx",
0, OP_FRT_FRB_C, 63<<26 | 72<<1, "fmr",
0, OP_FRT_FRB_C, 63<<26 | 40<<1, "fneg",
0, OP_FRT_FRB_C, 63<<26 | 264<<1, "fabs",
0, OP_FRT_FRB_C, 63<<26 | 136<<1, "fnabs",
0, OP_FRT_FRA_FRB_C, 63<<26 | 21<<1, "fadd",
0, OP_FRT_FRA_FRB_C, 59<<26 | 21<<1, "fadds",
0, OP_FRT_FRA_FRB_C, 63<<26 | 20<<1, "fsub",
0, OP_FRT_FRA_FRB_C, 59<<26 | 20<<1, "fsubs",
0, OP_FRT_FRA_FRC_C, 63<<26 | 25<<1, "fmul",
0, OP_FRT_FRA_FRC_C, 59<<26 | 25<<1, "fmuls",
0, OP_FRT_FRA_FRB_C, 63<<26 | 18<<1, "fdiv",
0, OP_FRT_FRA_FRB_C, 59<<26 | 18<<1, "fdivs",
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 29<<1, "fmadd",
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 29<<1, "fmadds",
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 28<<1, "fmsub",
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 28<<1, "fmsubs",
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 31<<1, "fnmadd",
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 31<<1, "fnmadds",
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 30<<1, "fnmsub",
0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 30<<1, "fnmsubs",
0, OP_FRT_FRB_C, 63<<26 | 12<<1, "frsp",
0, OP_FRT_FRB_C, 63<<26 | 814<<1, "fctid",
0, OP_FRT_FRB_C, 63<<26 | 815<<1, "fctidz",
0, OP_FRT_FRB_C, 63<<26 | 14<<1, "fctiw",
0, OP_FRT_FRB_C, 63<<26 | 15<<1, "fctiwz",
0, OP_FRT_FRB_C, 63<<26 | 846<<1, "fcfid",
0, OP_BF_FRA_FRB, 63<<26 | 0<<1, "fcmpu",
0, OP_BF_FRA_FRB, 63<<26 | 32<<1, "fcmpo",
0, OP_FRT_C, 63<<26 | 583<<1, "mffs",
0, OP_BF_BFA, 63<<26 | 64<<1, "mcrfs",
0, OP_BF_U_C, 63<<26 | 134<<1, "mtfsfi",
0, OP_FLM_FRB_C, 63<<26 | 711<<1, "mtfsf",
0, OP_BT_C, 63<<26 | 70<<1, "mtfsb0",
0, OP_BT_C, 63<<26 | 38<<1, "mtfsb1",
0, OP_FRT_FRB_C, 63<<26 | 22<<1, "fsqrt",
0, OP_FRT_FRB_C, 59<<26 | 22<<1, "fsqrts",
0, OP_FRT_FRB_C, 59<<26 | 24<<1, "fres",
0, OP_FRT_FRB_C, 63<<26 | 26<<1, "frsqrte",
0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 23<<1, "fsel",
/* page 98 */

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/*
* $Source$
* $State$
*/
operation
: OP_BF_BFA CR ',' CR { emit4($1 | ($2<<23) | ($4<<18)); }
| OP_BF_FRA_FRB CR ',' FPR ',' FPR { emit4($1 | ($2<<23) | ($4<<16) | ($6<<11)); }
| OP_BF_L_RA_RB CR ',' u1 ',' GPR ',' GPR { emit4($1 | ($2<<23) | ($4<<21) | ($6<<16) | ($8<<11)); }
| OP_BF_L_RA_SI CR ',' u1 ',' GPR ',' e16 { emit4($1 | ($2<<23) | ($4<<21) | ($6<<16) | $8); }
| OP_BF_L_RA_UI CR ',' u1 ',' GPR ',' e16 { emit4($1 | ($2<<23) | ($4<<21) | ($6<<16) | $8); }
| OP_BF_U_C c CR ',' u4 { emit4($1 | $2 | ($3<<23) | ($5<<12)); }
| OP_BO_BI_BDA u5 ',' u5 ',' bda { emit4($1 | ($2<<21) | ($4<<16) | $6); }
| OP_BO_BI_BDL u5 ',' u5 ',' bdl { emit4($1 | ($2<<21) | ($4<<16) | $6); }
| OP_BO_BI_BH u5 ',' u5 ',' u2 { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
| OP_BT_BA_BB u5 ',' u5 ',' u5 { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
| OP_BT_C c u5 { emit4($1 | $2 | ($3<<21)); }
| OP_FLM_FRB_C c u8 ',' FPR { emit4($1 | $2 | ($3<<17) | ($5<<11)); }
| OP_FRS_RA_D FPR ',' e16 '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); }
| OP_FRS_RA_RB FPR ',' GPR ',' GPR { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
| OP_FRT_FRA_FRB_C c FPR ',' FPR ',' FPR { emit4($1 | $2 | ($3<<21) | ($5<<16) | ($7<<11)); }
| OP_FRT_FRA_FRC_FRB_C c FPR ',' FPR ',' FPR ',' FPR { emit4($1 | $2 | ($3<<21) | ($5<<16) | ($9<<11) | ($7<<6)); }
| OP_FRT_FRA_FRC_C c FPR ',' FPR ',' FPR { emit4($1 | $2 | ($3<<21) | ($5<<16) | ($7<<6)); }
| OP_FRT_FRB_C c FPR ',' FPR { emit4($1 | $2 | ($3<<21) | ($5<<11)); }
| OP_FRT_RA_D FPR ',' e16 '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); }
| OP_FRT_RA_RB FPR ',' GPR ',' GPR { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
| OP_FRT_C c FPR { emit4($1 | $2 | ($3<<21)); }
| OP_RT GPR { emit4($1 | ($2<<21)); }
| OP_RT_RA_C c GPR ',' GPR { emit4($1 | $2 | ($3<<21) | ($5<<16)); }
| OP_RT_RA_D GPR ',' e16 '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); }
| OP_RT_RA_DS GPR ',' ds '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); }
| OP_RT_RA_NB GPR ',' GPR ',' nb { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
| OP_RT_RA_RB GPR ',' GPR ',' GPR { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
| OP_RT_RA_RB_C c GPR ',' GPR ',' GPR { emit4($1 | $2 | ($3<<21) | ($5<<16) | ($7<<11)); }
| OP_RT_RA_SI GPR ',' GPR ',' e16 { emit4($1 | ($2<<21) | ($4<<16) | $6); }
| OP_RT_RA_SI_addic c GPR ',' GPR ',' e16 { emit4($1 | ($2<<26) | ($3<<21) | ($5<<16) | $7); }
| OP_RT_SPR GPR ',' SPR { emit4($1 | ($2<<21) | ($4<<11)); }
| OP_RS_FXM u7 ',' GPR { emit4($1 | ($4<<21) | ($2<<12)); }
| OP_RS_RA_C c GPR ',' GPR { emit4($1 | $2 | ($5<<21) | ($3<<16)); }
| OP_RS_RA_D GPR ',' e16 '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); }
| OP_RS_RA_DS GPR ',' ds '(' GPR ')' { emit4($1 | ($2<<21) | ($6<<16) | $4); }
| OP_RS_RA_NB GPR ',' GPR ',' nb { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
| OP_RS_RA_UI GPR ',' GPR ',' e16 { emit4($1 | ($4<<21) | ($2<<16) | $6); }
| OP_RS_RA_UI_CC C GPR ',' GPR ',' e16 { emit4($1 | ($5<<21) | ($3<<16) | $7); }
| OP_RS_RA_RB GPR ',' GPR ',' GPR { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
| OP_RS_RA_RB_C c GPR ',' GPR ',' GPR { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11)); }
| OP_RS_RA_RB_MB5_ME5_C c GPR ',' GPR ',' GPR ',' u5 ',' u5 { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11) | ($9<<6) | ($11<<1)); }
| OP_RS_RA_RB_MB6_C c GPR ',' GPR ',' GPR ',' u6 { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11) | (($9&0x1F)<<6) | (($9&0x20)>>0)); }
| OP_RS_RA_RB_ME6_C c GPR ',' GPR ',' GPR ',' u6 { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11) | (($9&0x1F)<<6) | (($9&0x20)>>0)); }
| OP_RS_RA_SH_MB5_ME5_C c GPR ',' GPR ',' u5 ',' u5 ',' u5 { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11) | ($9<<6) | ($11<<1)); }
| OP_RS_RA_SH_MB6_SH_C c GPR ',' GPR ',' u6 ',' u6 { emit4($1 | $2 | ($5<<21) | ($3<<16) | (($7&0x1F)<<11) | ($9<<6) | (($7&0x20)>>4)); }
| OP_RS_RA_SH_ME6_SH_C c GPR ',' GPR ',' u6 ',' u6 { emit4($1 | $2 | ($5<<21) | ($3<<16) | (($7&0x1F)<<11) | ($9<<6) | (($7&0x20)>>4)); }
| OP_RS_RA_SH5_C c GPR ',' GPR ',' u5 { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11)); }
| OP_RS_RA_SH6_C c GPR ',' GPR ',' u6 { emit4($1 | $2 | ($5<<21) | ($3<<16) | (($7&0x1F)<<11) | (($7&0x20)>>4)); }
| OP_RS_SPR SPR ',' GPR { emit4($1 | ($4<<21) | ($2<<11)); }
| OP_TO_RA_RB u5 ',' GPR ',' GPR { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
| OP_TO_RA_SI u5 ',' GPR ',' e16 { emit4($1 | ($2<<21) | ($4<<16) | $6); }
| OP_LEV u7 { emit4($1 | ($2<<5)); }
| OP_LIA lia { emit4($1 | $2); }
| OP_LIL lil { emit4($1 | $2); }
;
c
: /* nothing */ { $$ = 0; }
| C { $$ = 1; }
;
e16
: '<' expr
{
DOTVAL += 2;
newrelo($2.typ, RELOH2 | FIXUPFLAGS);
DOTVAL -= 2;
$$ = ($2.val >> 16) & 0xFFFF;
}
| '>' expr
{
DOTVAL += 2;
newrelo($2.typ, RELO2 | FIXUPFLAGS);
DOTVAL -= 2;
$$ = $2.val & 0xFFFF;
}
| expr
{
DOTVAL += 2;
newrelo($1.typ, RELO2 | FIXUPFLAGS);
DOTVAL -= 2;
$$ = $1.val & 0xFFFF;
}
;
u8
: absexp
{
if (($1 < 0) || ($1 > 0xFF))
serror("8-bit unsigned value out of range");
$$ = $1;
}
;
u7
: absexp
{
if (($1 < 0) || ($1 > 0x7F))
serror("7-bit unsigned value out of range");
$$ = $1;
}
;
u6
: absexp
{
if (($1 < 0) || ($1 > 0x3F))
serror("6-bit unsigned value out of range");
$$ = $1;
}
;
u5
: absexp
{
if (($1 < 0) || ($1 > 0x1F))
serror("5-bit unsigned value out of range");
$$ = $1;
}
;
u4
: absexp
{
if (($1 < 0) || ($1 > 0xF))
serror("4-bit unsigned value out of range");
$$ = $1;
}
;
u1
: absexp
{
if (($1 < 0) || ($1 > 1))
serror("1-bit unsigned value out of range");
$$ = $1;
}
;
u2
: absexp
{
if (($1 < 0) || ($1 > 0x3))
serror("2-bit unsigned value out of range");
$$ = $1;
}
;
ds
: e16
{
if ($1 & 3)
serror("value must be 4-aligned");
$$ = $1;
}
;
nb
: absexp
{
if (($1 < 1) || ($1 > 32))
serror("register count must be in the range 1..32");
if ($1 == 32)
$$ = 0;
else
$$ = $1;
}
;
bdl
: expr
{
int dist = $1.val - DOTVAL;
fit(fitx(dist, 25));
if (dist & 0x3)
serror("jump targets must be 4-aligned");
DOTVAL += 2;
newrelo($1.typ, RELO2 | RELPC | FIXUPFLAGS);
DOTVAL -= 2;
$$ = dist & 0xFFFD;
}
;
bda
: expr
{
int target = $1.val;
fit(fitx(target, 16));
if (target & 0x3)
serror("jump targets must be 4-aligned");
DOTVAL += 2;
newrelo($1.typ, RELO2 | FIXUPFLAGS);
DOTVAL -= 2;
$$ = target & 0xFFFD;
}
;
lil
: expr
{
int dist = $1.val - DOTVAL;
fit(fitx(dist, 26));
if (dist & 0x3)
serror("jump targets must be 4-aligned");
newrelo($1.typ, RELOPPC | RELPC | FIXUPFLAGS);
$$ = dist & 0x03FFFFFD;
}
;
lia
: expr
{
int target = $1.val;
fit(fitx(target, 26));
if (target & 0x3)
serror("jump targets must be 4-aligned");
newrelo($1.typ, RELOPPC | FIXUPFLAGS);
$$ = target & 0x03FFFFFD;
}
;

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/*
* $Source$
* $State$
*/

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LIST
libem_s.a

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#
! $Source$
! $State$
! $Revision$
#include "powerpc.h"
.sect .text
! Index into a bounds-checked array.
!
! On entry:
! r3 = ptr to descriptor
! r4 = index
! r5 = address of array
.define .aar4
.aar4:
addis r0, r0, <.trap_earray
ori r0, r0, >.trap_earray
mtspr ctr, r0 ! load CTR with trap address
lwz r0, 0(r3)
subf. r4, r0, r4 ! adjust range
bcctr IFTRUE, LT, 0 ! check lower bound
lwz r0, 4(r3)
cmpl cr0, 0, r4, r3
bcctr IFFALSE, LT, 0 ! check upper bound
lwz r0, 8(r3)
mullw r4, r4, r0 ! scale index
add r3, r4, r5 ! calculate element address
bclr ALWAYS, 0, 0

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#
! $Source$
! $State$
! $Revision$
#include "powerpc.h"
.sect .text
! Converts a 64-bit double into a 32-bit integer.
!
! Stack: ( double -- int )
.define .cfi8
.cfi8:
lfd f0, 0(sp)
fctiwz f0, f0
stfd f0, 0(sp)
addi sp, sp, 4
bclr ALWAYS, 0, 0 ! ...and return

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#
! $Source$
! $State$
! $Revision$
#include "powerpc.h"
.sect .text
! Converts a 64-bit double into a 32-bit unsigned integer.
!
! Stack: ( double -- uint )
.define .cfu8
.cfu8:
la(r3, .fd_00000000)
lfd f0, 0(r3) ! f0 = 0.0
lfd f1, 0(sp) ! value to be converted
la(r3, .fd_FFFFFFFF)
lfd f3, 0(r3) ! f3 = 0xFFFFFFFF
la(r3, .fd_80000000)
lfd f4, 0(r3) ! f4 = 0x80000000
fsel f2, f1, f1, f0
fsub f5, f3, f1
fsel f2, f5, f2, f3
fsub f5, f2, f4
fcmpu cr0, f2, f4
fsel f2, f5, f5, f2
fctiwz f2, f2
stfd f2, 0(sp)
addi sp, sp, 4
bclr IFTRUE, LT, 0
lwz r3, 0(sp)
xoris r3, r3, 0x8000
stw r3, 0(sp)
bclr ALWAYS, 0, 0

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#
! $Source$
! $State$
! $Revision$
#include "powerpc.h"
.sect .text
! Converts a 32-bit integer into a 64-bit double.
!
! Stack: ( int -- double )
.define .cif8
.cif8:
addi sp, sp, -4 ! make space for the double
lwz r3, 4(sp)
xoris r3, r3, 0x8000
stw r3, 4(sp) ! flip sign of integer value
addis r3, r0, 0x4330
stw r3, 0(sp) ! set high word to construct a double
lfd f0, 0(sp) ! load value
la (r3, pivot)
lfd f1, 0(r3) ! load pivot value
fsub f0, f0, f1 ! adjust
stfd f0, 0(sp) ! save value again...
bclr ALWAYS, 0, 0 ! ...and return
.sect .rom
pivot:
.data4 0x43300000
.data4 0x80000000

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#
! $Source$
! $State$
! $Revision$
#include "powerpc.h"
.sect .text
! this is not a subroutine, but just a
! piece of code that computes the jump-
! address and jumps to it.
! traps if resulting address is zero
!
! On entry: r3 = address of CSA table
! r4 = value
.define .csa
.csa:
lwz r5, 0(r3) ! load default
mtspr ctr, r5
lwz r5, 4(r3) ! fetch lower bound
subf. r4, r5, r4 ! adjust value
bcctr IFTRUE, LT, 0 ! jump to default if out of range
lwz r5, 8(r3) ! fetch range
cmp cr0, 0, r4, r5
bcctr IFTRUE, GT, 0 ! jump to default if out of range
addi r3, r3, 12 ! skip header
rlwinm r4, r4, 2, 0, 31-2 ! scale value (<<2)
b 1f
1:
lwzx r5, r3, r4 ! load target
b 1f
1:
mtspr ctr, r5
or. r5, r5, r5 ! test it
b 1f
1:
bcctr IFFALSE, EQ, 0 ! jump to target if non-zero
b .trap_ecase ! otherwise trap

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#
! $Source$
! $State$
! $Revision$
#include "powerpc.h"
.sect .text
! this is not a subroutine, but just a
! piece of code that computes the jump-
! address and jumps to it.
! traps if resulting address is zero
!
! On entry: r3 = address of CSB table
! r4 = value
.define .csb
.csb:
lwz r5, 0(r3) ! load default
mtspr ctr, r5
lwz r6, 4(r3) ! fetch count
1:
or. r6, r6, r6 ! test count
bcctr IFTRUE, EQ, 0 ! exit if zero
addi r6, r6, -1 ! otherwise decrement
lwzu r7, 8(r3) ! fetch target index, increment pointer
cmp cr0, 0, r4, r7 ! compare with value
bc IFFALSE, EQ, 1b ! if not equal, go again
lwz r7, 4(r3) ! fetch target address
mtspr ctr, r7
or. r7, r7, r7 ! test it
bcctr IFFALSE, EQ, 0 ! jump to target if non-zero
b .trap_ecase ! otherwise trap

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#
! $Source$
! $State$
! $Revision$
#include "powerpc.h"
.sect .text
! Converts a 32-bit unsigned integer into a 64-bit double.
!
! Stack: ( uint -- double )
.define .cuf8
.cuf8:
addi sp, sp, -4 ! make space for the double
addis r3, r0, 0x4330
stw r3, 0(sp) ! set high word to construct a double
lfd f0, 0(sp) ! load value
la (r3, pivot)
lfd f1, 0(r3) ! load pivot value
fsub f0, f0, f1 ! adjust
stfd f0, 0(sp) ! save value again...
bclr ALWAYS, 0, 0 ! ...and return
.sect .rom
pivot:
.data4 0x43300000
.data4 0x00000000

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#
! $Source$
! $State$
! $Revision$
#include "powerpc.h"
.sect .rom
! Contains a handy double-precision zero. (Also works as a single-precision
! zero.)
.define .fd_00000000, .fs_00000000
.fd_00000000:
.fs_00000000:
.data4 0x00000000
.data4 0x00000000

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#
! $Source$
! $State$
! $Revision$
#include "powerpc.h"
.sect .rom
! Contains a handy double-precision 0x80000000.
.define .fd_80000000
.fd_80000000:
!float 2.147483648e+9 sz 8
.data1 0101,0340,00,00,00,00,00,00

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#
! $Source$
! $State$
! $Revision$
#include "powerpc.h"
.sect .rom
! Contains a handy double-precision 0xFFFFFFFF.
.define .fd_FFFFFFFF
.fd_FFFFFFFF:
!float 4.294967295e+9 sz 8
.data1 0101,0357,0377,0377,0377,0340,00,00

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/*
* $Source$
* $State$
* $Revision$
*/
/* no headers allowed! */
/* Given a double, calculates the mantissa and exponent.
*
* This function is intended to be called internally by the code generator,
* so the calling convention is odd.
*/
int __fef8(double* fp)
{
double f = *fp;
int exponent, sign;
if (f == 0.0)
return 0;
if (f < 0.0)
{
sign = -1;
f = -f;
}
else
sign = 0;
exponent = 0;
while (f >= 1.0)
{
f /= 2.0;
exponent++;
}
while (f < 0.5)
{
f *= 2.0;
exponent--;
}
*fp = (sign) ? -f : f;
return exponent;
}

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#
! $Source$
! $State$
! $Revision$
#include "powerpc.h"
.sect .text
! Multiplies two floats, and returns the fraction and integer.
.define .fif8
.fif8:
lfd f0, 8(sp)
lfd f1, 0(sp)
fmul f0, f0, f1
fabs f1, f0 ! f0 = result
! The following chunk does f1 = floor(f1). See page 158 of the book.
mtfsfi cr7, 3 ! set rounding mode to -inf.
mtfsb0 23
fctid f2, f1
fcfid f2, f2
mcrfs cr7, cr5
bc IFFALSE, 31, toobig
fmr f1, f2
toobig:
fabs f2, f1 ! f2 = fabs(f1)
fsub f2, f2, f1
stfd f2, 8(sp)
fneg f2, f1
fsel f2, f0, f1, f2
stfd f2, 0(sp)
bclr ALWAYS, 0, 0

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#
! $Source$
! $State$
! $Revision$
#include "powerpc.h"
.sect .text
! Loads a variable-sized structure onto the stack.
!
! r3 = size
! r4 = address
.define .los
.los:
! These sizes are handled specially.
cmpi cr0, 0, r3, 1
bc IFFALSE, GT, size1
cmpi cr0, 0, r3, 2
bc IFFALSE, GT, size2
cmpi cr0, 0, r3, 4
bc IFFALSE, GT, size4
! Variable-sized structure.
addi r3, r3, 3
andi. r3, r3, ~3 ! align size
add r4, r4, r3 ! adjust address to top of block
srawi r3, r3, 2 ! convert size to the number of words
mtspr ctr, r3
1:
lwzu r5, -4(r4)
stwu r5, -4(sp)
bc DNZ, 0, 1b ! decrement CTR, jump if non-zero
bclr ALWAYS, 0, 0
size1:
lbz r3, 0(r4)
b 1f
size2:
lhz r3, 0(r4)
b 1f
size4:
lwz r3, 0(r4)
1:
stwu r3, -4(sp)
bclr ALWAYS, 0, 0

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-- $Source$
-- $State$
-- $Revision$
local d = ROOTDIR.."mach/powerpc/libem/"
libem_powerpc = acklibrary {
outputs = {"%U%/libem-%PLATFORM%.a"},
ACKINCLUDES = {PARENT, d},
ackfile (d.."ret.s"),
ackfile (d.."tge.s"),
ackfile (d.."csa.s"),
ackfile (d.."csb.s"),
ackfile (d.."los.s"),
ackfile (d.."sts.s"),
ackfile (d.."aar4.s"),
ackfile (d.."fef8.c"),
ackfile (d.."fif8.s"),
ackfile (d.."cif8.s"),
ackfile (d.."cuf8.s"),
ackfile (d.."cfi8.s"),
ackfile (d.."cfu8.s"),
ackfile (d.."fd_00000000.s"),
ackfile (d.."fd_80000000.s"),
ackfile (d.."fd_FFFFFFFF.s"),
install = pm.install("%BINDIR%lib/%PLATFORM%/libem.a"),
}

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#
! $Source$
! $State$
! $Revision$
! Declare segments (the order is important).
.sect .text
.sect .rom
.sect .data
.sect .bss
#define IFFALSE 4
#define IFTRUE 12
#define ALWAYS 20
#define DNZ 16
#define LT 0
#define GT 1
#define EQ 2
#define OV 3
#define la(reg, val) addis reg, r0, <val; ori reg, reg, >val

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#
! $Source$
! $State$
! $Revision$
#include "powerpc.h"
.sect .text
! Standard boilerplate for returning from functions.
.define .ret
.ret:
lwz r0, 4(fp)
mtspr lr, r0
lwz r0, 0(fp) ! our stack frame becomes invalid as soon as...
addi sp, fp, 8 ! ...we change sp
or fp, r0, r0
bclr ALWAYS, 0, 0

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#
! $Source$
! $State$
! $Revision$
#include "powerpc.h"
.sect .text
! Stores a variable-sized structure from the stack.
!
! r3 = size
! r4 = address
.define .sts
.sts:
! These sizes are handled specially.
lwz r5, 0(sp)
cmpi cr0, 0, r3, 1
bc IFFALSE, GT, size1
cmpi cr0, 0, r3, 2
bc IFFALSE, GT, size2
cmpi cr0, 0, r3, 4
bc IFFALSE, GT, size4
! Variable-sized structure.
addi r3, r3, 3
andi. r3, r3, ~3 ! align size
srawi r3, r3, 2 ! convert size to the number of words
mtspr ctr, r3
1:
lwz r5, 0(sp)
addi sp, sp, 4
stw r5, 0(r4)
addi r4, r4, 4
bc DNZ, 0, 1b ! decrement CTR, jump if non-zero
bclr ALWAYS, 0, 0
size1:
stb r5, 0(r4)
b 1f
size2:
sth r5, 0(r4)
b 1f
size4:
stw r5, 0(r4)
1:
addi sp, sp, 4
bclr ALWAYS, 0, 0

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#
! $Source$
! $State$
! $Revision$
#include "powerpc.h"
.sect .rom
! Lookup table for tge.
.define .teq_table
.teq_table:
.data4 1 ! . .
.data4 0 ! . G
.data4 0 ! L .
.define .tne_table
.tne_table:
.data4 0 ! . .
.data4 1 ! . G
.data4 1 ! L .
.define .tgt_table
.tgt_table:
.data4 0 ! . .
.data4 1 ! . G
.data4 0 ! L .
.define .tge_table
.tge_table:
.data4 1 ! . .
.data4 1 ! . G
.data4 0 ! L .
.define .tlt_table
.tlt_table:
.data4 0 ! . .
.data4 0 ! . G
.data4 1 ! L .
.define .tle_table
.tle_table:
.data4 1 ! . .
.data4 0 ! . G
.data4 1 ! L .

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pmfile
edata.s
em_end.s
end.s
etext.s

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end_s.a
edata.s
em_end.s
end.s
etext.s

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.sect .text
.sect .rom
.sect .data
.sect .bss
.define _edata
.sect .data
.align 4
.sect .data
_edata:

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! $Source$
! $State$
! $Revision$
.sect .text
.sect .rom
.sect .data
.sect .bss
.sect .end ! only for declaration of _end, __end and endbss.
.define endtext, endrom, enddata, endbss, __end
.sect .text
.align 4
endtext:
.sect .rom
.align 4
endrom:
.sect .data
.align 4
enddata:
.sect .end
.align 4
__end:
endbss:

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.sect .text
.sect .rom
.sect .data
.sect .bss
.define _end
.sect .end ! only for declaration of _end, __end and endbss.
_end:

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.sect .text
.sect .rom
.sect .data
.sect .bss
.define _etext
.sect .text
.align 4
.sect .text
_etext:

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-- $Source$
-- $State$
-- $Revision$
local d = ROOTDIR.."mach/powerpc/libend/"
libend_powerpc = acklibrary {
outputs = {"%U%/libend-%PLATFORM%.a"},
ackfile (d.."edata.s"),
ackfile (d.."em_end.s"),
ackfile (d.."end.s"),
ackfile (d.."etext.s"),
install = pm.install("%BINDIR%lib/%PLATFORM%/libend.a"),
}

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mach.c
mach.h
table

209
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/*
* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
* See the copyright notice in the ACK home directory, in the file "Copyright".
*
*/
#include <stdlib.h>
#include <limits.h>
#ifndef NORCSID
static char rcsid[]= "$Id$" ;
#endif
int framesize;
/*
* machine dependent back end routines for the Zilog Z80.
*/
con_part(int sz, word w)
{
while (part_size % sz)
part_size++;
if (part_size == TEM_WSIZE)
part_flush();
if (sz == 1) {
w &= 0xFF;
w <<= 8*(3-part_size);
part_word |= w;
} else if (sz == 2) {
w &= 0xFFFF;
if (part_size == 0) {
/* Shift 8 for m68k2, 16 otherwise */
w <<= 4 * TEM_WSIZE;
}
part_word |= w;
} else {
assert(sz == TEM_WSIZE);
part_word = w;
}
part_size += sz;
}
con_mult(word sz)
{
if (argval != 4)
fatal("bad icon/ucon size");
fprintf(codefile,".data4 %s\n", str);
}
#define CODE_GENERATOR
#define IEEEFLOAT
#define FL_MSL_AT_LOW_ADDRESS 1
#define FL_MSW_AT_LOW_ADDRESS 1
#define FL_MSB_AT_LOW_ADDRESS 1
#include <con_float>
prolog(full nlocals)
{
int ss = nlocals + 8;
fprintf(codefile, "addi sp, sp, %d\n", -ss);
fprintf(codefile, "stw fp, %d(sp)\n", nlocals);
fprintf(codefile, "mfspr r0, lr\n"
"stw r0, %d(sp)\n", nlocals+4);
fprintf(codefile, "addi fp, sp, %d\n", nlocals);
framesize = nlocals;
}
mes(word type)
{
int argt ;
switch ( (int)type ) {
case ms_ext :
for (;;) {
switch ( argt=getarg(
ptyp(sp_cend)|ptyp(sp_pnam)|sym_ptyp) ) {
case sp_cend :
return ;
default:
strarg(argt) ;
fprintf(codefile,".define %s\n",argstr) ;
break ;
}
}
default :
while ( getarg(any_ptyp) != sp_cend ) ;
break ;
}
}
char *segname[] = {
".sect .text",
".sect .data",
".sect .rom",
".sect .bss"
};
#ifdef REGVARS
static int savedregsi[32];
static int numsaved;
/* Initialise regvar system for one function. */
i_regsave()
{
int i;
fprintf(codefile, "! i_regsave()\n");
for (i=0; i<32; i++)
savedregsi[i] = INT_MAX;
numsaved = 0;
}
/* Mark a register as being saved. */
regsave(const char* regname, full offset, int size)
{
int regnum = atoi(regname+1);
savedregsi[regnum] = offset;
numsaved++;
fprintf(codefile, "! %d is saved in %s\n", offset, regname);
#if 0
fprintf(codefile, "stwu %s, -4(sp)\n", regname);
if (offset >= 0)
fprintf(codefile, "lwz %s, %d(fp)\n", regname, offset);
#endif
}
/* Finish saving ragisters. */
void saveloadregs(const char* ops, const char* opm)
{
int offset = -(framesize + numsaved*4);
int reg = 32;
/* Check for the possibility of a multiple. */
do
{
reg--;
}
while ((reg > 0) && (savedregsi[reg] != INT_MAX));
if (reg < 31)
{
fprintf(codefile, "%s r%d, %d(fp)\n", opm, reg+1, offset);
offset += (31-reg)*4;
}
/* Saved everything else singly. */
while (reg > 0)
{
if (savedregsi[reg] != INT_MAX)
{
fprintf(codefile, "%s r%d, %d(fp)\n", ops, reg, offset);
offset += 4;
}
reg--;
}
}
f_regsave()
{
int i;
fprintf(codefile, "! f_regsave()\n");
fprintf(codefile, "addi sp, sp, %d\n", -numsaved*4);
saveloadregs("stw", "stmw");
for (i=0; i<32; i++)
if ((savedregsi[i] != INT_MAX) && (savedregsi[i] > 0))
fprintf(codefile, "lwz r%d, %d(fp)\n", i, savedregsi[i]);
}
/* Restore all saved registers. */
regreturn()
{
fprintf(codefile, "! regreturn()\n");
saveloadregs("lwz", "lmw");
}
/* Calculate the score of a given register. */
int regscore(full offset, int size, int type, int frequency, int totype)
{
int score;
fprintf(codefile, "! regscore(%ld, %d, %d, %d, %d)\n", offset, size, type, frequency, totype);
if (size != 4)
return -1;
/* Per use: 6 bytes (on average)
* Overhead in prologue: 4 bytes, plus 4 if a parameter
* Overhead in epilogue: 0 bytes
*/
score = frequency*6 - 4 - ((offset>=0) ? 4 : 0);
fprintf(codefile, "! local at offset %d has regvar score %d\n", offset, score);
return score;
}
#endif

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/*
* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
* See the copyright notice in the ACK home directory, in the file "Copyright".
*/
/* $Id$ */
#define ex_ap(y) fprintf(codefile,".extern %s\n",y)
#define in_ap(y) /* nothing */
#define newilb(x) fprintf(codefile,"%s:\n",x)
#define newdlb(x) fprintf(codefile,"%s:\n",x)
#define dlbdlb(x,y) fprintf(codefile,"%s = %s\n",x,y)
#define newlbss(l,x) fprintf(codefile,".comm %s,%u\n",l,x);
#define cst_fmt "%d"
#define off_fmt "%d"
#define ilb_fmt "I%x_%x"
#define dlb_fmt "_%d"
#define hol_fmt "hol%d"
#define hol_off "%ld+hol%d"
#define con_cst(x) fprintf(codefile,".data4\t%ld\n",x)
#define con_ilb(x) fprintf(codefile,".data4\t%s\n",x)
#define con_dlb(x) fprintf(codefile,".data4\t%s\n",x)
#define fmt_id(sf, st) sprintf(st,"_%s",sf)
#define modhead ".sect .text; .sect .rom; .sect .data; .sect .bss\n"
#define BSS_INIT 0

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-- $Source$
-- $State$
local d = ROOTDIR.."mach/powerpc/"
include (d.."libem/pmfile")
include (d.."libend/pmfile")
mach_powerpc = group {
ARCH = "powerpc",
proto_as,
proto_ncg { ARCHDIR = "powerpc" },
proto_top,
-- ego_descr,
}
support_powerpc = group {
OPTIMISATION = "-O",
libem_powerpc,
libend_powerpc,
}

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table

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/* 68020 desciptor table for ACK target optimizer */
MAXOP 3;
%%;
P, Q, R { TRUE };
X, Y, Z { TRUE };
%%;
/* Whitespace is significant here! */
addi X, X, 0 -> ;
addis X, X, 0 -> ;
or X, Y, Z : or. X, X, X -> or. X, Y, Z ;
%%;