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Do not use '#endif/#else xxx'; it is not allowed for ANSI C

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This commit is contained in:
ceriel 1991-12-17 15:05:43 +00:00
parent fa0bee0b26
commit 53c4951b29
40 changed files with 364 additions and 364 deletions
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2
lang/pc/comp/Makefile
View file

@ -2,4 +2,4 @@ distr:
echo '#ifndef lint' > Version.c echo '#ifndef lint' > Version.c
echo 'char Version[] = "ACK Pascal compiler Version XXX";' | \ echo 'char Version[] = "ACK Pascal compiler Version XXX";' | \
sed "s/XXX/`RC -i`/" >> Version.c sed "s/XXX/`RC -i`/" >> Version.c
echo '#endif lint' >> Version.c echo '#endif' >> Version.c

8
lang/pc/comp/error.c
View file

@ -59,7 +59,7 @@ debug(va_alist)
} }
va_end(ap); va_end(ap);
} }
#endif DEBUG #endif /* DEBUG */
/*VARARGS*/ /*VARARGS*/
error(va_alist) error(va_alist)
@ -220,7 +220,7 @@ _error(class, node, ap)
case VDEBUG: case VDEBUG:
remark = "(debug)"; remark = "(debug)";
break; break;
#endif DEBUG #endif /* DEBUG */
} }
/* the place */ /* the place */
@ -235,7 +235,7 @@ _error(class, node, ap)
case FATAL: case FATAL:
#ifdef DEBUG #ifdef DEBUG
case VDEBUG: case VDEBUG:
#endif DEBUG #endif /* DEBUG */
ln = LineNumber; ln = LineNumber;
break; break;
} }
@ -268,7 +268,7 @@ _error(class, node, ap)
} }
#ifdef DEBUG #ifdef DEBUG
} }
#endif DEBUG #endif /* DEBUG */
if( FileName ) fprint(ERROUT, "\"%s\", line %u: ", FileName, ln); if( FileName ) fprint(ERROUT, "\"%s\", line %u: ", FileName, ln);

4
lang/pc/comp/main.c
View file

@ -101,7 +101,7 @@ Compile(src, dst)
LexScan(); LexScan();
return 0; /* running the optimizer is not very useful */ return 0; /* running the optimizer is not very useful */
} }
#endif DEBUG #endif /* DEBUG */
C_init(word_size, pointer_size); C_init(word_size, pointer_size);
if( !C_open(dst) ) if( !C_open(dst) )
fatal("couldn't open output file"); fatal("couldn't open output file");
@ -121,7 +121,7 @@ Compile(src, dst)
C_close(); C_close();
#ifdef DEBUG #ifdef DEBUG
if( options['I'] ) Info(); if( options['I'] ) Info();
#endif DEBUG #endif /* DEBUG */
return !err_occurred; return !err_occurred;
} }

2
lang/pc/comp/options.c
View file

@ -147,7 +147,7 @@ DoOption(text)
} }
} }
break; break;
#endif NOCROSS #endif /* NOCROSS */
} }
} }
} }

4
lang/pc/comp/type.H
View file

@ -146,7 +146,7 @@ extern struct type
#define long_size (SZ_LONG) #define long_size (SZ_LONG)
#define pointer_size (SZ_POINTER) #define pointer_size (SZ_POINTER)
#define real_size (SZ_REAL) #define real_size (SZ_REAL)
#else NOCROSS #else /* NOCROSS */
extern int extern int
word_align, word_align,
int_align, int_align,
@ -161,7 +161,7 @@ extern arith
long_size, long_size,
pointer_size, pointer_size,
real_size; /* All from type.c */ real_size; /* All from type.c */
#endif NOCROSS #endif /* NOCROSS */
extern arith extern arith
align(); align();

2
lang/pc/comp/type.c
View file

@ -33,7 +33,7 @@ arith
long_size = SZ_LONG, long_size = SZ_LONG,
pointer_size = SZ_POINTER, pointer_size = SZ_POINTER,
real_size = SZ_REAL; real_size = SZ_REAL;
#endif NOCROSS #endif /* NOCROSS */
extern arith max_int; extern arith max_int;

2
mach/6500/as/mach4.c
View file

@ -47,7 +47,7 @@ expr
#else #else
$$.typ = $1.typ; /* Even if $1.typ is relocatable, it should be */ $$.typ = $1.typ; /* Even if $1.typ is relocatable, it should be */
/* absolute by the final pass. */ /* absolute by the final pass. */
#endif RELOCATION #endif /* RELOCATION */
} }
; ;
operation operation

2
mach/i386/ncg/mach.c
View file

@ -156,7 +156,7 @@ regreturn()
} }
fputs("leave\nret\n", codefile); fputs("leave\nret\n", codefile);
} }
#endif REGVARS #endif /* REGVARS */
mes(type) word type ; { mes(type) word type ; {
int argt, a1, a2 ; int argt, a1, a2 ;

2
mach/i86/ncg/mach.c
View file

@ -153,7 +153,7 @@ regreturn()
} }
else fputs("jmp .cret\n", codefile); else fputs("jmp .cret\n", codefile);
} }
#endif REGVARS #endif /* REGVARS */
mes(type) word type ; { mes(type) word type ; {
int argt ; int argt ;

4
mach/m68020/as/mach1.c
View file

@ -51,10 +51,10 @@ extern valu_t bd_rel1,bd_rel2,od_rel1,od_rel2;
#ifdef ASLD #ifdef ASLD
#define T_EMIT2(a,b,c,d) t_emit2(a,b,c,(valu_t)0) #define T_EMIT2(a,b,c,d) t_emit2(a,b,c,(valu_t)0)
#define T_EMIT4(a,b,c,d) t_emit4(a,b,c,(valu_t)0) #define T_EMIT4(a,b,c,d) t_emit4(a,b,c,(valu_t)0)
#else ALSD #else /* ALSD */
#define T_EMIT2(a,b,c,d) t_emit2(a,b,c,(valu_t)d) #define T_EMIT2(a,b,c,d) t_emit2(a,b,c,(valu_t)d)
#define T_EMIT4(a,b,c,d) t_emit4(a,b,c,(valu_t)d) #define T_EMIT4(a,b,c,d) t_emit4(a,b,c,(valu_t)d)
#endif ASLD #endif /* ASLD */
#else #else
#define T_EMIT2(a,b,c,d) t_emit2(a) #define T_EMIT2(a,b,c,d) t_emit2(a)
#define T_EMIT4(a,b,c,d) t_emit4(a) #define T_EMIT4(a,b,c,d) t_emit4(a)

98
mach/m68020/ncg/table
View file

@ -200,7 +200,7 @@ regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8)
t_regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8) . t_regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8) .
t_regAcon = {A_REG reg; INT bd;} 4 cost(2,6) . t_regAcon = {A_REG reg; INT bd;} 4 cost(2,6) .
#else TBL68020 #else /* TBL68020 */
/* Part (iii) */ /* Part (iii) */
absolute4 = {ADDR bd;} 4 cost(4,7) "(" bd ")" . absolute4 = {ADDR bd;} 4 cost(4,7) "(" bd ")" .
offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) "(" bd "," reg ")" . offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) "(" bd "," reg ")" .
@ -288,7 +288,7 @@ DREG_pair = {D_REG4 reg1; D_REG4 reg2;} 8 cost(2,0) reg1 ":" reg2 .
#define t_regAregXcon regAregXcon #define t_regAregXcon regAregXcon
#define t_regAcon regAcon #define t_regAcon regAcon
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE!=2 #if WORD_SIZE!=2
#define DLOCAL LOCAL #define DLOCAL LOCAL
@ -349,7 +349,7 @@ control1 = indirect1 + offsetted1 + index_off1 + absolute1 .
alterable1 = data1 + D_REG - consts . alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG . any1 = data1 + D_REG .
#else TBL68020 #else /* TBL68020 */
data4 = D_REG4 + indirect4 + post_inc4 + pre_dec4 + index_off4 + data4 = D_REG4 + indirect4 + post_inc4 + pre_dec4 + index_off4 +
offsetted4 + OFF_off4 + OFF_indoff4 + offsetted4 + OFF_off4 + OFF_indoff4 +
@ -396,7 +396,7 @@ control1 = memory1 - (post_inc1 + pre_dec1 + consts ) .
alterable1 = data1 + D_REG - consts . alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG. /* all four above together */ any1 = data1 + D_REG. /* all four above together */
#endif TBL68020 #endif /* TBL68020 */
/* This is a common part */ /* This is a common part */
#if WORD_SIZE==2 #if WORD_SIZE==2
/* Not any4, since any is used in 'with' and not in 'kills' */ /* Not any4, since any is used in 'with' and not in 'kills' */
@ -424,7 +424,7 @@ allexceptcon = ALL - ( D_REG + A_REG + consts + dreg2 + dreg1 +
t_regAcon + t_regAregXcon ) . t_regAcon + t_regAregXcon ) .
use_index = index_off4 + index_off2 + index_off1 . use_index = index_off4 + index_off2 + index_off1 .
#else TBL68020 #else /* TBL68020 */
reg_memind4 = OFF_off4 + OFF_indoff4 + INDOFF_off4 . reg_memind4 = OFF_off4 + OFF_indoff4 + INDOFF_off4 .
memind4 = reg_memind4 + memind4 = reg_memind4 +
@ -466,7 +466,7 @@ use_indaddr = regAregXcon +
use_index = use_index4 + use_index2 + use_index1 + use_indaddr + regX . use_index = use_index4 + use_index2 + use_index1 + use_indaddr + regX .
#endif TBL68020 #endif /* TBL68020 */
/* A common part */ /* A common part */
posextern = absolute + all_indir . posextern = absolute + all_indir .
@ -513,7 +513,7 @@ test_set2 = datalt2 .
#endif #endif
test_set1 = datalt1 . test_set1 = datalt1 .
#else TBL68020 #else /* TBL68020 */
imm_cmp4 = any4 - immediate4 - A_REG . imm_cmp4 = any4 - immediate4 - A_REG .
imm_cmp2 = any2 - consts . imm_cmp2 = any2 - consts .
@ -527,15 +527,15 @@ test_set2 = data2 - consts .
#endif #endif
test_set1 = data1 - consts . test_set1 = data1 - consts .
#endif TBL68020 #endif /* TBL68020 */
test_set = test_set4 + test_set2 + test_set1 . test_set = test_set4 + test_set2 + test_set1 .
#ifndef TBL68020 #ifndef TBL68020
t_address = address + t_regAregXcon + t_regAcon . t_address = address + t_regAregXcon + t_regAcon .
#else TBL68020 #else /* TBL68020 */
#define t_address address #define t_address address
#endif TBL68020 #endif /* TBL68020 */
#if TBL68881 #if TBL68881
freg = FD_REG + FS_REG . freg = FD_REG + FS_REG .
@ -591,7 +591,7 @@ divs_l "divs.l" data4:ro, LOCAL:rw:cc cost(0,90).
divu_l "divu.l" data4:ro, LOCAL:rw:cc cost(0,78). divu_l "divu.l" data4:ro, LOCAL:rw:cc cost(0,78).
muls_l "muls.l" data4:ro, LOCAL:rw:cc cost(0,44). muls_l "muls.l" data4:ro, LOCAL:rw:cc cost(0,44).
mulu_l "mulu.l" data4:ro, LOCAL:rw:cc cost(0,44). mulu_l "mulu.l" data4:ro, LOCAL:rw:cc cost(0,44).
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
add_l "add.l" any4:ro, D_REG4:rw:cc cost(2,3). add_l "add.l" any4:ro, D_REG4:rw:cc cost(2,3).
@ -777,9 +777,9 @@ extb_l "extb.l" extend1_4+D_REG+LOCAL:rw:cc cost(2,4).
muls_l "muls.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44). muls_l "muls.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
mulu_l "mulu.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44). mulu_l "mulu.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
#endif #endif
#else TBL68020 #else /* TBL68020 */
pea address+control4 cost(2,4). pea address+control4 cost(2,4).
#endif TBL68020 #endif /* TBL68020 */
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* Extra pseudo instruction; it just kills a D_REG; * Extra pseudo instruction; it just kills a D_REG;
@ -888,7 +888,7 @@ from t_regAcon sfit(%bd, 16) to A_REG+areg
from t_regAcon to A_REG+areg from t_regAcon to A_REG+areg
gen move_l %1.reg, %2 gen move_l %1.reg, %2
add_l {const4, %1.bd}, %2 add_l {const4, %1.bd}, %2
#endif TBL68020 #endif /* TBL68020 */
from address - ext_addr to A_REG+areg from address - ext_addr to A_REG+areg
gen lea %1, %2 gen lea %1, %2
@ -977,7 +977,7 @@ from t_regAcon sfit(%bd, 16) to STACK
from t_regAcon to STACK from t_regAcon to STACK
gen move_l %1.reg, {pre_dec4, sp} gen move_l %1.reg, {pre_dec4, sp}
add_l {const4, %1.bd}, {indirect4, sp} add_l {const4, %1.bd}, {indirect4, sp}
#endif TBL68020 #endif /* TBL68020 */
from A_REG to STACK from A_REG to STACK
gen pea {indirect4, %1} gen pea {indirect4, %1}
@ -1059,7 +1059,7 @@ from extend1 to STACK
#ifdef TBL68020 #ifdef TBL68020
from regX to STACK from regX to STACK
gen pea %1 gen pea %1
#endif TBL68020 #endif /* TBL68020 */
/* This last stackingrule is never used: whenever regX is put on /* This last stackingrule is never used: whenever regX is put on
* the fakestack, some em-instuctions are left that remove it * the fakestack, some em-instuctions are left that remove it
* immediately. However cgg complained about not having a * immediately. However cgg complained about not having a
@ -1138,7 +1138,7 @@ from t_regAcon
uses reusing %1, AA_REG=%1.reg uses reusing %1, AA_REG=%1.reg
gen add_l {const4, %1.bd}, %a gen add_l {const4, %1.bd}, %a
yields %a yields %a
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
from regAregXcon %bd==0 && %sc==1 from regAregXcon %bd==0 && %sc==1
@ -1539,7 +1539,7 @@ pat lol mlu stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
with data_int with data_int
kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any) kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
gen mulu_i %1, {LOCAL, $1} gen mulu_i %1, {LOCAL, $1}
#endif TBL68020 #endif /* TBL68020 */
proc lolxxxstl example lol adi stl proc lolxxxstl example lol adi stl
with conreg_int-bconst with conreg_int-bconst
@ -2948,7 +2948,7 @@ with exact local_addr yields {LOCAL, %1.bd+$1}
with exact ext_addr yields {absolute_int, %1.bd+$1} with exact ext_addr yields {absolute_int, %1.bd+$1}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted_int, %1.reg, %1.bd+$1} with regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted_int, %1.reg, %1.bd+$1} with exact regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
with exact regAregXcon yields {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1} with exact regAregXcon yields {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1}
#ifdef FANCY_MODES #ifdef FANCY_MODES
@ -3037,7 +3037,7 @@ with exact ext_addr yields {absolute1, %1.bd}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted1, %1.reg, %1.bd} with regAcon yields {offsetted1, %1.reg, %1.bd}
with regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd} with regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted1, %1.reg, %1.bd} with exact regAcon yields {offsetted1, %1.reg, %1.bd}
with exact regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd} with exact regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#ifdef FANCY_MODES #ifdef FANCY_MODES
@ -3070,7 +3070,7 @@ with exact ext_addr yields {absolute2, %1.bd}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted2, %1.reg, %1.bd} with regAcon yields {offsetted2, %1.reg, %1.bd}
with regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd} with regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted2, %1.reg, %1.bd} with exact regAcon yields {offsetted2, %1.reg, %1.bd}
with exact regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd} with exact regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==2 #if WORD_SIZE==2
@ -3102,7 +3102,7 @@ with exact ext_addr yields {absolute4, %1.bd}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted4, %1.reg, %1.bd} with regAcon yields {offsetted4, %1.reg, %1.bd}
with regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd} with regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted4, %1.reg, %1.bd} with exact regAcon yields {offsetted4, %1.reg, %1.bd}
with exact regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd} with exact regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==4 #if WORD_SIZE==4
@ -3342,7 +3342,7 @@ with regAcon store_int
kills allexceptcon kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1} gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
#endif #endif
#else TBL68020 #else /* TBL68020 */
with exact regAcon store_int with exact regAcon store_int
kills allexceptcon kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1} gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
@ -3390,7 +3390,7 @@ with exact ext_regX store_int
kills allexceptcon kills allexceptcon
gen move %2, {abs_index_int, %1.sc, %1.xreg, %1.bd+$1} gen move %2, {abs_index_int, %1.sc, %1.xreg, %1.bd+$1}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
pat sti $1==1 pat sti $1==1
with A_REG any1 with A_REG any1
@ -3409,7 +3409,7 @@ with regAcon any1
with regAregXcon any1 with regAregXcon any1
kills allexceptcon kills allexceptcon
gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd} gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon any1 with exact regAcon any1
kills allexceptcon kills allexceptcon
gen move %2, {offsetted1, %1.reg, %1.bd} gen move %2, {offsetted1, %1.reg, %1.bd}
@ -3457,7 +3457,7 @@ with exact ext_regX any1
kills allexceptcon kills allexceptcon
gen move %2, {abs_index1, %1.sc, %1.xreg, %1.bd} gen move %2, {abs_index1, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
pat sti $1==2 pat sti $1==2
with A_REG any2 with A_REG any2
@ -3476,7 +3476,7 @@ with regAcon any2
with regAregXcon any2 with regAregXcon any2
kills allexceptcon kills allexceptcon
gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd} gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon any2 with exact regAcon any2
kills allexceptcon kills allexceptcon
gen move %2, {offsetted2, %1.reg, %1.bd} gen move %2, {offsetted2, %1.reg, %1.bd}
@ -3529,7 +3529,7 @@ with exact ext_regX any2
kills allexceptcon kills allexceptcon
gen move %2, {abs_index2, %1.sc, %1.xreg, %1.bd} gen move %2, {abs_index2, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
pat sti $1==4 pat sti $1==4
with A_REG store4-sconsts4 with A_REG store4-sconsts4
@ -3557,7 +3557,7 @@ with regAcon store4-sconsts4
with regAregXcon store4-sconsts4 with regAregXcon store4-sconsts4
kills allexceptcon kills allexceptcon
gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd} gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon store4 with exact regAcon store4
kills allexceptcon kills allexceptcon
gen move %2, {offsetted4, %1.reg, %1.bd} gen move %2, {offsetted4, %1.reg, %1.bd}
@ -3607,7 +3607,7 @@ with exact ext_regX store4
kills allexceptcon kills allexceptcon
gen move %2, {abs_index4, %1.sc, %1.xreg, %1.bd} gen move %2, {abs_index4, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat sti $1==6 pat sti $1==6
@ -3834,7 +3834,7 @@ pat mli $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4 DD_REG4 with data4 DD_REG4
gen muls_l %1, %2 yields %2 gen muls_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".mli"} gen jsr {absolute4, ".mli"}
@ -3853,12 +3853,12 @@ pat dvi $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4-sconsts4 DD_REG4 with data4-sconsts4 DD_REG4
gen divs_l %1, %2 yields %2 gen divs_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvi"} gen jsr {absolute4, ".dvi"}
yields dl1 yields dl1
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat rmi $1==2 pat rmi $1==2
@ -3878,12 +3878,12 @@ with data4-sconsts4 DD_REG4
killreg %2 killreg %2
/* !!!! contents of %2 have changed: make this known to cg */ /* !!!! contents of %2 have changed: make this known to cg */
yields %a yields %a
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvi"} gen jsr {absolute4, ".dvi"}
yields dl2 yields dl2
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat ngi $1==2 pat ngi $1==2
@ -3934,12 +3934,12 @@ pat mlu $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4-sconsts4 DD_REG4 with data4-sconsts4 DD_REG4
gen mulu_l %1, %2 yields %2 gen mulu_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".mlu"} gen jsr {absolute4, ".mlu"}
yields dl1 yields dl1
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat dvu $1==2 pat dvu $1==2
@ -3953,12 +3953,12 @@ pat dvu $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4-sconsts4 DD_REG4 with data4-sconsts4 DD_REG4
gen divu_l %1, %2 yields %2 gen divu_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvu"} gen jsr {absolute4, ".dvu"}
yields dl1 yields dl1
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat rmu $1==2 pat rmu $1==2
@ -3979,12 +3979,12 @@ with data4-sconsts4 DD_REG4
killreg %2 killreg %2
/* !!!! contents of %2 have changed: make this known to cg */ /* !!!! contents of %2 have changed: make this known to cg */
yields %a yields %a
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvu"} gen jsr {absolute4, ".dvu"}
yields dl2 yields dl2
#endif TBL68020 #endif /* TBL68020 */
pat slu leaving sli $1 pat slu leaving sli $1
@ -4400,7 +4400,7 @@ with exact LOCAL ext_regX
with exact absolute4 ext_regX with exact absolute4 ext_regX
yields {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd} yields {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
/* I WOULD ALSO LIKE THIS: /* I WOULD ALSO LIKE THIS:
* pat ads * pat ads
@ -4442,7 +4442,7 @@ with DD_REG4
gen add_l %1, %1 yields %1 gen add_l %1, %1 yields %1
#endif #endif
#endif TBL68020 #endif /* TBL68020 */
/************************************************ /************************************************
@ -5093,7 +5093,7 @@ pat lae aar $2==4 && rom($1,3)==1
pat lae aar $2==4 && nicesize(rom($1,3)) pat lae aar $2==4 && nicesize(rom($1,3))
with D_REG yields {regX, rom($1,3), %1} with D_REG yields {regX, rom($1,3), %1}
leaving ads 4 adp rom($1,3)*(0-rom($1,1)) leaving ads 4 adp rom($1,3)*(0-rom($1,1))
#else TBL68020 #else /* TBL68020 */
pat lae aar $2==4 && rom($1,3)==2 pat lae aar $2==4 && rom($1,3)==2
with DD_REG with DD_REG
gen asl_l {small_const, 1}, %1 gen asl_l {small_const, 1}, %1
@ -5111,7 +5111,7 @@ with DD_REG
gen asl_l {small_const, 3}, %1 gen asl_l {small_const, 3}, %1
yields %1 yields %1
leaving ads 4 adp (0 - rom($1,1))<<3 leaving ads 4 adp (0 - rom($1,1))<<3
#endif TBL68020 #endif /* TBL68020 */
#endif /* ARR_OPT */ #endif /* ARR_OPT */
#endif /* WORD_SIZE!=2 */ #endif /* WORD_SIZE!=2 */
@ -5928,11 +5928,11 @@ with A_REG D_REG4
pea {absolute4, 1} /* push constant 1 == ERANGE */ pea {absolute4, 1} /* push constant 1 == ERANGE */
jsr {absolute4, ".trp"} jsr {absolute4, ".trp"}
1: yields %2 1: yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".rck"} gen jsr {absolute4, ".rck"}
#endif TBL68020 #endif /* TBL68020 */
#endif /* WORD_SIZE==4 || TBL68020 */ #endif /* WORD_SIZE==4 || TBL68020 */
pat rtt leaving ret 0 pat rtt leaving ret 0
@ -6579,10 +6579,10 @@ with memory1+DD_REG
#else #else
#ifdef TBL68020 #ifdef TBL68020
extb_l {LOCAL,$4} extb_l {LOCAL,$4}
#else TBL68020 #else /* TBL68020 */
ext_w {LOCAL,$4} ext_w {LOCAL,$4}
ext_l {LOCAL,$4} ext_l {LOCAL,$4}
#endif TBL68020 #endif /* TBL68020 */
#endif #endif
pat loc loc cii $1==2 && $2==4 pat loc loc cii $1==2 && $2==4

2
mach/m68k2/as/mach5.c
View file

@ -430,7 +430,7 @@ ea707172(sz)
#else #else
if (exp_2.typ != S_ABS) if (exp_2.typ != S_ABS)
sm = 0; sm = 0;
#endif ASLD #endif /* ASLD */
sm = small(sm, 2); sm = small(sm, 2);
if (sm) if (sm)
mrg_2 = 070; mrg_2 = 070;

98
mach/m68k2/ncg/table
View file

@ -200,7 +200,7 @@ regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8)
t_regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8) . t_regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8) .
t_regAcon = {A_REG reg; INT bd;} 4 cost(2,6) . t_regAcon = {A_REG reg; INT bd;} 4 cost(2,6) .
#else TBL68020 #else /* TBL68020 */
/* Part (iii) */ /* Part (iii) */
absolute4 = {ADDR bd;} 4 cost(4,7) "(" bd ")" . absolute4 = {ADDR bd;} 4 cost(4,7) "(" bd ")" .
offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) "(" bd "," reg ")" . offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) "(" bd "," reg ")" .
@ -288,7 +288,7 @@ DREG_pair = {D_REG4 reg1; D_REG4 reg2;} 8 cost(2,0) reg1 ":" reg2 .
#define t_regAregXcon regAregXcon #define t_regAregXcon regAregXcon
#define t_regAcon regAcon #define t_regAcon regAcon
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE!=2 #if WORD_SIZE!=2
#define DLOCAL LOCAL #define DLOCAL LOCAL
@ -349,7 +349,7 @@ control1 = indirect1 + offsetted1 + index_off1 + absolute1 .
alterable1 = data1 + D_REG - consts . alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG . any1 = data1 + D_REG .
#else TBL68020 #else /* TBL68020 */
data4 = D_REG4 + indirect4 + post_inc4 + pre_dec4 + index_off4 + data4 = D_REG4 + indirect4 + post_inc4 + pre_dec4 + index_off4 +
offsetted4 + OFF_off4 + OFF_indoff4 + offsetted4 + OFF_off4 + OFF_indoff4 +
@ -396,7 +396,7 @@ control1 = memory1 - (post_inc1 + pre_dec1 + consts ) .
alterable1 = data1 + D_REG - consts . alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG. /* all four above together */ any1 = data1 + D_REG. /* all four above together */
#endif TBL68020 #endif /* TBL68020 */
/* This is a common part */ /* This is a common part */
#if WORD_SIZE==2 #if WORD_SIZE==2
/* Not any4, since any is used in 'with' and not in 'kills' */ /* Not any4, since any is used in 'with' and not in 'kills' */
@ -424,7 +424,7 @@ allexceptcon = ALL - ( D_REG + A_REG + consts + dreg2 + dreg1 +
t_regAcon + t_regAregXcon ) . t_regAcon + t_regAregXcon ) .
use_index = index_off4 + index_off2 + index_off1 . use_index = index_off4 + index_off2 + index_off1 .
#else TBL68020 #else /* TBL68020 */
reg_memind4 = OFF_off4 + OFF_indoff4 + INDOFF_off4 . reg_memind4 = OFF_off4 + OFF_indoff4 + INDOFF_off4 .
memind4 = reg_memind4 + memind4 = reg_memind4 +
@ -466,7 +466,7 @@ use_indaddr = regAregXcon +
use_index = use_index4 + use_index2 + use_index1 + use_indaddr + regX . use_index = use_index4 + use_index2 + use_index1 + use_indaddr + regX .
#endif TBL68020 #endif /* TBL68020 */
/* A common part */ /* A common part */
posextern = absolute + all_indir . posextern = absolute + all_indir .
@ -513,7 +513,7 @@ test_set2 = datalt2 .
#endif #endif
test_set1 = datalt1 . test_set1 = datalt1 .
#else TBL68020 #else /* TBL68020 */
imm_cmp4 = any4 - immediate4 - A_REG . imm_cmp4 = any4 - immediate4 - A_REG .
imm_cmp2 = any2 - consts . imm_cmp2 = any2 - consts .
@ -527,15 +527,15 @@ test_set2 = data2 - consts .
#endif #endif
test_set1 = data1 - consts . test_set1 = data1 - consts .
#endif TBL68020 #endif /* TBL68020 */
test_set = test_set4 + test_set2 + test_set1 . test_set = test_set4 + test_set2 + test_set1 .
#ifndef TBL68020 #ifndef TBL68020
t_address = address + t_regAregXcon + t_regAcon . t_address = address + t_regAregXcon + t_regAcon .
#else TBL68020 #else /* TBL68020 */
#define t_address address #define t_address address
#endif TBL68020 #endif /* TBL68020 */
#if TBL68881 #if TBL68881
freg = FD_REG + FS_REG . freg = FD_REG + FS_REG .
@ -591,7 +591,7 @@ divs_l "divs.l" data4:ro, LOCAL:rw:cc cost(0,90).
divu_l "divu.l" data4:ro, LOCAL:rw:cc cost(0,78). divu_l "divu.l" data4:ro, LOCAL:rw:cc cost(0,78).
muls_l "muls.l" data4:ro, LOCAL:rw:cc cost(0,44). muls_l "muls.l" data4:ro, LOCAL:rw:cc cost(0,44).
mulu_l "mulu.l" data4:ro, LOCAL:rw:cc cost(0,44). mulu_l "mulu.l" data4:ro, LOCAL:rw:cc cost(0,44).
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
add_l "add.l" any4:ro, D_REG4:rw:cc cost(2,3). add_l "add.l" any4:ro, D_REG4:rw:cc cost(2,3).
@ -777,9 +777,9 @@ extb_l "extb.l" extend1_4+D_REG+LOCAL:rw:cc cost(2,4).
muls_l "muls.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44). muls_l "muls.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
mulu_l "mulu.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44). mulu_l "mulu.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
#endif #endif
#else TBL68020 #else /* TBL68020 */
pea address+control4 cost(2,4). pea address+control4 cost(2,4).
#endif TBL68020 #endif /* TBL68020 */
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* Extra pseudo instruction; it just kills a D_REG; * Extra pseudo instruction; it just kills a D_REG;
@ -888,7 +888,7 @@ from t_regAcon sfit(%bd, 16) to A_REG+areg
from t_regAcon to A_REG+areg from t_regAcon to A_REG+areg
gen move_l %1.reg, %2 gen move_l %1.reg, %2
add_l {const4, %1.bd}, %2 add_l {const4, %1.bd}, %2
#endif TBL68020 #endif /* TBL68020 */
from address - ext_addr to A_REG+areg from address - ext_addr to A_REG+areg
gen lea %1, %2 gen lea %1, %2
@ -977,7 +977,7 @@ from t_regAcon sfit(%bd, 16) to STACK
from t_regAcon to STACK from t_regAcon to STACK
gen move_l %1.reg, {pre_dec4, sp} gen move_l %1.reg, {pre_dec4, sp}
add_l {const4, %1.bd}, {indirect4, sp} add_l {const4, %1.bd}, {indirect4, sp}
#endif TBL68020 #endif /* TBL68020 */
from A_REG to STACK from A_REG to STACK
gen pea {indirect4, %1} gen pea {indirect4, %1}
@ -1059,7 +1059,7 @@ from extend1 to STACK
#ifdef TBL68020 #ifdef TBL68020
from regX to STACK from regX to STACK
gen pea %1 gen pea %1
#endif TBL68020 #endif /* TBL68020 */
/* This last stackingrule is never used: whenever regX is put on /* This last stackingrule is never used: whenever regX is put on
* the fakestack, some em-instuctions are left that remove it * the fakestack, some em-instuctions are left that remove it
* immediately. However cgg complained about not having a * immediately. However cgg complained about not having a
@ -1138,7 +1138,7 @@ from t_regAcon
uses reusing %1, AA_REG=%1.reg uses reusing %1, AA_REG=%1.reg
gen add_l {const4, %1.bd}, %a gen add_l {const4, %1.bd}, %a
yields %a yields %a
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
from regAregXcon %bd==0 && %sc==1 from regAregXcon %bd==0 && %sc==1
@ -1539,7 +1539,7 @@ pat lol mlu stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
with data_int with data_int
kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any) kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
gen mulu_i %1, {LOCAL, $1} gen mulu_i %1, {LOCAL, $1}
#endif TBL68020 #endif /* TBL68020 */
proc lolxxxstl example lol adi stl proc lolxxxstl example lol adi stl
with conreg_int-bconst with conreg_int-bconst
@ -2948,7 +2948,7 @@ with exact local_addr yields {LOCAL, %1.bd+$1}
with exact ext_addr yields {absolute_int, %1.bd+$1} with exact ext_addr yields {absolute_int, %1.bd+$1}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted_int, %1.reg, %1.bd+$1} with regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted_int, %1.reg, %1.bd+$1} with exact regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
with exact regAregXcon yields {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1} with exact regAregXcon yields {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1}
#ifdef FANCY_MODES #ifdef FANCY_MODES
@ -3037,7 +3037,7 @@ with exact ext_addr yields {absolute1, %1.bd}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted1, %1.reg, %1.bd} with regAcon yields {offsetted1, %1.reg, %1.bd}
with regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd} with regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted1, %1.reg, %1.bd} with exact regAcon yields {offsetted1, %1.reg, %1.bd}
with exact regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd} with exact regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#ifdef FANCY_MODES #ifdef FANCY_MODES
@ -3070,7 +3070,7 @@ with exact ext_addr yields {absolute2, %1.bd}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted2, %1.reg, %1.bd} with regAcon yields {offsetted2, %1.reg, %1.bd}
with regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd} with regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted2, %1.reg, %1.bd} with exact regAcon yields {offsetted2, %1.reg, %1.bd}
with exact regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd} with exact regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==2 #if WORD_SIZE==2
@ -3102,7 +3102,7 @@ with exact ext_addr yields {absolute4, %1.bd}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted4, %1.reg, %1.bd} with regAcon yields {offsetted4, %1.reg, %1.bd}
with regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd} with regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted4, %1.reg, %1.bd} with exact regAcon yields {offsetted4, %1.reg, %1.bd}
with exact regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd} with exact regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==4 #if WORD_SIZE==4
@ -3342,7 +3342,7 @@ with regAcon store_int
kills allexceptcon kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1} gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
#endif #endif
#else TBL68020 #else /* TBL68020 */
with exact regAcon store_int with exact regAcon store_int
kills allexceptcon kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1} gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
@ -3390,7 +3390,7 @@ with exact ext_regX store_int
kills allexceptcon kills allexceptcon
gen move %2, {abs_index_int, %1.sc, %1.xreg, %1.bd+$1} gen move %2, {abs_index_int, %1.sc, %1.xreg, %1.bd+$1}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
pat sti $1==1 pat sti $1==1
with A_REG any1 with A_REG any1
@ -3409,7 +3409,7 @@ with regAcon any1
with regAregXcon any1 with regAregXcon any1
kills allexceptcon kills allexceptcon
gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd} gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon any1 with exact regAcon any1
kills allexceptcon kills allexceptcon
gen move %2, {offsetted1, %1.reg, %1.bd} gen move %2, {offsetted1, %1.reg, %1.bd}
@ -3457,7 +3457,7 @@ with exact ext_regX any1
kills allexceptcon kills allexceptcon
gen move %2, {abs_index1, %1.sc, %1.xreg, %1.bd} gen move %2, {abs_index1, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
pat sti $1==2 pat sti $1==2
with A_REG any2 with A_REG any2
@ -3476,7 +3476,7 @@ with regAcon any2
with regAregXcon any2 with regAregXcon any2
kills allexceptcon kills allexceptcon
gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd} gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon any2 with exact regAcon any2
kills allexceptcon kills allexceptcon
gen move %2, {offsetted2, %1.reg, %1.bd} gen move %2, {offsetted2, %1.reg, %1.bd}
@ -3529,7 +3529,7 @@ with exact ext_regX any2
kills allexceptcon kills allexceptcon
gen move %2, {abs_index2, %1.sc, %1.xreg, %1.bd} gen move %2, {abs_index2, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
pat sti $1==4 pat sti $1==4
with A_REG store4-sconsts4 with A_REG store4-sconsts4
@ -3557,7 +3557,7 @@ with regAcon store4-sconsts4
with regAregXcon store4-sconsts4 with regAregXcon store4-sconsts4
kills allexceptcon kills allexceptcon
gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd} gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon store4 with exact regAcon store4
kills allexceptcon kills allexceptcon
gen move %2, {offsetted4, %1.reg, %1.bd} gen move %2, {offsetted4, %1.reg, %1.bd}
@ -3607,7 +3607,7 @@ with exact ext_regX store4
kills allexceptcon kills allexceptcon
gen move %2, {abs_index4, %1.sc, %1.xreg, %1.bd} gen move %2, {abs_index4, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat sti $1==6 pat sti $1==6
@ -3834,7 +3834,7 @@ pat mli $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4 DD_REG4 with data4 DD_REG4
gen muls_l %1, %2 yields %2 gen muls_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".mli"} gen jsr {absolute4, ".mli"}
@ -3853,12 +3853,12 @@ pat dvi $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4-sconsts4 DD_REG4 with data4-sconsts4 DD_REG4
gen divs_l %1, %2 yields %2 gen divs_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvi"} gen jsr {absolute4, ".dvi"}
yields dl1 yields dl1
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat rmi $1==2 pat rmi $1==2
@ -3878,12 +3878,12 @@ with data4-sconsts4 DD_REG4
killreg %2 killreg %2
/* !!!! contents of %2 have changed: make this known to cg */ /* !!!! contents of %2 have changed: make this known to cg */
yields %a yields %a
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvi"} gen jsr {absolute4, ".dvi"}
yields dl2 yields dl2
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat ngi $1==2 pat ngi $1==2
@ -3934,12 +3934,12 @@ pat mlu $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4-sconsts4 DD_REG4 with data4-sconsts4 DD_REG4
gen mulu_l %1, %2 yields %2 gen mulu_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".mlu"} gen jsr {absolute4, ".mlu"}
yields dl1 yields dl1
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat dvu $1==2 pat dvu $1==2
@ -3953,12 +3953,12 @@ pat dvu $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4-sconsts4 DD_REG4 with data4-sconsts4 DD_REG4
gen divu_l %1, %2 yields %2 gen divu_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvu"} gen jsr {absolute4, ".dvu"}
yields dl1 yields dl1
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat rmu $1==2 pat rmu $1==2
@ -3979,12 +3979,12 @@ with data4-sconsts4 DD_REG4
killreg %2 killreg %2
/* !!!! contents of %2 have changed: make this known to cg */ /* !!!! contents of %2 have changed: make this known to cg */
yields %a yields %a
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvu"} gen jsr {absolute4, ".dvu"}
yields dl2 yields dl2
#endif TBL68020 #endif /* TBL68020 */
pat slu leaving sli $1 pat slu leaving sli $1
@ -4400,7 +4400,7 @@ with exact LOCAL ext_regX
with exact absolute4 ext_regX with exact absolute4 ext_regX
yields {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd} yields {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
/* I WOULD ALSO LIKE THIS: /* I WOULD ALSO LIKE THIS:
* pat ads * pat ads
@ -4442,7 +4442,7 @@ with DD_REG4
gen add_l %1, %1 yields %1 gen add_l %1, %1 yields %1
#endif #endif
#endif TBL68020 #endif /* TBL68020 */
/************************************************ /************************************************
@ -5093,7 +5093,7 @@ pat lae aar $2==4 && rom($1,3)==1
pat lae aar $2==4 && nicesize(rom($1,3)) pat lae aar $2==4 && nicesize(rom($1,3))
with D_REG yields {regX, rom($1,3), %1} with D_REG yields {regX, rom($1,3), %1}
leaving ads 4 adp rom($1,3)*(0-rom($1,1)) leaving ads 4 adp rom($1,3)*(0-rom($1,1))
#else TBL68020 #else /* TBL68020 */
pat lae aar $2==4 && rom($1,3)==2 pat lae aar $2==4 && rom($1,3)==2
with DD_REG with DD_REG
gen asl_l {small_const, 1}, %1 gen asl_l {small_const, 1}, %1
@ -5111,7 +5111,7 @@ with DD_REG
gen asl_l {small_const, 3}, %1 gen asl_l {small_const, 3}, %1
yields %1 yields %1
leaving ads 4 adp (0 - rom($1,1))<<3 leaving ads 4 adp (0 - rom($1,1))<<3
#endif TBL68020 #endif /* TBL68020 */
#endif /* ARR_OPT */ #endif /* ARR_OPT */
#endif /* WORD_SIZE!=2 */ #endif /* WORD_SIZE!=2 */
@ -5928,11 +5928,11 @@ with A_REG D_REG4
pea {absolute4, 1} /* push constant 1 == ERANGE */ pea {absolute4, 1} /* push constant 1 == ERANGE */
jsr {absolute4, ".trp"} jsr {absolute4, ".trp"}
1: yields %2 1: yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".rck"} gen jsr {absolute4, ".rck"}
#endif TBL68020 #endif /* TBL68020 */
#endif /* WORD_SIZE==4 || TBL68020 */ #endif /* WORD_SIZE==4 || TBL68020 */
pat rtt leaving ret 0 pat rtt leaving ret 0
@ -6579,10 +6579,10 @@ with memory1+DD_REG
#else #else
#ifdef TBL68020 #ifdef TBL68020
extb_l {LOCAL,$4} extb_l {LOCAL,$4}
#else TBL68020 #else /* TBL68020 */
ext_w {LOCAL,$4} ext_w {LOCAL,$4}
ext_l {LOCAL,$4} ext_l {LOCAL,$4}
#endif TBL68020 #endif /* TBL68020 */
#endif #endif
pat loc loc cii $1==2 && $2==4 pat loc loc cii $1==2 && $2==4

98
mach/m68k4/ncg/table
View file

@ -200,7 +200,7 @@ regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8)
t_regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8) . t_regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8) .
t_regAcon = {A_REG reg; INT bd;} 4 cost(2,6) . t_regAcon = {A_REG reg; INT bd;} 4 cost(2,6) .
#else TBL68020 #else /* TBL68020 */
/* Part (iii) */ /* Part (iii) */
absolute4 = {ADDR bd;} 4 cost(4,7) "(" bd ")" . absolute4 = {ADDR bd;} 4 cost(4,7) "(" bd ")" .
offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) "(" bd "," reg ")" . offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) "(" bd "," reg ")" .
@ -288,7 +288,7 @@ DREG_pair = {D_REG4 reg1; D_REG4 reg2;} 8 cost(2,0) reg1 ":" reg2 .
#define t_regAregXcon regAregXcon #define t_regAregXcon regAregXcon
#define t_regAcon regAcon #define t_regAcon regAcon
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE!=2 #if WORD_SIZE!=2
#define DLOCAL LOCAL #define DLOCAL LOCAL
@ -349,7 +349,7 @@ control1 = indirect1 + offsetted1 + index_off1 + absolute1 .
alterable1 = data1 + D_REG - consts . alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG . any1 = data1 + D_REG .
#else TBL68020 #else /* TBL68020 */
data4 = D_REG4 + indirect4 + post_inc4 + pre_dec4 + index_off4 + data4 = D_REG4 + indirect4 + post_inc4 + pre_dec4 + index_off4 +
offsetted4 + OFF_off4 + OFF_indoff4 + offsetted4 + OFF_off4 + OFF_indoff4 +
@ -396,7 +396,7 @@ control1 = memory1 - (post_inc1 + pre_dec1 + consts ) .
alterable1 = data1 + D_REG - consts . alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG. /* all four above together */ any1 = data1 + D_REG. /* all four above together */
#endif TBL68020 #endif /* TBL68020 */
/* This is a common part */ /* This is a common part */
#if WORD_SIZE==2 #if WORD_SIZE==2
/* Not any4, since any is used in 'with' and not in 'kills' */ /* Not any4, since any is used in 'with' and not in 'kills' */
@ -424,7 +424,7 @@ allexceptcon = ALL - ( D_REG + A_REG + consts + dreg2 + dreg1 +
t_regAcon + t_regAregXcon ) . t_regAcon + t_regAregXcon ) .
use_index = index_off4 + index_off2 + index_off1 . use_index = index_off4 + index_off2 + index_off1 .
#else TBL68020 #else /* TBL68020 */
reg_memind4 = OFF_off4 + OFF_indoff4 + INDOFF_off4 . reg_memind4 = OFF_off4 + OFF_indoff4 + INDOFF_off4 .
memind4 = reg_memind4 + memind4 = reg_memind4 +
@ -466,7 +466,7 @@ use_indaddr = regAregXcon +
use_index = use_index4 + use_index2 + use_index1 + use_indaddr + regX . use_index = use_index4 + use_index2 + use_index1 + use_indaddr + regX .
#endif TBL68020 #endif /* TBL68020 */
/* A common part */ /* A common part */
posextern = absolute + all_indir . posextern = absolute + all_indir .
@ -513,7 +513,7 @@ test_set2 = datalt2 .
#endif #endif
test_set1 = datalt1 . test_set1 = datalt1 .
#else TBL68020 #else /* TBL68020 */
imm_cmp4 = any4 - immediate4 - A_REG . imm_cmp4 = any4 - immediate4 - A_REG .
imm_cmp2 = any2 - consts . imm_cmp2 = any2 - consts .
@ -527,15 +527,15 @@ test_set2 = data2 - consts .
#endif #endif
test_set1 = data1 - consts . test_set1 = data1 - consts .
#endif TBL68020 #endif /* TBL68020 */
test_set = test_set4 + test_set2 + test_set1 . test_set = test_set4 + test_set2 + test_set1 .
#ifndef TBL68020 #ifndef TBL68020
t_address = address + t_regAregXcon + t_regAcon . t_address = address + t_regAregXcon + t_regAcon .
#else TBL68020 #else /* TBL68020 */
#define t_address address #define t_address address
#endif TBL68020 #endif /* TBL68020 */
#if TBL68881 #if TBL68881
freg = FD_REG + FS_REG . freg = FD_REG + FS_REG .
@ -591,7 +591,7 @@ divs_l "divs.l" data4:ro, LOCAL:rw:cc cost(0,90).
divu_l "divu.l" data4:ro, LOCAL:rw:cc cost(0,78). divu_l "divu.l" data4:ro, LOCAL:rw:cc cost(0,78).
muls_l "muls.l" data4:ro, LOCAL:rw:cc cost(0,44). muls_l "muls.l" data4:ro, LOCAL:rw:cc cost(0,44).
mulu_l "mulu.l" data4:ro, LOCAL:rw:cc cost(0,44). mulu_l "mulu.l" data4:ro, LOCAL:rw:cc cost(0,44).
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
add_l "add.l" any4:ro, D_REG4:rw:cc cost(2,3). add_l "add.l" any4:ro, D_REG4:rw:cc cost(2,3).
@ -777,9 +777,9 @@ extb_l "extb.l" extend1_4+D_REG+LOCAL:rw:cc cost(2,4).
muls_l "muls.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44). muls_l "muls.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
mulu_l "mulu.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44). mulu_l "mulu.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
#endif #endif
#else TBL68020 #else /* TBL68020 */
pea address+control4 cost(2,4). pea address+control4 cost(2,4).
#endif TBL68020 #endif /* TBL68020 */
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* Extra pseudo instruction; it just kills a D_REG; * Extra pseudo instruction; it just kills a D_REG;
@ -888,7 +888,7 @@ from t_regAcon sfit(%bd, 16) to A_REG+areg
from t_regAcon to A_REG+areg from t_regAcon to A_REG+areg
gen move_l %1.reg, %2 gen move_l %1.reg, %2
add_l {const4, %1.bd}, %2 add_l {const4, %1.bd}, %2
#endif TBL68020 #endif /* TBL68020 */
from address - ext_addr to A_REG+areg from address - ext_addr to A_REG+areg
gen lea %1, %2 gen lea %1, %2
@ -977,7 +977,7 @@ from t_regAcon sfit(%bd, 16) to STACK
from t_regAcon to STACK from t_regAcon to STACK
gen move_l %1.reg, {pre_dec4, sp} gen move_l %1.reg, {pre_dec4, sp}
add_l {const4, %1.bd}, {indirect4, sp} add_l {const4, %1.bd}, {indirect4, sp}
#endif TBL68020 #endif /* TBL68020 */
from A_REG to STACK from A_REG to STACK
gen pea {indirect4, %1} gen pea {indirect4, %1}
@ -1059,7 +1059,7 @@ from extend1 to STACK
#ifdef TBL68020 #ifdef TBL68020
from regX to STACK from regX to STACK
gen pea %1 gen pea %1
#endif TBL68020 #endif /* TBL68020 */
/* This last stackingrule is never used: whenever regX is put on /* This last stackingrule is never used: whenever regX is put on
* the fakestack, some em-instuctions are left that remove it * the fakestack, some em-instuctions are left that remove it
* immediately. However cgg complained about not having a * immediately. However cgg complained about not having a
@ -1138,7 +1138,7 @@ from t_regAcon
uses reusing %1, AA_REG=%1.reg uses reusing %1, AA_REG=%1.reg
gen add_l {const4, %1.bd}, %a gen add_l {const4, %1.bd}, %a
yields %a yields %a
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
from regAregXcon %bd==0 && %sc==1 from regAregXcon %bd==0 && %sc==1
@ -1539,7 +1539,7 @@ pat lol mlu stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
with data_int with data_int
kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any) kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
gen mulu_i %1, {LOCAL, $1} gen mulu_i %1, {LOCAL, $1}
#endif TBL68020 #endif /* TBL68020 */
proc lolxxxstl example lol adi stl proc lolxxxstl example lol adi stl
with conreg_int-bconst with conreg_int-bconst
@ -2948,7 +2948,7 @@ with exact local_addr yields {LOCAL, %1.bd+$1}
with exact ext_addr yields {absolute_int, %1.bd+$1} with exact ext_addr yields {absolute_int, %1.bd+$1}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted_int, %1.reg, %1.bd+$1} with regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted_int, %1.reg, %1.bd+$1} with exact regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
with exact regAregXcon yields {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1} with exact regAregXcon yields {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1}
#ifdef FANCY_MODES #ifdef FANCY_MODES
@ -3037,7 +3037,7 @@ with exact ext_addr yields {absolute1, %1.bd}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted1, %1.reg, %1.bd} with regAcon yields {offsetted1, %1.reg, %1.bd}
with regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd} with regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted1, %1.reg, %1.bd} with exact regAcon yields {offsetted1, %1.reg, %1.bd}
with exact regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd} with exact regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#ifdef FANCY_MODES #ifdef FANCY_MODES
@ -3070,7 +3070,7 @@ with exact ext_addr yields {absolute2, %1.bd}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted2, %1.reg, %1.bd} with regAcon yields {offsetted2, %1.reg, %1.bd}
with regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd} with regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted2, %1.reg, %1.bd} with exact regAcon yields {offsetted2, %1.reg, %1.bd}
with exact regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd} with exact regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==2 #if WORD_SIZE==2
@ -3102,7 +3102,7 @@ with exact ext_addr yields {absolute4, %1.bd}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted4, %1.reg, %1.bd} with regAcon yields {offsetted4, %1.reg, %1.bd}
with regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd} with regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted4, %1.reg, %1.bd} with exact regAcon yields {offsetted4, %1.reg, %1.bd}
with exact regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd} with exact regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==4 #if WORD_SIZE==4
@ -3342,7 +3342,7 @@ with regAcon store_int
kills allexceptcon kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1} gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
#endif #endif
#else TBL68020 #else /* TBL68020 */
with exact regAcon store_int with exact regAcon store_int
kills allexceptcon kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1} gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
@ -3390,7 +3390,7 @@ with exact ext_regX store_int
kills allexceptcon kills allexceptcon
gen move %2, {abs_index_int, %1.sc, %1.xreg, %1.bd+$1} gen move %2, {abs_index_int, %1.sc, %1.xreg, %1.bd+$1}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
pat sti $1==1 pat sti $1==1
with A_REG any1 with A_REG any1
@ -3409,7 +3409,7 @@ with regAcon any1
with regAregXcon any1 with regAregXcon any1
kills allexceptcon kills allexceptcon
gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd} gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon any1 with exact regAcon any1
kills allexceptcon kills allexceptcon
gen move %2, {offsetted1, %1.reg, %1.bd} gen move %2, {offsetted1, %1.reg, %1.bd}
@ -3457,7 +3457,7 @@ with exact ext_regX any1
kills allexceptcon kills allexceptcon
gen move %2, {abs_index1, %1.sc, %1.xreg, %1.bd} gen move %2, {abs_index1, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
pat sti $1==2 pat sti $1==2
with A_REG any2 with A_REG any2
@ -3476,7 +3476,7 @@ with regAcon any2
with regAregXcon any2 with regAregXcon any2
kills allexceptcon kills allexceptcon
gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd} gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon any2 with exact regAcon any2
kills allexceptcon kills allexceptcon
gen move %2, {offsetted2, %1.reg, %1.bd} gen move %2, {offsetted2, %1.reg, %1.bd}
@ -3529,7 +3529,7 @@ with exact ext_regX any2
kills allexceptcon kills allexceptcon
gen move %2, {abs_index2, %1.sc, %1.xreg, %1.bd} gen move %2, {abs_index2, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
pat sti $1==4 pat sti $1==4
with A_REG store4-sconsts4 with A_REG store4-sconsts4
@ -3557,7 +3557,7 @@ with regAcon store4-sconsts4
with regAregXcon store4-sconsts4 with regAregXcon store4-sconsts4
kills allexceptcon kills allexceptcon
gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd} gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon store4 with exact regAcon store4
kills allexceptcon kills allexceptcon
gen move %2, {offsetted4, %1.reg, %1.bd} gen move %2, {offsetted4, %1.reg, %1.bd}
@ -3607,7 +3607,7 @@ with exact ext_regX store4
kills allexceptcon kills allexceptcon
gen move %2, {abs_index4, %1.sc, %1.xreg, %1.bd} gen move %2, {abs_index4, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat sti $1==6 pat sti $1==6
@ -3834,7 +3834,7 @@ pat mli $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4 DD_REG4 with data4 DD_REG4
gen muls_l %1, %2 yields %2 gen muls_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".mli"} gen jsr {absolute4, ".mli"}
@ -3853,12 +3853,12 @@ pat dvi $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4-sconsts4 DD_REG4 with data4-sconsts4 DD_REG4
gen divs_l %1, %2 yields %2 gen divs_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvi"} gen jsr {absolute4, ".dvi"}
yields dl1 yields dl1
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat rmi $1==2 pat rmi $1==2
@ -3878,12 +3878,12 @@ with data4-sconsts4 DD_REG4
killreg %2 killreg %2
/* !!!! contents of %2 have changed: make this known to cg */ /* !!!! contents of %2 have changed: make this known to cg */
yields %a yields %a
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvi"} gen jsr {absolute4, ".dvi"}
yields dl2 yields dl2
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat ngi $1==2 pat ngi $1==2
@ -3934,12 +3934,12 @@ pat mlu $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4-sconsts4 DD_REG4 with data4-sconsts4 DD_REG4
gen mulu_l %1, %2 yields %2 gen mulu_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".mlu"} gen jsr {absolute4, ".mlu"}
yields dl1 yields dl1
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat dvu $1==2 pat dvu $1==2
@ -3953,12 +3953,12 @@ pat dvu $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4-sconsts4 DD_REG4 with data4-sconsts4 DD_REG4
gen divu_l %1, %2 yields %2 gen divu_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvu"} gen jsr {absolute4, ".dvu"}
yields dl1 yields dl1
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat rmu $1==2 pat rmu $1==2
@ -3979,12 +3979,12 @@ with data4-sconsts4 DD_REG4
killreg %2 killreg %2
/* !!!! contents of %2 have changed: make this known to cg */ /* !!!! contents of %2 have changed: make this known to cg */
yields %a yields %a
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvu"} gen jsr {absolute4, ".dvu"}
yields dl2 yields dl2
#endif TBL68020 #endif /* TBL68020 */
pat slu leaving sli $1 pat slu leaving sli $1
@ -4400,7 +4400,7 @@ with exact LOCAL ext_regX
with exact absolute4 ext_regX with exact absolute4 ext_regX
yields {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd} yields {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
/* I WOULD ALSO LIKE THIS: /* I WOULD ALSO LIKE THIS:
* pat ads * pat ads
@ -4442,7 +4442,7 @@ with DD_REG4
gen add_l %1, %1 yields %1 gen add_l %1, %1 yields %1
#endif #endif
#endif TBL68020 #endif /* TBL68020 */
/************************************************ /************************************************
@ -5093,7 +5093,7 @@ pat lae aar $2==4 && rom($1,3)==1
pat lae aar $2==4 && nicesize(rom($1,3)) pat lae aar $2==4 && nicesize(rom($1,3))
with D_REG yields {regX, rom($1,3), %1} with D_REG yields {regX, rom($1,3), %1}
leaving ads 4 adp rom($1,3)*(0-rom($1,1)) leaving ads 4 adp rom($1,3)*(0-rom($1,1))
#else TBL68020 #else /* TBL68020 */
pat lae aar $2==4 && rom($1,3)==2 pat lae aar $2==4 && rom($1,3)==2
with DD_REG with DD_REG
gen asl_l {small_const, 1}, %1 gen asl_l {small_const, 1}, %1
@ -5111,7 +5111,7 @@ with DD_REG
gen asl_l {small_const, 3}, %1 gen asl_l {small_const, 3}, %1
yields %1 yields %1
leaving ads 4 adp (0 - rom($1,1))<<3 leaving ads 4 adp (0 - rom($1,1))<<3
#endif TBL68020 #endif /* TBL68020 */
#endif /* ARR_OPT */ #endif /* ARR_OPT */
#endif /* WORD_SIZE!=2 */ #endif /* WORD_SIZE!=2 */
@ -5928,11 +5928,11 @@ with A_REG D_REG4
pea {absolute4, 1} /* push constant 1 == ERANGE */ pea {absolute4, 1} /* push constant 1 == ERANGE */
jsr {absolute4, ".trp"} jsr {absolute4, ".trp"}
1: yields %2 1: yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".rck"} gen jsr {absolute4, ".rck"}
#endif TBL68020 #endif /* TBL68020 */
#endif /* WORD_SIZE==4 || TBL68020 */ #endif /* WORD_SIZE==4 || TBL68020 */
pat rtt leaving ret 0 pat rtt leaving ret 0
@ -6579,10 +6579,10 @@ with memory1+DD_REG
#else #else
#ifdef TBL68020 #ifdef TBL68020
extb_l {LOCAL,$4} extb_l {LOCAL,$4}
#else TBL68020 #else /* TBL68020 */
ext_w {LOCAL,$4} ext_w {LOCAL,$4}
ext_l {LOCAL,$4} ext_l {LOCAL,$4}
#endif TBL68020 #endif /* TBL68020 */
#endif #endif
pat loc loc cii $1==2 && $2==4 pat loc loc cii $1==2 && $2==4

98
mach/moon3/ncg/table
View file

@ -200,7 +200,7 @@ regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8)
t_regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8) . t_regAregXcon = {A_REG reg; D_REG4 xreg; INT sc; INT bd;} 4 cost(2,8) .
t_regAcon = {A_REG reg; INT bd;} 4 cost(2,6) . t_regAcon = {A_REG reg; INT bd;} 4 cost(2,6) .
#else TBL68020 #else /* TBL68020 */
/* Part (iii) */ /* Part (iii) */
absolute4 = {ADDR bd;} 4 cost(4,7) "(" bd ")" . absolute4 = {ADDR bd;} 4 cost(4,7) "(" bd ")" .
offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) "(" bd "," reg ")" . offsetted4 = {A_REG reg; INT bd;} 4 cost(2,6) "(" bd "," reg ")" .
@ -288,7 +288,7 @@ DREG_pair = {D_REG4 reg1; D_REG4 reg2;} 8 cost(2,0) reg1 ":" reg2 .
#define t_regAregXcon regAregXcon #define t_regAregXcon regAregXcon
#define t_regAcon regAcon #define t_regAcon regAcon
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE!=2 #if WORD_SIZE!=2
#define DLOCAL LOCAL #define DLOCAL LOCAL
@ -349,7 +349,7 @@ control1 = indirect1 + offsetted1 + index_off1 + absolute1 .
alterable1 = data1 + D_REG - consts . alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG . any1 = data1 + D_REG .
#else TBL68020 #else /* TBL68020 */
data4 = D_REG4 + indirect4 + post_inc4 + pre_dec4 + index_off4 + data4 = D_REG4 + indirect4 + post_inc4 + pre_dec4 + index_off4 +
offsetted4 + OFF_off4 + OFF_indoff4 + offsetted4 + OFF_off4 + OFF_indoff4 +
@ -396,7 +396,7 @@ control1 = memory1 - (post_inc1 + pre_dec1 + consts ) .
alterable1 = data1 + D_REG - consts . alterable1 = data1 + D_REG - consts .
any1 = data1 + D_REG. /* all four above together */ any1 = data1 + D_REG. /* all four above together */
#endif TBL68020 #endif /* TBL68020 */
/* This is a common part */ /* This is a common part */
#if WORD_SIZE==2 #if WORD_SIZE==2
/* Not any4, since any is used in 'with' and not in 'kills' */ /* Not any4, since any is used in 'with' and not in 'kills' */
@ -424,7 +424,7 @@ allexceptcon = ALL - ( D_REG + A_REG + consts + dreg2 + dreg1 +
t_regAcon + t_regAregXcon ) . t_regAcon + t_regAregXcon ) .
use_index = index_off4 + index_off2 + index_off1 . use_index = index_off4 + index_off2 + index_off1 .
#else TBL68020 #else /* TBL68020 */
reg_memind4 = OFF_off4 + OFF_indoff4 + INDOFF_off4 . reg_memind4 = OFF_off4 + OFF_indoff4 + INDOFF_off4 .
memind4 = reg_memind4 + memind4 = reg_memind4 +
@ -466,7 +466,7 @@ use_indaddr = regAregXcon +
use_index = use_index4 + use_index2 + use_index1 + use_indaddr + regX . use_index = use_index4 + use_index2 + use_index1 + use_indaddr + regX .
#endif TBL68020 #endif /* TBL68020 */
/* A common part */ /* A common part */
posextern = absolute + all_indir . posextern = absolute + all_indir .
@ -513,7 +513,7 @@ test_set2 = datalt2 .
#endif #endif
test_set1 = datalt1 . test_set1 = datalt1 .
#else TBL68020 #else /* TBL68020 */
imm_cmp4 = any4 - immediate4 - A_REG . imm_cmp4 = any4 - immediate4 - A_REG .
imm_cmp2 = any2 - consts . imm_cmp2 = any2 - consts .
@ -527,15 +527,15 @@ test_set2 = data2 - consts .
#endif #endif
test_set1 = data1 - consts . test_set1 = data1 - consts .
#endif TBL68020 #endif /* TBL68020 */
test_set = test_set4 + test_set2 + test_set1 . test_set = test_set4 + test_set2 + test_set1 .
#ifndef TBL68020 #ifndef TBL68020
t_address = address + t_regAregXcon + t_regAcon . t_address = address + t_regAregXcon + t_regAcon .
#else TBL68020 #else /* TBL68020 */
#define t_address address #define t_address address
#endif TBL68020 #endif /* TBL68020 */
#if TBL68881 #if TBL68881
freg = FD_REG + FS_REG . freg = FD_REG + FS_REG .
@ -591,7 +591,7 @@ divs_l "divs.l" data4:ro, LOCAL:rw:cc cost(0,90).
divu_l "divu.l" data4:ro, LOCAL:rw:cc cost(0,78). divu_l "divu.l" data4:ro, LOCAL:rw:cc cost(0,78).
muls_l "muls.l" data4:ro, LOCAL:rw:cc cost(0,44). muls_l "muls.l" data4:ro, LOCAL:rw:cc cost(0,44).
mulu_l "mulu.l" data4:ro, LOCAL:rw:cc cost(0,44). mulu_l "mulu.l" data4:ro, LOCAL:rw:cc cost(0,44).
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
add_l "add.l" any4:ro, D_REG4:rw:cc cost(2,3). add_l "add.l" any4:ro, D_REG4:rw:cc cost(2,3).
@ -777,9 +777,9 @@ extb_l "extb.l" extend1_4+D_REG+LOCAL:rw:cc cost(2,4).
muls_l "muls.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44). muls_l "muls.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
mulu_l "mulu.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44). mulu_l "mulu.l" data4:ro, D_REG+LOCAL:rw:cc cost(2,44).
#endif #endif
#else TBL68020 #else /* TBL68020 */
pea address+control4 cost(2,4). pea address+control4 cost(2,4).
#endif TBL68020 #endif /* TBL68020 */
/* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! /* !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
* Extra pseudo instruction; it just kills a D_REG; * Extra pseudo instruction; it just kills a D_REG;
@ -888,7 +888,7 @@ from t_regAcon sfit(%bd, 16) to A_REG+areg
from t_regAcon to A_REG+areg from t_regAcon to A_REG+areg
gen move_l %1.reg, %2 gen move_l %1.reg, %2
add_l {const4, %1.bd}, %2 add_l {const4, %1.bd}, %2
#endif TBL68020 #endif /* TBL68020 */
from address - ext_addr to A_REG+areg from address - ext_addr to A_REG+areg
gen lea %1, %2 gen lea %1, %2
@ -977,7 +977,7 @@ from t_regAcon sfit(%bd, 16) to STACK
from t_regAcon to STACK from t_regAcon to STACK
gen move_l %1.reg, {pre_dec4, sp} gen move_l %1.reg, {pre_dec4, sp}
add_l {const4, %1.bd}, {indirect4, sp} add_l {const4, %1.bd}, {indirect4, sp}
#endif TBL68020 #endif /* TBL68020 */
from A_REG to STACK from A_REG to STACK
gen pea {indirect4, %1} gen pea {indirect4, %1}
@ -1059,7 +1059,7 @@ from extend1 to STACK
#ifdef TBL68020 #ifdef TBL68020
from regX to STACK from regX to STACK
gen pea %1 gen pea %1
#endif TBL68020 #endif /* TBL68020 */
/* This last stackingrule is never used: whenever regX is put on /* This last stackingrule is never used: whenever regX is put on
* the fakestack, some em-instuctions are left that remove it * the fakestack, some em-instuctions are left that remove it
* immediately. However cgg complained about not having a * immediately. However cgg complained about not having a
@ -1138,7 +1138,7 @@ from t_regAcon
uses reusing %1, AA_REG=%1.reg uses reusing %1, AA_REG=%1.reg
gen add_l {const4, %1.bd}, %a gen add_l {const4, %1.bd}, %a
yields %a yields %a
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
from regAregXcon %bd==0 && %sc==1 from regAregXcon %bd==0 && %sc==1
@ -1539,7 +1539,7 @@ pat lol mlu stl $1==$3 && $2==WORD_SIZE && inreg($1)==reg_any
with data_int with data_int
kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any) kills regvar($1, reg_any), use_index %xreg==regvar($1, reg_any)
gen mulu_i %1, {LOCAL, $1} gen mulu_i %1, {LOCAL, $1}
#endif TBL68020 #endif /* TBL68020 */
proc lolxxxstl example lol adi stl proc lolxxxstl example lol adi stl
with conreg_int-bconst with conreg_int-bconst
@ -2948,7 +2948,7 @@ with exact local_addr yields {LOCAL, %1.bd+$1}
with exact ext_addr yields {absolute_int, %1.bd+$1} with exact ext_addr yields {absolute_int, %1.bd+$1}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted_int, %1.reg, %1.bd+$1} with regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted_int, %1.reg, %1.bd+$1} with exact regAcon yields {offsetted_int, %1.reg, %1.bd+$1}
with exact regAregXcon yields {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1} with exact regAregXcon yields {index_off_int, %1.reg, %1.xreg, %1.sc, %1.bd+$1}
#ifdef FANCY_MODES #ifdef FANCY_MODES
@ -3037,7 +3037,7 @@ with exact ext_addr yields {absolute1, %1.bd}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted1, %1.reg, %1.bd} with regAcon yields {offsetted1, %1.reg, %1.bd}
with regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd} with regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted1, %1.reg, %1.bd} with exact regAcon yields {offsetted1, %1.reg, %1.bd}
with exact regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd} with exact regAregXcon yields {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#ifdef FANCY_MODES #ifdef FANCY_MODES
@ -3070,7 +3070,7 @@ with exact ext_addr yields {absolute2, %1.bd}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted2, %1.reg, %1.bd} with regAcon yields {offsetted2, %1.reg, %1.bd}
with regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd} with regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted2, %1.reg, %1.bd} with exact regAcon yields {offsetted2, %1.reg, %1.bd}
with exact regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd} with exact regAregXcon yields {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==2 #if WORD_SIZE==2
@ -3102,7 +3102,7 @@ with exact ext_addr yields {absolute4, %1.bd}
#ifndef TBL68020 #ifndef TBL68020
with regAcon yields {offsetted4, %1.reg, %1.bd} with regAcon yields {offsetted4, %1.reg, %1.bd}
with regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd} with regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon yields {offsetted4, %1.reg, %1.bd} with exact regAcon yields {offsetted4, %1.reg, %1.bd}
with exact regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd} with exact regAregXcon yields {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#if WORD_SIZE==4 #if WORD_SIZE==4
@ -3342,7 +3342,7 @@ with regAcon store_int
kills allexceptcon kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1} gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
#endif #endif
#else TBL68020 #else /* TBL68020 */
with exact regAcon store_int with exact regAcon store_int
kills allexceptcon kills allexceptcon
gen move %2, {offsetted_int, %1.reg, %1.bd+$1} gen move %2, {offsetted_int, %1.reg, %1.bd+$1}
@ -3390,7 +3390,7 @@ with exact ext_regX store_int
kills allexceptcon kills allexceptcon
gen move %2, {abs_index_int, %1.sc, %1.xreg, %1.bd+$1} gen move %2, {abs_index_int, %1.sc, %1.xreg, %1.bd+$1}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
pat sti $1==1 pat sti $1==1
with A_REG any1 with A_REG any1
@ -3409,7 +3409,7 @@ with regAcon any1
with regAregXcon any1 with regAregXcon any1
kills allexceptcon kills allexceptcon
gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd} gen move %2, {index_off1, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon any1 with exact regAcon any1
kills allexceptcon kills allexceptcon
gen move %2, {offsetted1, %1.reg, %1.bd} gen move %2, {offsetted1, %1.reg, %1.bd}
@ -3457,7 +3457,7 @@ with exact ext_regX any1
kills allexceptcon kills allexceptcon
gen move %2, {abs_index1, %1.sc, %1.xreg, %1.bd} gen move %2, {abs_index1, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
pat sti $1==2 pat sti $1==2
with A_REG any2 with A_REG any2
@ -3476,7 +3476,7 @@ with regAcon any2
with regAregXcon any2 with regAregXcon any2
kills allexceptcon kills allexceptcon
gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd} gen move %2, {index_off2, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon any2 with exact regAcon any2
kills allexceptcon kills allexceptcon
gen move %2, {offsetted2, %1.reg, %1.bd} gen move %2, {offsetted2, %1.reg, %1.bd}
@ -3529,7 +3529,7 @@ with exact ext_regX any2
kills allexceptcon kills allexceptcon
gen move %2, {abs_index2, %1.sc, %1.xreg, %1.bd} gen move %2, {abs_index2, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
pat sti $1==4 pat sti $1==4
with A_REG store4-sconsts4 with A_REG store4-sconsts4
@ -3557,7 +3557,7 @@ with regAcon store4-sconsts4
with regAregXcon store4-sconsts4 with regAregXcon store4-sconsts4
kills allexceptcon kills allexceptcon
gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd} gen move %2, {index_off4, %1.reg, %1.xreg, %1.sc, %1.bd}
#else TBL68020 #else /* TBL68020 */
with exact regAcon store4 with exact regAcon store4
kills allexceptcon kills allexceptcon
gen move %2, {offsetted4, %1.reg, %1.bd} gen move %2, {offsetted4, %1.reg, %1.bd}
@ -3607,7 +3607,7 @@ with exact ext_regX store4
kills allexceptcon kills allexceptcon
gen move %2, {abs_index4, %1.sc, %1.xreg, %1.bd} gen move %2, {abs_index4, %1.sc, %1.xreg, %1.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat sti $1==6 pat sti $1==6
@ -3834,7 +3834,7 @@ pat mli $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4 DD_REG4 with data4 DD_REG4
gen muls_l %1, %2 yields %2 gen muls_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".mli"} gen jsr {absolute4, ".mli"}
@ -3853,12 +3853,12 @@ pat dvi $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4-sconsts4 DD_REG4 with data4-sconsts4 DD_REG4
gen divs_l %1, %2 yields %2 gen divs_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvi"} gen jsr {absolute4, ".dvi"}
yields dl1 yields dl1
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat rmi $1==2 pat rmi $1==2
@ -3878,12 +3878,12 @@ with data4-sconsts4 DD_REG4
killreg %2 killreg %2
/* !!!! contents of %2 have changed: make this known to cg */ /* !!!! contents of %2 have changed: make this known to cg */
yields %a yields %a
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvi"} gen jsr {absolute4, ".dvi"}
yields dl2 yields dl2
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat ngi $1==2 pat ngi $1==2
@ -3934,12 +3934,12 @@ pat mlu $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4-sconsts4 DD_REG4 with data4-sconsts4 DD_REG4
gen mulu_l %1, %2 yields %2 gen mulu_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".mlu"} gen jsr {absolute4, ".mlu"}
yields dl1 yields dl1
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat dvu $1==2 pat dvu $1==2
@ -3953,12 +3953,12 @@ pat dvu $1==4
#ifdef TBL68020 #ifdef TBL68020
with data4-sconsts4 DD_REG4 with data4-sconsts4 DD_REG4
gen divu_l %1, %2 yields %2 gen divu_l %1, %2 yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvu"} gen jsr {absolute4, ".dvu"}
yields dl1 yields dl1
#endif TBL68020 #endif /* TBL68020 */
#if WORD_SIZE==2 #if WORD_SIZE==2
pat rmu $1==2 pat rmu $1==2
@ -3979,12 +3979,12 @@ with data4-sconsts4 DD_REG4
killreg %2 killreg %2
/* !!!! contents of %2 have changed: make this known to cg */ /* !!!! contents of %2 have changed: make this known to cg */
yields %a yields %a
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".dvu"} gen jsr {absolute4, ".dvu"}
yields dl2 yields dl2
#endif TBL68020 #endif /* TBL68020 */
pat slu leaving sli $1 pat slu leaving sli $1
@ -4400,7 +4400,7 @@ with exact LOCAL ext_regX
with exact absolute4 ext_regX with exact absolute4 ext_regX
yields {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd} yields {abs_regXcon, %2.sc, %2.xreg, %1.bd, %2.bd}
#endif /* FANCY_MODES */ #endif /* FANCY_MODES */
#endif TBL68020 #endif /* TBL68020 */
/* I WOULD ALSO LIKE THIS: /* I WOULD ALSO LIKE THIS:
* pat ads * pat ads
@ -4442,7 +4442,7 @@ with DD_REG4
gen add_l %1, %1 yields %1 gen add_l %1, %1 yields %1
#endif #endif
#endif TBL68020 #endif /* TBL68020 */
/************************************************ /************************************************
@ -5093,7 +5093,7 @@ pat lae aar $2==4 && rom($1,3)==1
pat lae aar $2==4 && nicesize(rom($1,3)) pat lae aar $2==4 && nicesize(rom($1,3))
with D_REG yields {regX, rom($1,3), %1} with D_REG yields {regX, rom($1,3), %1}
leaving ads 4 adp rom($1,3)*(0-rom($1,1)) leaving ads 4 adp rom($1,3)*(0-rom($1,1))
#else TBL68020 #else /* TBL68020 */
pat lae aar $2==4 && rom($1,3)==2 pat lae aar $2==4 && rom($1,3)==2
with DD_REG with DD_REG
gen asl_l {small_const, 1}, %1 gen asl_l {small_const, 1}, %1
@ -5111,7 +5111,7 @@ with DD_REG
gen asl_l {small_const, 3}, %1 gen asl_l {small_const, 3}, %1
yields %1 yields %1
leaving ads 4 adp (0 - rom($1,1))<<3 leaving ads 4 adp (0 - rom($1,1))<<3
#endif TBL68020 #endif /* TBL68020 */
#endif /* ARR_OPT */ #endif /* ARR_OPT */
#endif /* WORD_SIZE!=2 */ #endif /* WORD_SIZE!=2 */
@ -5928,11 +5928,11 @@ with A_REG D_REG4
pea {absolute4, 1} /* push constant 1 == ERANGE */ pea {absolute4, 1} /* push constant 1 == ERANGE */
jsr {absolute4, ".trp"} jsr {absolute4, ".trp"}
1: yields %2 1: yields %2
#else TBL68020 #else /* TBL68020 */
with STACK with STACK
kills ALL kills ALL
gen jsr {absolute4, ".rck"} gen jsr {absolute4, ".rck"}
#endif TBL68020 #endif /* TBL68020 */
#endif /* WORD_SIZE==4 || TBL68020 */ #endif /* WORD_SIZE==4 || TBL68020 */
pat rtt leaving ret 0 pat rtt leaving ret 0
@ -6579,10 +6579,10 @@ with memory1+DD_REG
#else #else
#ifdef TBL68020 #ifdef TBL68020
extb_l {LOCAL,$4} extb_l {LOCAL,$4}
#else TBL68020 #else /* TBL68020 */
ext_w {LOCAL,$4} ext_w {LOCAL,$4}
ext_l {LOCAL,$4} ext_l {LOCAL,$4}
#endif TBL68020 #endif /* TBL68020 */
#endif #endif
pat loc loc cii $1==2 && $2==4 pat loc loc cii $1==2 && $2==4

4
mach/pdp/cg/table
View file

@ -40,10 +40,10 @@
#ifdef REGPATCH #ifdef REGPATCH
#define SL 8 #define SL 8
#define SSL "010" #define SSL "010"
#else REGPATCH #else /* REGPATCH */
#define SL 4 #define SL 4
#define SSL "4" #define SSL "4"
#endif REGPATCH #endif /* REGPATCH */
#define NC nocoercions: #define NC nocoercions:

6
mach/proto/as/comm0.h
View file

@ -68,8 +68,8 @@
#ifndef ASLD #ifndef ASLD
#ifndef RELOCATION #ifndef RELOCATION
separate linker only possible if relocation info produced separate linker only possible if relocation info produced
#endif RELOCATION #endif /* RELOCATION */
#endif ASLD #endif /* ASLD */
#ifndef DEBUG #ifndef DEBUG
#define DEBUG 1 #define DEBUG 1
@ -124,7 +124,7 @@ _include <signal.h>
#else #else
#define PASS_SYMB 1 #define PASS_SYMB 1
#define PASS_RELO 1 #define PASS_RELO 1
#endif THREE_PASS #endif /* THREE_PASS */
#ifdef ASLD #ifdef ASLD
#define RELOMOVE(a,b) /* empty */ #define RELOMOVE(a,b) /* empty */

4
mach/proto/as/comm1.h
View file

@ -42,11 +42,11 @@ extern short dflag; /* -d option (list mode) */
#ifdef ASLD #ifdef ASLD
#ifdef RELOCATION #ifdef RELOCATION
extern short rflag; /* -r option (relocation info) */ extern short rflag; /* -r option (relocation info) */
#endif RELOCATION #endif /* RELOCATION */
#else #else
#define rflag 1 #define rflag 1
extern valu_t relonami; extern valu_t relonami;
#endif ASLD #endif /* ASLD */
#ifdef THREE_PASS #ifdef THREE_PASS
extern short bflag; /* -b option (no optimizations) */ extern short bflag; /* -b option (no optimizations) */

2
mach/proto/as/comm2.y
View file

@ -96,7 +96,7 @@ static item_t *last_it, *o_it;
else if (listtemp) { listflag = listtemp; listeoln = 1; } else if (listtemp) { listflag = listtemp; listeoln = 1; }
#else #else
#define LISTLINE(n) /* empty */ #define LISTLINE(n) /* empty */
#endif LISTING #endif /* LISTING */
#ifdef ASLD #ifdef ASLD
#define RELODONE /* empty */ #define RELODONE /* empty */

18
mach/proto/as/comm4.c
View file

@ -93,8 +93,8 @@ char **argv;
#ifdef RELOCATION #ifdef RELOCATION
#ifdef ASLD #ifdef ASLD
rflag = 1; rflag = 1;
#endif ASLD #endif /* ASLD */
#endif RELOCATION #endif /* RELOCATION */
break; break;
case 'b': case 'b':
#ifdef THREE_PASS #ifdef THREE_PASS
@ -115,7 +115,7 @@ char **argv;
#ifdef RELOCATION #ifdef RELOCATION
if (rflag) if (rflag)
sflag |= SYM_SCT; sflag |= SYM_SCT;
#endif RELOCATION #endif /* RELOCATION */
pass_1(argc, argv); pass_1(argc, argv);
#ifdef THREE_PASS #ifdef THREE_PASS
pass_23(PASS_2); pass_23(PASS_2);
@ -304,7 +304,7 @@ needed()
#endif #endif
return(need); return(need);
} }
#endif ASLD #endif /* ASLD */
parse(s) parse(s)
char *s; char *s;
@ -423,7 +423,7 @@ pass_23(n)
machstart(n); machstart(n);
#ifndef ASLD #ifndef ASLD
newmodule(modulename); newmodule(modulename);
#endif ASLD #endif /* ASLD */
ffreopen(temppath, tempfile); ffreopen(temppath, tempfile);
yyparse(); yyparse();
commfinish(); commfinish();
@ -534,12 +534,12 @@ commfinish()
0, 0,
load(ip) load(ip)
); );
#else not ASLD #else /* not ASLD */
#ifdef THREE_PASS #ifdef THREE_PASS
if (pass == PASS_2) { if (pass == PASS_2) {
cp->c_size -= sp->s_gain; cp->c_size -= sp->s_gain;
} }
#endif THREE_PASS #endif /* THREE_PASS */
} }
if (pass == PASS_1) cp->c_size = ip->i_valu; if (pass == PASS_1) cp->c_size = ip->i_valu;
if (PASS_SYMB) { if (PASS_SYMB) {
@ -553,7 +553,7 @@ commfinish()
cp->c_size cp->c_size
); );
} }
#endif not ASLD #endif /* not ASLD */
} }
if (PASS_SYMB == 0) if (PASS_SYMB == 0)
return; return;
@ -578,7 +578,7 @@ commfinish()
(valu_t)0 (valu_t)0
); );
} }
#endif not ASLD #endif /* not ASLD */
/* /*
* produce symbol table entries for sections * produce symbol table entries for sections
*/ */

8
mach/proto/as/comm6.c
View file

@ -26,7 +26,7 @@ register int typ;
typ = S_VAR; typ = S_VAR;
else if (pass == PASS_2 && (ip->i_type & S_TYP) == S_UND) else if (pass == PASS_2 && (ip->i_type & S_TYP) == S_UND)
ip->i_type |= typ; ip->i_type |= typ;
#endif THREE_PASS #endif /* THREE_PASS */
if (typ == S_UND) if (typ == S_UND)
serror("illegal equate"); serror("illegal equate");
if (pass == PASS_3) if (pass == PASS_3)
@ -40,7 +40,7 @@ register item_t *ip;
register flag; register flag;
#ifdef GENLAB #ifdef GENLAB
static char genlab[] = GENLAB; static char genlab[] = GENLAB;
#endif GENLAB #endif /* GENLAB */
if (pass == PASS_1) { if (pass == PASS_1) {
/* printf("declare %s: %o\n", ip->i_name, typ); */ /* printf("declare %s: %o\n", ip->i_name, typ); */
@ -59,12 +59,12 @@ register item_t *ip;
flag = SYM_LOC; flag = SYM_LOC;
#else #else
flag = SYM_EXT|SYM_LOC; /* S_EXT not stable in PASS_1 */ flag = SYM_EXT|SYM_LOC; /* S_EXT not stable in PASS_1 */
#endif THREE_PASS #endif /* THREE_PASS */
#ifdef GENLAB #ifdef GENLAB
if (!(flag & SYM_EXT) && if (!(flag & SYM_EXT) &&
strncmp(ip->i_name, genlab, sizeof(genlab)-1) == 0) strncmp(ip->i_name, genlab, sizeof(genlab)-1) == 0)
flag = SYM_LAB; flag = SYM_LAB;
#endif GENLAB #endif /* GENLAB */
if (sflag & flag) if (sflag & flag)
newsymb( newsymb(
ip->i_name, ip->i_name,

2
mach/proto/as/comm7.c
View file

@ -167,7 +167,7 @@ listline(textline)
listcolm = 0; listcolm = 0;
listflag = listtemp; listflag = listtemp;
} }
#endif LISTING #endif /* LISTING */
/* ---------- code optimization ---------- */ /* ---------- code optimization ---------- */

4
mach/proto/cg/codegen.c
View file

@ -247,14 +247,14 @@ if (Debug)
#ifdef MAXSPLIT #ifdef MAXSPLIT
sret = split(tp,&tokexp[i],ply,toplevel); sret = split(tp,&tokexp[i],ply,toplevel);
if (sret==0) { if (sret==0) {
#endif MAXSPLIT #endif /* MAXSPLIT */
totalcost += stackupto(tp,ply,toplevel); totalcost += stackupto(tp,ply,toplevel);
CHKCOST(); CHKCOST();
break; break;
#ifdef MAXSPLIT #ifdef MAXSPLIT
} }
i += sret; i += sret;
#endif MAXSPLIT #endif /* MAXSPLIT */
} else } else
i += 1; i += 1;
tp--; tp--;

2
mach/proto/cg/extern.h
View file

@ -41,7 +41,7 @@ extern int pathash[256]; /* Indices into previous */
extern c1_t c1coercs[]; /* coercions type 1 */ extern c1_t c1coercs[]; /* coercions type 1 */
#ifdef MAXSPLIT #ifdef MAXSPLIT
extern c2_t c2coercs[]; /* coercions type 2 */ extern c2_t c2coercs[]; /* coercions type 2 */
#endif MAXSPLIT #endif /* MAXSPLIT */
extern c3_t c3coercs[]; /* coercions type 3 */ extern c3_t c3coercs[]; /* coercions type 3 */
extern struct reginfo **reglist[]; /* lists of registers per property */ extern struct reginfo **reglist[]; /* lists of registers per property */

2
mach/proto/cg/fillem.c
View file

@ -548,7 +548,7 @@ bss(n,t,b) full n; {
if (b==0 if (b==0
#ifdef BSS_INIT #ifdef BSS_INIT
|| (t==sp_cstx && argval==BSS_INIT) || (t==sp_cstx && argval==BSS_INIT)
#endif BSS_INIT #endif /* BSS_INIT */
) { ) {
switchseg(SEGBSS); switchseg(SEGBSS);
newlbss(labstr,n); newlbss(labstr,n);

2
mach/proto/cg/reg.c
View file

@ -163,7 +163,7 @@ chkregs() {
for(j=0;j<nregvar[i];j++) for(j=0;j<nregvar[i];j++)
inctcount(rvnumbers[i][j]); inctcount(rvnumbers[i][j]);
} }
#endif REGVARS #endif /* REGVARS */
for (rp=machregs;rp<machregs+NREGS;rp++) { for (rp=machregs;rp<machregs+NREGS;rp++) {
assert(rp->r_refcount==rp->r_tcount); assert(rp->r_refcount==rp->r_tcount);
rp->r_tcount=0; rp->r_tcount=0;

2
mach/proto/cg/regvar.c
View file

@ -135,6 +135,6 @@ unlinkregs() {
} }
} }
#endif REGVARS #endif /* REGVARS */
/* nothing after this */ /* nothing after this */

4
mach/proto/cg/subr.c
View file

@ -332,7 +332,7 @@ instsize(tinstno,tp) token_p tp; {
return(tokens[inp->in_info[0]].t_size); return(tokens[inp->in_info[0]].t_size);
} }
} }
#endif MAXSPLIT #endif /* MAXSPLIT */
tref(tp,amount) register token_p tp; { tref(tp,amount) register token_p tp; {
register i; register i;
@ -389,7 +389,7 @@ found:
fakestack[stackheight++] = savestack[i]; fakestack[stackheight++] = savestack[i];
return(cp->c2_nsplit); return(cp->c2_nsplit);
} }
#endif MAXSPLIT #endif /* MAXSPLIT */
unsigned docoerc(tp,cp,ply,toplevel,forced) token_p tp; c3_p cp; { unsigned docoerc(tp,cp,ply,toplevel,forced) token_p tp; c3_p cp; {
token_t savestack[MAXSAVE]; token_t savestack[MAXSAVE];

2
mach/proto/cg/types.h
View file

@ -27,4 +27,4 @@ typedef char * string;
#define word long #define word long
#ifndef WRD_FMT #ifndef WRD_FMT
#define WRD_FMT "%ld" #define WRD_FMT "%ld"
#endif WRD_FMT #endif /* WRD_FMT */

2
mach/proto/fp/div_ext.c
View file

@ -138,7 +138,7 @@ EXTEND *e1,*e2;
*lp <<= count; *lp <<= count;
} }
} }
#else USE_DIVIDE #else /* USE_DIVIDE */
u[4] = (e1->m2 & 1) << 15; u[4] = (e1->m2 & 1) << 15;
b64_rsft(&(e1->m1)); b64_rsft(&(e1->m1));

4
mach/proto/ncg/codegen.c
View file

@ -295,14 +295,14 @@ if (Debug)
#ifdef MAXSPLIT #ifdef MAXSPLIT
sret = split(tp,&tokexp[i],ply,toplevel); sret = split(tp,&tokexp[i],ply,toplevel);
if (sret==0) { if (sret==0) {
#endif MAXSPLIT #endif /* MAXSPLIT */
totalcost += stackupto(tp,ply,toplevel); totalcost += stackupto(tp,ply,toplevel);
CHKCOST(); CHKCOST();
break; break;
#ifdef MAXSPLIT #ifdef MAXSPLIT
} }
i += sret; i += sret;
#endif MAXSPLIT #endif /* MAXSPLIT */
} else } else
i += 1; i += 1;
tp--; tp--;

2
mach/proto/ncg/extern.h
View file

@ -42,7 +42,7 @@ extern int pathash[256]; /* Indices into previous */
extern c1_t c1coercs[]; /* coercions type 1 */ extern c1_t c1coercs[]; /* coercions type 1 */
#ifdef MAXSPLIT #ifdef MAXSPLIT
extern c2_t c2coercs[]; /* coercions type 2 */ extern c2_t c2coercs[]; /* coercions type 2 */
#endif MAXSPLIT #endif /* MAXSPLIT */
extern c3_t c3coercs[]; /* coercions type 3 */ extern c3_t c3coercs[]; /* coercions type 3 */
extern struct reginfo **reglist[]; /* lists of registers per property */ extern struct reginfo **reglist[]; /* lists of registers per property */

2
mach/proto/ncg/fillem.c
View file

@ -588,7 +588,7 @@ bss(n,t,b) full n; {
if (b==0 if (b==0
#ifdef BSS_INIT #ifdef BSS_INIT
|| (t==sp_cstx && argval==BSS_INIT) || (t==sp_cstx && argval==BSS_INIT)
#endif BSS_INIT #endif /* BSS_INIT */
) { ) {
switchseg(SEGBSS); switchseg(SEGBSS);
newlbss(labstr,n); newlbss(labstr,n);

2
mach/proto/ncg/reg.c
View file

@ -205,7 +205,7 @@ chkregs() {
for(j=0;j<nregvar[i];j++) for(j=0;j<nregvar[i];j++)
inctcount(rvnumbers[i][j]); inctcount(rvnumbers[i][j]);
} }
#endif REGVARS #endif /* REGVARS */
for (rp=machregs+1;rp<machregs+NREGS;rp++) { for (rp=machregs+1;rp<machregs+NREGS;rp++) {
assert(rp->r_refcount==rp->r_tcount); assert(rp->r_refcount==rp->r_tcount);
rp->r_tcount=0; rp->r_tcount=0;

2
mach/proto/ncg/regvar.c
View file

@ -145,6 +145,6 @@ unlinkregs() {
} }
} }
#endif REGVARS #endif /* REGVARS */
/* nothing after this */ /* nothing after this */

4
mach/proto/ncg/subr.c
View file

@ -415,7 +415,7 @@ instsize(tinstno,tp) token_p tp; {
return(tokens[inp->in_info[0]].t_size); return(tokens[inp->in_info[0]].t_size);
} }
} }
#endif MAXSPLIT #endif /* MAXSPLIT */
tref(tp,amount) register token_p tp; { tref(tp,amount) register token_p tp; {
register i; register i;
@ -530,7 +530,7 @@ found:
rest_stack(); rest_stack();
return(cp->c2_nsplit); return(cp->c2_nsplit);
} }
#endif MAXSPLIT #endif /* MAXSPLIT */
unsigned docoerc(tp,cp,ply,toplevel,forced) token_p tp; register c3_p cp; { unsigned docoerc(tp,cp,ply,toplevel,forced) token_p tp; register c3_p cp; {
unsigned cost; unsigned cost;

2
mach/proto/ncg/types.h
View file

@ -27,4 +27,4 @@ typedef char * string;
#define word long #define word long
#ifndef WRD_FMT #ifndef WRD_FMT
#define WRD_FMT "%ld" #define WRD_FMT "%ld"
#endif WRD_FMT #endif /* WRD_FMT */

6
mach/vax4/cg/mach.c
View file

@ -2,7 +2,7 @@
#ifndef lint #ifndef lint
static char rcsid[] = "$Header$"; static char rcsid[] = "$Header$";
#endif lint #endif /* lint */
/* /*
* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands. * (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
* See the copyright notice in the ACK home directory, in the file "Copyright". * See the copyright notice in the ACK home directory, in the file "Copyright".
@ -129,7 +129,7 @@ prolog(nlocals)
fprintf(codefile,"\tsubl2\t$%ld,sp\n",nlocals); fprintf(codefile,"\tsubl2\t$%ld,sp\n",nlocals);
} }
#endif not REGVARS #endif /* not REGVARS */
char *segname[] = { char *segname[] = {
".sect .text", /* SEGTXT */ ".sect .text", /* SEGTXT */
@ -273,4 +273,4 @@ regscore(off, size, typ, score, totyp)
return i - 1; return i - 1;
} }
#endif REGVARS #endif /* REGVARS */

212
mach/vax4/cg/table
View file

@ -54,7 +54,7 @@ R8 = ("r8",4) regvar,RREG.
R9 = ("r9",4) regvar,RREG. R9 = ("r9",4) regvar,RREG.
RA = ("r10",4) regvar,RREG. RA = ("r10",4) regvar,RREG.
RB = ("r11",4) regvar,RREG. RB = ("r11",4) regvar,RREG.
#else REGVARS #else /* REGVARS */
R4 = ("r4",4),REG. R4 = ("r4",4),REG.
R5 = ("r5",4),REG. R5 = ("r5",4),REG.
R6 = ("r6",4),REG. R6 = ("r6",4),REG.
@ -63,7 +63,7 @@ R8 = ("r8",4),REG.
R9 = ("r9",4),REG. R9 = ("r9",4),REG.
RA = ("r10",4),REG. RA = ("r10",4),REG.
RB = ("r11",4),REG. RB = ("r11",4),REG.
#endif REGVARS #endif /* REGVARS */
QR0 = ("r0",8,R0,R1),QREG. QR0 = ("r0",8,R0,R1),QREG.
QR2 = ("r2",8,R2,R3),QREG. QR2 = ("r2",8,R2,R3),QREG.
#ifndef REGVARS #ifndef REGVARS
@ -71,14 +71,14 @@ QR4 = ("r4",8,R4,R5),QREG.
QR6 = ("r6",8,R6,R7),QREG. QR6 = ("r6",8,R6,R7),QREG.
QR8 = ("r8",8,R8,R9),QREG. QR8 = ("r8",8,R8,R9),QREG.
QRA = ("r10",8,RA,RB),QREG. QRA = ("r10",8,RA,RB),QREG.
#endif REGVARS #endif /* REGVARS */
QR1 = ("r1",8,R1,R2),QREG. QR1 = ("r1",8,R1,R2),QREG.
#ifndef REGVARS #ifndef REGVARS
QR3 = ("r3",8,R3,R4),QREG. QR3 = ("r3",8,R3,R4),QREG.
QR5 = ("r5",8,R5,R6),QREG. QR5 = ("r5",8,R5,R6),QREG.
QR7 = ("r7",8,R7,R8),QREG. QR7 = ("r7",8,R7,R8),QREG.
QR9 = ("r9",8,R9,RA),QREG. QR9 = ("r9",8,R9,RA),QREG.
#endif REGVARS #endif /* REGVARS */
TOKENS: TOKENS:
@ -112,7 +112,7 @@ regdec1 = {REGISTER reg;} 4 cost=(0,3) "-(%[reg])"
regdec2 = {REGISTER reg;} 4 cost=(0,3) "-(%[reg])" regdec2 = {REGISTER reg;} 4 cost=(0,3) "-(%[reg])"
regdec4 = {REGISTER reg;} 4 cost=(0,3) "-(%[reg])" regdec4 = {REGISTER reg;} 4 cost=(0,3) "-(%[reg])"
regdec8 = {REGISTER reg;} 8 cost=(0,6) "-(%[reg])" regdec8 = {REGISTER reg;} 8 cost=(0,6) "-(%[reg])"
#endif REGVARS #endif /* REGVARS */
displ1 = {REGISTER reg; STRING ind;} 4 cost=(2,6) "%[ind](%[reg])" displ1 = {REGISTER reg; STRING ind;} 4 cost=(2,6) "%[ind](%[reg])"
displ2 = {REGISTER reg; STRING ind;} 4 cost=(2,6) "%[ind](%[reg])" displ2 = {REGISTER reg; STRING ind;} 4 cost=(2,6) "%[ind](%[reg])"
displ4 = {REGISTER reg; STRING ind;} 4 cost=(2,6) "%[ind](%[reg])" displ4 = {REGISTER reg; STRING ind;} 4 cost=(2,6) "%[ind](%[reg])"
@ -186,19 +186,19 @@ Xsource1 = regdef1 + displ1 + displdef1 +
source1 = Xsource1 source1 = Xsource1
#ifdef REGVARS #ifdef REGVARS
+ reginc1 + regdec1 + reginc1 + regdec1
#endif REGVARS #endif /* REGVARS */
Xsource2 = regdef2 + displ2 + displdef2 + Xsource2 = regdef2 + displ2 + displdef2 +
EXTERNAL2 + reldef2 + CONST2 + LOCAL2 + ind2 EXTERNAL2 + reldef2 + CONST2 + LOCAL2 + ind2
source2 = Xsource2 source2 = Xsource2
#ifdef REGVARS #ifdef REGVARS
+ reginc2 + regdec2 + reginc2 + regdec2
#endif REGVARS #endif /* REGVARS */
Xsource4 = REG + regdef4 + displ4 + displdef4 + LocaLBase + Xsource4 = REG + regdef4 + displ4 + displdef4 + LocaLBase +
EXTERNAL4 + reldef4 + CONST + DOUBLE + LOCAL4 + ind4 EXTERNAL4 + reldef4 + CONST + DOUBLE + LOCAL4 + ind4
source4 = Xsource4 source4 = Xsource4
#ifdef REGVARS #ifdef REGVARS
+ RREG + reginc4 + regdec4 + RREG + reginc4 + regdec4
#endif REGVARS #endif /* REGVARS */
dups4 = CONST + regdef1 + displ1 + LOCAL1 + dups4 = CONST + regdef1 + displ1 + LOCAL1 +
REG + regdef2 + displ2 + LOCAL2 + REG + regdef2 + displ2 + LOCAL2 +
RREG + regdef4 + displ4 + LOCAL4 + DOUBLE RREG + regdef4 + displ4 + LOCAL4 + DOUBLE
@ -208,7 +208,7 @@ Xsource8 = QREG + regdef8 + displ8 + displdef8 +
source8 = Xsource8 source8 = Xsource8
#ifdef REGVARS #ifdef REGVARS
+ reginc8 + regdec8 + reginc8 + regdec8
#endif REGVARS #endif /* REGVARS */
source1or2 = source1 + source2 - ind2 source1or2 = source1 + source2 - ind2
source1or2or4 = source1or2 + source4 - (ind2 + ind4) source1or2or4 = source1or2 + source4 - (ind2 + ind4)
source2or4 = source2 + source4 - ind4 source2or4 = source2 + source4 - ind4
@ -227,12 +227,12 @@ nonexist = nonexist1 + aind
regch4 = reginc1 + regdec1 + reginc2 + regdec2 + reginc4 + regdec4 regch4 = reginc1 + regdec1 + reginc2 + regdec2 + reginc4 + regdec4
regch8 = reginc8 + regdec8 regch8 = reginc8 + regdec8
regch = regch4 + regch8 regch = regch4 + regch8
#endif REGVARS #endif /* REGVARS */
displs = displ1 + displ2 + displ4 + displ8 + displs = displ1 + displ2 + displ4 + displ8 +
regdef1 + regdef2 + regdef4 + regdef8 regdef1 + regdef2 + regdef4 + regdef8
#ifdef REGVARS #ifdef REGVARS
+ regch + regch
#endif REGVARS #endif /* REGVARS */
displdefs = displdef1 + displdef2 + displdef4 + displdef8 displdefs = displdef1 + displdef2 + displdef4 + displdef8
EXTERNALS = EXTERNAL1 + EXTERNAL2 + EXTERNAL4 + EXTERNAL8 EXTERNALS = EXTERNAL1 + EXTERNAL2 + EXTERNAL4 + EXTERNAL8
LOCALS = LOCAL1 + LOCAL2 + LOCAL4 + LOCAL8 LOCALS = LOCAL1 + LOCAL2 + LOCAL4 + LOCAL8
@ -248,10 +248,10 @@ extandloc = externals + LOCALS
#ifdef REGVARS #ifdef REGVARS
reg4 = REG + RREG + LocaLBase reg4 = REG + RREG + LocaLBase
reg8 = QREG reg8 = QREG
#else REGVARS #else /* REGVARS */
reg4 = REG reg4 = REG
reg8 = QREG reg8 = QREG
#endif REGVARS #endif /* REGVARS */
sreg4 = REG * SCRATCH sreg4 = REG * SCRATCH
sreg8 = QREG * SCRATCH sreg8 = QREG * SCRATCH
bigsource4 = source1or2or4 + nonexist + ind2 + ind4 bigsource4 = source1or2or4 + nonexist + ind2 + ind4
@ -262,9 +262,9 @@ scr = ALL - (EXTERNALS + LOCALS + ADDR_LOCAL + ADDR_EXTERNAL + CONST
#ifdef REGVARS #ifdef REGVARS
#define REMEXTANDLOC remove(externals) remove(LOCALS,inreg(%[num])==0) #define REMEXTANDLOC remove(externals) remove(LOCALS,inreg(%[num])==0)
#define REMREG(x) remove(regch,%[reg]==regvar(x)) #define REMREG(x) remove(regch,%[reg]==regvar(x))
#else REGVARS #else /* REGVARS */
#define REMEXTANDLOC remove(extandloc) #define REMEXTANDLOC remove(extandloc)
#endif REGVARS #endif /* REGVARS */
CODE: CODE:
@ -278,13 +278,13 @@ loc | | | {CONST4,$1} | |
ldc | | | {CONST8,$1} | | ldc | | | {CONST8,$1} | |
#ifdef REGVARS #ifdef REGVARS
lol inreg($1)==2 | | REMREG($1) | regvar($1) | | lol inreg($1)==2 | | REMREG($1) | regvar($1) | |
#endif REGVARS #endif /* REGVARS */
lol $1 < 0 | | | {LOCAL4,LB,$1,4} | | lol $1 < 0 | | | {LOCAL4,LB,$1,4} | |
lol $1 >= 0 | | | {LOCAL4,AP,$1,4} | | lol $1 >= 0 | | | {LOCAL4,AP,$1,4} | |
loe | | | {EXTERNAL4,$1} | | loe | | | {EXTERNAL4,$1} | |
#ifdef REGVARS #ifdef REGVARS
lil inreg($1)==2 | | REMREG($1) | {regdef4,regvar($1)} | | lil inreg($1)==2 | | REMREG($1) | {regdef4,regvar($1)} | |
#endif REGVARS #endif /* REGVARS */
lil $1 < 0 | | | {displdef4,LB,tostring($1)} | | lil $1 < 0 | | | {displdef4,LB,tostring($1)} | |
lil $1 >= 0 | | | {displdef4,AP,tostring($1)} | | lil $1 >= 0 | | | {displdef4,AP,tostring($1)} | |
lof | | | | adp $1 loi 4 | lof | | | | adp $1 loi 4 |
@ -407,7 +407,7 @@ stl inreg($1)==2 | NC bigsource4 |
move(%[1],regvar($1)) | | | move(%[1],regvar($1)) | | |
... | STACK | ... | STACK |
"movl\t(sp)+,%(regvar($1)%)" | | | (3,7) "movl\t(sp)+,%(regvar($1)%)" | | | (3,7)
#endif REGVARS #endif /* REGVARS */
stl $1 < 0 | NC bigsource4 | stl $1 < 0 | NC bigsource4 |
remove(displaced) remove(displaced)
remove(LOCALS,%[num] <= $1+3 && %[num]+%[size] > $1) remove(LOCALS,%[num] <= $1+3 && %[num]+%[size] > $1)
@ -431,7 +431,7 @@ sil inreg($1)==2 | NC bigsource4 |
move(%[1],{regdef4,regvar($1)}) | | | move(%[1],{regdef4,regvar($1)}) | | |
... | STACK | ... | STACK |
"movl\t(sp)+,(%(regvar($1)%))" | | | (3,10) "movl\t(sp)+,(%(regvar($1)%))" | | | (3,10)
#endif REGVARS #endif /* REGVARS */
sil $1 < 0 | NC bigsource4 | sil $1 < 0 | NC bigsource4 |
REMEXTANDLOC REMEXTANDLOC
move(%[1],{displdef4,LB,tostring($1)}) | | | move(%[1],{displdef4,LB,tostring($1)}) | | |
@ -663,7 +663,7 @@ adi stl $1==4 && inreg($2)==2
"addl3\t%[1],%[2],%(regvar($2)%)" "addl3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
adi stl $1==4 && $2<0 adi stl $1==4 && $2<0
| source4 source4 | | source4 source4 |
remove(displaced) remove(displaced)
@ -687,7 +687,7 @@ adi lol stf $1==4 && inreg($2)==2
REMEXTANDLOC REMEXTANDLOC
"addl3\t%[1],%[2],$3(%(regvar($2)%))" "addl3\t%[1],%[2],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | | setcc({displ4,regvar($2),tostring($3)}) | | |
#endif REGVARS #endif /* REGVARS */
adi sil $1==4 && $2<0 adi sil $1==4 && $2<0
| source4 source4 | | source4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -721,7 +721,7 @@ sbi stl $1==4 && inreg($2)==2
"subl3\t%[1],%[2],%(regvar($2)%)" "subl3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
sbi stl $1==4 && $2<0 sbi stl $1==4 && $2<0
| source4 source4 | | source4 source4 |
remove(displaced) remove(displaced)
@ -745,7 +745,7 @@ sbi lol stf $1==4 && inreg($2)==2
REMEXTANDLOC REMEXTANDLOC
"subl3\t%[1],%[2],$3(%(regvar($2)%))" "subl3\t%[1],%[2],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | | setcc({displ4,regvar($2),tostring($3)}) | | |
#endif REGVARS #endif /* REGVARS */
sbi sil $1==4 && $2<0 sbi sil $1==4 && $2<0
| source4 source4 | | source4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -783,7 +783,7 @@ mli stl $1==4 && inreg($2)==2
"mull3\t%[1],%[2],%(regvar($2)%)" "mull3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
mli stl $1==4 && $2<0 mli stl $1==4 && $2<0
| source4 source4 | | source4 source4 |
remove(displaced) remove(displaced)
@ -807,7 +807,7 @@ mli lol stf $1==4 && inreg($2)==2
REMEXTANDLOC REMEXTANDLOC
"mull3\t%[1],%[2],$3(%(regvar($2)%))" "mull3\t%[1],%[2],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | | setcc({displ4,regvar($2),tostring($3)}) | | |
#endif REGVARS #endif /* REGVARS */
mli sil $1==4 && $2<0 mli sil $1==4 && $2<0
| source4 source4 | | source4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -841,7 +841,7 @@ dvi stl $1==4 && inreg($2)==2
"divl3\t%[1],%[2],%(regvar($2)%)" "divl3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
dvi stl $1==4 && $2<0 dvi stl $1==4 && $2<0
| source4 source4 | | source4 source4 |
remove(displaced) remove(displaced)
@ -865,7 +865,7 @@ dvi lol stf $1==4 && inreg($2)==2
REMEXTANDLOC REMEXTANDLOC
"divl3\t%[1],%[2],$3(%(regvar($2)%))" "divl3\t%[1],%[2],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | | setcc({displ4,regvar($2),tostring($3)}) | | |
#endif REGVARS #endif /* REGVARS */
dvi sil $1==4 && $2<0 dvi sil $1==4 && $2<0
| source4 source4 | | source4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -900,7 +900,7 @@ rmi stl $1==4 && inreg($2)==2
"subl3\t%[a],%[2],%(regvar($2)%)" "subl3\t%[a],%[2],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
rmi stl $1==4 && $2<0 rmi stl $1==4 && $2<0
| Xsource4 Xsource4 | | Xsource4 Xsource4 |
remove(displaced) remove(displaced)
@ -936,7 +936,7 @@ rmi lol stf $1==4 && inreg($2)==2
"mull2\t%[1],%[a]" "mull2\t%[1],%[a]"
"subl3\t%[a],%[2],$3(%(regvar($2)%))" "subl3\t%[a],%[2],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | | setcc({displ4,regvar($2),tostring($3)}) | | |
#endif REGVARS #endif /* REGVARS */
rmi sil $1==4 && $2<0 rmi sil $1==4 && $2<0
| Xsource4 Xsource4 | | Xsource4 Xsource4 |
REMEXTANDLOC REMEXTANDLOC
@ -976,7 +976,7 @@ ngi stl $1==4 && inreg($2)==2
"mnegl\t%[1],%(regvar($2)%)" "mnegl\t%[1],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
ngi stl $1==4 && $2<0 ngi stl $1==4 && $2<0
| source4 | | source4 |
remove(displaced) remove(displaced)
@ -1000,7 +1000,7 @@ ngi lol stf $1==4 && inreg($2)==2
REMEXTANDLOC REMEXTANDLOC
"mnegl\t%[1],$3(%(regvar($2)%))" "mnegl\t%[1],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | | setcc({displ4,regvar($2),tostring($3)}) | | |
#endif REGVARS #endif /* REGVARS */
ngi sil $1==4 && $2<0 ngi sil $1==4 && $2<0
| source4 | | source4 |
REMEXTANDLOC REMEXTANDLOC
@ -1030,7 +1030,7 @@ sli stl $1==4 && inreg($2)==2
"ashl\t%[1],%[2],%(regvar($2)%)" "ashl\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
sli stl $1==4 && $2<0 sli stl $1==4 && $2<0
| source1or2or4 source4 | | source1or2or4 source4 |
remove(displaced) remove(displaced)
@ -1054,7 +1054,7 @@ sli lol stf $1==4 && inreg($2)==2
REMEXTANDLOC REMEXTANDLOC
"ashl\t%[1],%[2],$3(%(regvar($2)%))" "ashl\t%[1],%[2],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | | setcc({displ4,regvar($2),tostring($3)}) | | |
#endif REGVARS #endif /* REGVARS */
sli sil $1==4 && $2<0 sli sil $1==4 && $2<0
| source1or2or4 source4 | | source1or2or4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -1097,7 +1097,7 @@ sri stl $1==4 && inreg($2)==2
"ashl\t$$%(0-%[1.num]%),%[2],%(regvar($2)%)" "ashl\t$$%(0-%[1.num]%),%[2],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | (6,10)+%[1]+%[2] setcc(regvar($2)) | | | (6,10)+%[1]+%[2]
#endif REGVARS #endif /* REGVARS */
sri stl $1==4 && $2<0 sri stl $1==4 && $2<0
| source4 source4 | | source4 source4 |
remove(displaced) remove(displaced)
@ -1147,7 +1147,7 @@ sri lol stf $1==4 && inreg($2)==2
REMEXTANDLOC REMEXTANDLOC
"ashl\t$$%(0-%[1.num]%),%[2],$3(%(regvar($2)%))" "ashl\t$$%(0-%[1.num]%),%[2],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | | (6,10)+%[1]+%[2] setcc({displ4,regvar($2),tostring($3)}) | | | (6,10)+%[1]+%[2]
#endif REGVARS #endif /* REGVARS */
sri sil $1==4 && $2<0 sri sil $1==4 && $2<0
| source4 source4 | | source4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -1255,7 +1255,7 @@ adf stl $1==4 && inreg($2)==2
remove(regvar($2)) remove(regvar($2))
"addf3\t%[1],%[2],%(regvar($2)%)" "addf3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2)) | | | erase(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
adf stl $1==4 && $2<0 adf stl $1==4 && $2<0
| source4 source4 | | source4 source4 |
remove(displaced) remove(displaced)
@ -1274,7 +1274,7 @@ adf sil $1==4 && inreg($2)==2
remove(regvar($2)) remove(regvar($2))
"addf3\t%[1],%[2],(%(regvar($2)%))" "addf3\t%[1],%[2],(%(regvar($2)%))"
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
adf sil $1==4 && $2<0 adf sil $1==4 && $2<0
| source4 source4 | | source4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -1289,7 +1289,7 @@ adf ste $1==4 | source4 source4 |
remove(externals) remove(externals)
"addf3\t%[1],%[2],$2" "addf3\t%[1],%[2],$2"
setcc({EXTERNAL4,$2}) | | | setcc({EXTERNAL4,$2}) | | |
#endif FLOAT4 #endif /* FLOAT4 */
adf $1==8 | source8 source8 | adf $1==8 | source8 source8 |
allocate(%[1],%[2],QREG) allocate(%[1],%[2],QREG)
"addd3\t%[1],%[2],%[a]" "addd3\t%[1],%[2],%[a]"
@ -1319,7 +1319,7 @@ adf sde $1==8 | source8 source8 |
remove(externals) remove(externals)
"addd3\t%[1],%[2],$2" "addd3\t%[1],%[2],$2"
setcc({EXTERNAL8,$2}) | | | setcc({EXTERNAL8,$2}) | | |
#endif FLOAT8 #endif /* FLOAT8 */
adf !defined($1) | source4 | adf !defined($1) | source4 |
remove(ALL) remove(ALL)
move(%[1],R0) move(%[1],R0)
@ -1340,7 +1340,7 @@ sbf stl $1==4 && inreg($2)==2
"subf3\t%[1],%[2],%(regvar($2)%)" "subf3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
sbf stl $1==4 && $2<0 sbf stl $1==4 && $2<0
| source4 source4 | | source4 source4 |
remove(displaced) remove(displaced)
@ -1359,7 +1359,7 @@ sbf sil $1==4 && inreg($2)==2
remove(regvar($2)) remove(regvar($2))
"subf3\t%[1],%[2],(%(regvar($2)%))" "subf3\t%[1],%[2],(%(regvar($2)%))"
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
sbf sil $1==4 && $2<0 sbf sil $1==4 && $2<0
| source4 source4 | | source4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -1374,7 +1374,7 @@ sbf ste $1==4 | source4 source4 |
remove(externals) remove(externals)
"subf3\t%[1],%[2],$2" "subf3\t%[1],%[2],$2"
setcc({EXTERNAL4,$2}) | | | setcc({EXTERNAL4,$2}) | | |
#endif FLOAT4 #endif /* FLOAT4 */
sbf $1==8 | source8 source8 | sbf $1==8 | source8 source8 |
allocate(%[1],%[2],QREG) allocate(%[1],%[2],QREG)
"subd3\t%[1],%[2],%[a]" "subd3\t%[1],%[2],%[a]"
@ -1400,7 +1400,7 @@ sbf sde $1==8 | source8 source8 |
remove(externals) remove(externals)
"subd3\t%[1],%[2],$2" "subd3\t%[1],%[2],$2"
setcc({EXTERNAL8,$2}) | | | setcc({EXTERNAL8,$2}) | | |
#endif FLOAT8 #endif /* FLOAT8 */
sbf !defined($1) | source1or2or4 | sbf !defined($1) | source1or2or4 |
remove(ALL) remove(ALL)
move(%[1],R0) move(%[1],R0)
@ -1424,7 +1424,7 @@ mlf stl $1==4 && inreg($2)==2
remove(regvar($2)) remove(regvar($2))
"mulf3\t%[1],%[2],%(regvar($2)%)" "mulf3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2)) | | | erase(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
mlf stl $1==4 && $2<0 mlf stl $1==4 && $2<0
| source4 source4 | | source4 source4 |
remove(displaced) remove(displaced)
@ -1443,7 +1443,7 @@ mlf sil $1==4 && inreg($2)==2
remove(regvar($2)) remove(regvar($2))
"mulf3\t%[1],%[2],(%(regvar($2)%))" "mulf3\t%[1],%[2],(%(regvar($2)%))"
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
mlf sil $1==4 && $2<0 mlf sil $1==4 && $2<0
| source4 source4 | | source4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -1458,7 +1458,7 @@ mlf ste $1==4 | source4 source4 |
remove(externals) remove(externals)
"mulf3\t%[1],%[2],$2" "mulf3\t%[1],%[2],$2"
setcc({EXTERNAL4,$2}) | | | setcc({EXTERNAL4,$2}) | | |
#endif FLOAT4 #endif /* FLOAT4 */
mlf $1==8 | source8 source8 | mlf $1==8 | source8 source8 |
allocate(%[1],%[2],QREG) allocate(%[1],%[2],QREG)
"muld3\t%[1],%[2],%[a]" "muld3\t%[1],%[2],%[a]"
@ -1488,7 +1488,7 @@ mlf sde $1==8 | source8 source8 |
remove(externals) remove(externals)
"muld3\t%[1],%[2],$2" "muld3\t%[1],%[2],$2"
setcc({EXTERNAL8,$2}) | | | setcc({EXTERNAL8,$2}) | | |
#endif FLOAT8 #endif /* FLOAT8 */
mlf !defined($1) | source1or2or4 | mlf !defined($1) | source1or2or4 |
remove(ALL) remove(ALL)
move(%[1],R0) move(%[1],R0)
@ -1509,7 +1509,7 @@ dvf stl $1==4 && inreg($2)==2
"divf3\t%[1],%[2],%(regvar($2)%)" "divf3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
dvf stl $1==4 && $2<0 dvf stl $1==4 && $2<0
| source4 source4 | | source4 source4 |
remove(displaced) remove(displaced)
@ -1528,7 +1528,7 @@ dvf sil $1==4 && inreg($2)==2
remove(regvar($2)) remove(regvar($2))
"divf3\t%[1],%[2],(%(regvar($2)%))" "divf3\t%[1],%[2],(%(regvar($2)%))"
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
dvf sil $1==4 && $2<0 dvf sil $1==4 && $2<0
| source4 source4 | | source4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -1543,7 +1543,7 @@ dvf ste $1==4 | source4 source4 |
remove(externals) remove(externals)
"divf3\t%[1],%[2],$2" "divf3\t%[1],%[2],$2"
setcc({EXTERNAL4,$2}) | | | setcc({EXTERNAL4,$2}) | | |
#endif FLOAT4 #endif /* FLOAT4 */
dvf $1==8 | source8 source8 | dvf $1==8 | source8 source8 |
allocate(%[1],%[2],QREG) allocate(%[1],%[2],QREG)
"divd3\t%[1],%[2],%[a]" "divd3\t%[1],%[2],%[a]"
@ -1569,7 +1569,7 @@ dvf sde $1==8 | source8 source8 |
remove(externals) remove(externals)
"divd3\t%[1],%[2],$2" "divd3\t%[1],%[2],$2"
setcc({EXTERNAL8,$2}) | | | setcc({EXTERNAL8,$2}) | | |
#endif FLOAT8 #endif /* FLOAT8 */
dvf !defined($1) | source1or2or4 | dvf !defined($1) | source1or2or4 |
remove(ALL) remove(ALL)
move(%[1],R0) move(%[1],R0)
@ -1586,7 +1586,7 @@ ngf stl $1==4 && inreg($2)==2
"mnegf\t%[1],%(regvar($2)%)" "mnegf\t%[1],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
ngf stl $1==4 && $2<0 ngf stl $1==4 && $2<0
| source4 | | source4 |
remove(displaced) remove(displaced)
@ -1605,7 +1605,7 @@ ngf sil $1==4 && inreg($2)==2
remove(regvar($2)) remove(regvar($2))
"mnegf\t%[1],(%(regvar($2)%))" "mnegf\t%[1],(%(regvar($2)%))"
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
ngf sil $1==4 && $2<0 ngf sil $1==4 && $2<0
| source4 | | source4 |
REMEXTANDLOC REMEXTANDLOC
@ -1620,7 +1620,7 @@ ngf ste $1==4 | source4 |
remove(externals) remove(externals)
"mnegf\t%[1],$2" "mnegf\t%[1],$2"
setcc({EXTERNAL4,$2}) | | | setcc({EXTERNAL4,$2}) | | |
#endif FLOAT4 #endif /* FLOAT4 */
ngf $1==8 | source8 | ngf $1==8 | source8 |
allocate(%[1],QREG) allocate(%[1],QREG)
"mnegd\t%[1],%[a]" "mnegd\t%[1],%[a]"
@ -1642,7 +1642,7 @@ ngf sde $1==8 | source8 |
remove(externals) remove(externals)
"mnegd\t%[1],$2" "mnegd\t%[1],$2"
setcc({EXTERNAL8,$2}) | | | setcc({EXTERNAL8,$2}) | | |
#endif FLOAT8 #endif /* FLOAT8 */
ngf !defined($1) | source1or2or4 | ngf !defined($1) | source1or2or4 |
remove(ALL) remove(ALL)
move(%[1],R0) move(%[1],R0)
@ -1891,7 +1891,7 @@ lol adp stl $1==$3 && inreg($1)==2
| | remove(regvar($1)) | | remove(regvar($1))
"addl2\t$$$2,%(regvar($1)%)" "addl2\t$$$2,%(regvar($1)%)"
erase(regvar($1)) | | | erase(regvar($1)) | | |
#endif REGVARS #endif /* REGVARS */
lol adp stl $1==$3 && $1<0 lol adp stl $1==$3 && $1<0
| | remove(displaced) | | remove(displaced)
remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1) remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1)
@ -1977,7 +1977,7 @@ inl inreg($1)==2 | | remove(regvar($1))
"incl\t%(regvar($1)%)" "incl\t%(regvar($1)%)"
erase(regvar($1)) erase(regvar($1))
setcc(regvar($1)) | | | setcc(regvar($1)) | | |
#endif REGVARS #endif /* REGVARS */
inl $1<0 | | remove(displaced) inl $1<0 | | remove(displaced)
remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1) remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1)
"incl\t$1(fp)" "incl\t$1(fp)"
@ -1993,7 +1993,7 @@ lol inl $1==$2 && inreg($1)==2
"incl\t%(regvar($1)%)" "incl\t%(regvar($1)%)"
erase(regvar($1)) erase(regvar($1))
setcc(regvar($1)) | %[a] | | setcc(regvar($1)) | %[a] | |
#endif REGVARS #endif /* REGVARS */
ine | | remove(externals) ine | | remove(externals)
"incl\t$1" "incl\t$1"
setcc({EXTERNAL4,$1}) | | | setcc({EXTERNAL4,$1}) | | |
@ -2002,7 +2002,7 @@ del inreg($1)==2 | | remove(regvar($1))
"decl\t%(regvar($1)%)" "decl\t%(regvar($1)%)"
erase(regvar($1)) erase(regvar($1))
setcc(regvar($1)) | | | setcc(regvar($1)) | | |
#endif REGVARS #endif /* REGVARS */
del $1<0 | | remove(displaced) del $1<0 | | remove(displaced)
remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1) remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1)
"decl\t$1(fp)" "decl\t$1(fp)"
@ -2018,7 +2018,7 @@ lol del $1==$2 && inreg($1)==2
"decl\t%(regvar($1)%)" "decl\t%(regvar($1)%)"
erase(regvar($1)) erase(regvar($1))
setcc(regvar($1)) | %[a] | | setcc(regvar($1)) | %[a] | |
#endif REGVARS #endif /* REGVARS */
dee | | remove(externals) dee | | remove(externals)
"decl\t$1" "decl\t$1"
setcc({EXTERNAL4,$1}) | | | setcc({EXTERNAL4,$1}) | | |
@ -2027,7 +2027,7 @@ zrl inreg($1)==2 | | remove(regvar($1))
"clrl\t%(regvar($1)%)" "clrl\t%(regvar($1)%)"
erase(regvar($1)) erase(regvar($1))
setcc(regvar($1)) | | | setcc(regvar($1)) | | |
#endif REGVARS #endif /* REGVARS */
zrl $1<0 | | remove(displaced) zrl $1<0 | | remove(displaced)
remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1) remove(LOCALS,%[num]<=$1+3 && %[num]+%[size]>$1)
"clrl\t$1(fp)" "clrl\t$1(fp)"
@ -2039,7 +2039,7 @@ zrl $1>=0 | | remove(displaced)
zrl zrl $1==$2+4 && $1<0 zrl zrl $1==$2+4 && $1<0
#ifdef REGVARS #ifdef REGVARS
&& inreg($1)<2 && inreg($2)<2 && inreg($1)<2 && inreg($2)<2
#endif REGVARS #endif /* REGVARS */
| | remove(displaced) | | remove(displaced)
remove(LOCALS,%[num]<=$2+7 && %[num]+%[size]>$2) remove(LOCALS,%[num]<=$2+7 && %[num]+%[size]>$2)
"clrq\t$2(fp)" "clrq\t$2(fp)"
@ -2047,7 +2047,7 @@ zrl zrl $1==$2+4 && $1<0
zrl zrl $1==$2+4 && $1>=0 zrl zrl $1==$2+4 && $1>=0
#ifdef REGVARS #ifdef REGVARS
&& inreg($1)<2 && inreg($2)<2 && inreg($1)<2 && inreg($2)<2
#endif REGVARS #endif /* REGVARS */
| | remove(displaced) | | remove(displaced)
remove(LOCALS,%[num]<=$2+7 && %[num]+%[size]>$2) remove(LOCALS,%[num]<=$2+7 && %[num]+%[size]>$2)
"clrq\t$2(ap)" "clrq\t$2(ap)"
@ -2070,10 +2070,10 @@ zer defined($1) | STACK |
#ifdef LOCLABS #ifdef LOCLABS
"1:\tclrl\t-(sp)" "1:\tclrl\t-(sp)"
"sobgtr\tr0,1b" "sobgtr\tr0,1b"
#else LOCLABS #else /* LOCLABS */
"clrl\t-(sp)" "clrl\t-(sp)"
"sobgtr\tr0,.-2" "sobgtr\tr0,.-2"
#endif LOCLABS #endif /* LOCLABS */
erase(R0) | | | erase(R0) | | |
zer !defined($1) | source1or2or4 | zer !defined($1) | source1or2or4 |
remove(ALL) remove(ALL)
@ -2081,10 +2081,10 @@ zer !defined($1) | source1or2or4 |
#ifdef LOCLABS #ifdef LOCLABS
"1:\tclrl\t-(sp)" "1:\tclrl\t-(sp)"
"sobgtr\tr0,1b" "sobgtr\tr0,1b"
#else LOCLABS #else /* LOCLABS */
"clrl\t-(sp)" "clrl\t-(sp)"
"sobgtr\tr0,.-2" "sobgtr\tr0,.-2"
#endif LOCLABS #endif /* LOCLABS */
erase(R0) | | | erase(R0) | | |
/******************************** /********************************
@ -2115,7 +2115,7 @@ loc loc cii stl $1==1 && $2==4 && inreg($4)==2
"cvtbl\t%[1],%(regvar($4)%)" "cvtbl\t%[1],%(regvar($4)%)"
erase(regvar($1)) erase(regvar($1))
setcc(regvar($4)) | | | setcc(regvar($4)) | | |
#endif REGVARS #endif /* REGVARS */
loc loc cii stl $1==1 && $2==4 && $4<0 loc loc cii stl $1==1 && $2==4 && $4<0
| source1or2or4 | | source1or2or4 |
remove(displaced) remove(displaced)
@ -2143,7 +2143,7 @@ loc loc cii stl $1==2 && $2==4 && inreg($4)==2
"cvtwl\t%[1],%(regvar($4)%)" "cvtwl\t%[1],%(regvar($4)%)"
erase(regvar($4)) erase(regvar($4))
setcc(regvar($4)) | | | setcc(regvar($4)) | | |
#endif REGVARS #endif /* REGVARS */
loc loc cii stl $1==2 && $2==4 && $4<0 loc loc cii stl $1==2 && $2==4 && $4<0
| source2or4 | | source2or4 |
remove(displaced) remove(displaced)
@ -2174,7 +2174,7 @@ loc loc cfi stl $1==4 && $2==4 && inreg($4)==2
"cvtfl\t%[1],%(regvar($4)%)" "cvtfl\t%[1],%(regvar($4)%)"
erase(regvar($4)) erase(regvar($4))
setcc(regvar($4)) | | | setcc(regvar($4)) | | |
#endif REGVARS #endif /* REGVARS */
loc loc cfi stl $1==4 && $2==4 && $4<0 loc loc cfi stl $1==4 && $2==4 && $4<0
| source4 | | source4 |
remove(displaced) remove(displaced)
@ -2191,7 +2191,7 @@ loc loc cfi ste $1==4 && $2==4 | source4 |
remove(externals) remove(externals)
"cvtfl\t%[1],$4" "cvtfl\t%[1],$4"
setcc({EXTERNAL4,$4}) | | | setcc({EXTERNAL4,$4}) | | |
#endif FLOAT4 #endif /* FLOAT4 */
loc loc cfi $1==4 && $2==4 | source4 | loc loc cfi $1==4 && $2==4 | source4 |
allocate(%[1],REG) allocate(%[1],REG)
"cvtfl\t%[1],%[a]" "cvtfl\t%[1],%[a]"
@ -2204,7 +2204,7 @@ loc loc cfi stl $1==8 && $2==4 && inreg($4)==2
"cvtdl\t%[1],%(regvar($4)%)" "cvtdl\t%[1],%(regvar($4)%)"
erase(regvar($4)) erase(regvar($4))
setcc(regvar($4)) | | | setcc(regvar($4)) | | |
#endif REGVARS #endif /* REGVARS */
loc loc cfi stl $1==8 && $2==4 && $4<0 loc loc cfi stl $1==8 && $2==4 && $4<0
| source8 | | source8 |
remove(displaced) remove(displaced)
@ -2221,7 +2221,7 @@ loc loc cfi ste $1==8 && $2==4 | source8 |
remove(externals) remove(externals)
"cvtdl\t%[1],$4" "cvtdl\t%[1],$4"
setcc({EXTERNAL4,$4}) | | | setcc({EXTERNAL4,$4}) | | |
#endif FLOAT8 #endif /* FLOAT8 */
loc loc cfi $1==8 && $2==4 | source8 | loc loc cfi $1==8 && $2==4 | source8 |
allocate(%[1],REG) allocate(%[1],REG)
"cvtdl\t%[1],%[a]" "cvtdl\t%[1],%[a]"
@ -2234,7 +2234,7 @@ loc loc cif stl $1==4 && $2==4 && inreg($4)==2
"cvtlf\t%[1],%(regvar($4)%)" "cvtlf\t%[1],%(regvar($4)%)"
erase(regvar($4)) erase(regvar($4))
setcc(regvar($4)) | | | setcc(regvar($4)) | | |
#endif REGVARS #endif /* REGVARS */
loc loc cif stl $1==4 && $2==4 && $4<0 loc loc cif stl $1==4 && $2==4 && $4<0
| source4 | | source4 |
remove(displaced) remove(displaced)
@ -2248,7 +2248,7 @@ loc loc cif stl $1==4 && $2==4 && $4>=0
loc loc cif ste $1==4 && $2==4 | source4 | loc loc cif ste $1==4 && $2==4 | source4 |
remove(externals) remove(externals)
"cvtlf\t%[1],$4" | | | "cvtlf\t%[1],$4" | | |
#endif FLOAT4 #endif /* FLOAT4 */
loc loc cif $1==4 && $2==4 | source4 | loc loc cif $1==4 && $2==4 | source4 |
allocate(%[1],REG) allocate(%[1],REG)
"cvtlf\t%[1],%[a]" | %[a] | | "cvtlf\t%[1],%[a]" | %[a] | |
@ -2261,7 +2261,7 @@ loc loc cif sdl $1==4 && $2==8 && inreg($4)==2
"cvtld\t%[1],%(regvar($4)%)" "cvtld\t%[1],%(regvar($4)%)"
erase(regvar($4)) erase(regvar($4))
setcc(regvar($4)) | | | setcc(regvar($4)) | | |
#endif REGVARS #endif /* REGVARS */
*/ */
loc loc cif sdl $1==4 && $2==8 && $4<0 loc loc cif sdl $1==4 && $2==8 && $4<0
| source4 | | source4 |
@ -2276,7 +2276,7 @@ loc loc cif sdl $1==4 && $2==8 && $4>=0
loc loc cif sde $1==4 && $2==8 | source4 | loc loc cif sde $1==4 && $2==8 | source4 |
remove(externals) remove(externals)
"cvtld\t%[1],$4" | | | "cvtld\t%[1],$4" | | |
#endif FLOAT8 #endif /* FLOAT8 */
loc loc cif $1==4 && $2==8 | source4 | loc loc cif $1==4 && $2==8 | source4 |
allocate(%[1],QREG) allocate(%[1],QREG)
"cvtld\t%[1],%[a]" | %[a] | | "cvtld\t%[1],%[a]" | %[a] | |
@ -2295,7 +2295,7 @@ loc loc cff sdl $1==4 && $2==8 && inreg($4)==2
"cvtfd\t%[1],%(regvar($4)%)" "cvtfd\t%[1],%(regvar($4)%)"
erase(regvar($4)) erase(regvar($4))
setcc(regvar($4)) | | | setcc(regvar($4)) | | |
#endif REGVARS #endif /* REGVARS */
*/ */
loc loc cff sdl $1==4 && $2==8 && $4<0 loc loc cff sdl $1==4 && $2==8 && $4<0
| source4 | | source4 |
@ -2310,7 +2310,7 @@ loc loc cff sdl $1==4 && $2==8 && $4>=0
loc loc cff sde $1==4 && $2==8 | source4 | loc loc cff sde $1==4 && $2==8 | source4 |
remove(externals) remove(externals)
"cvtfd\t%[1],$4" | | | "cvtfd\t%[1],$4" | | |
#endif FLOAT8 #endif /* FLOAT8 */
loc loc cff $1==4 && $2==8 | source4 | loc loc cff $1==4 && $2==8 | source4 |
allocate(%[1],QREG) allocate(%[1],QREG)
"cvtfd\t%[1],%[a]" | %[a] | | "cvtfd\t%[1],%[a]" | %[a] | |
@ -2322,7 +2322,7 @@ loc loc cff stl $1==8 && $2==4 && inreg($4)==2
"cvtdf\t%[1],%(regvar($4)%)" "cvtdf\t%[1],%(regvar($4)%)"
erase(regvar($4)) erase(regvar($4))
setcc(regvar($4)) | | | setcc(regvar($4)) | | |
#endif REGVARS #endif /* REGVARS */
loc loc cff stl $1==8 && $2==4 && $4<0 loc loc cff stl $1==8 && $2==4 && $4<0
| source8 | | source8 |
remove(displaced) remove(displaced)
@ -2336,7 +2336,7 @@ loc loc cff stl $1==8 && $2==4 && $4>=0
loc loc cff ste $1==8 && $2==4 | source8 | loc loc cff ste $1==8 && $2==4 | source8 |
remove(externals) remove(externals)
"cvtdf\t%[1],$4" | | | "cvtdf\t%[1],$4" | | |
#endif FLOAT4 #endif /* FLOAT4 */
loc loc cff $1==8 && $2==4 | source8 | loc loc cff $1==8 && $2==4 | source8 |
allocate(%[1],REG) allocate(%[1],REG)
"cvtdf\t%[1],%[a]" | %[a] | | "cvtdf\t%[1],%[a]" | %[a] | |
@ -2396,7 +2396,7 @@ and stl $1==4 && inreg($2)==2
"bicl3\t$$~%[2.num],%[1],%(regvar($2)%)" "bicl3\t$$~%[2.num],%[1],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | (4,4)+%[1]+%[2] setcc(regvar($2)) | | | (4,4)+%[1]+%[2]
#endif REGVARS #endif /* REGVARS */
and stl $1==4 && $2<0 and stl $1==4 && $2<0
| source4 source4 | | source4 source4 |
remove(displaced) remove(displaced)
@ -2452,7 +2452,7 @@ and sil $1==4 && inreg($2)==2
"bicl3\t$$~%[2.num],%[1],(%(regvar($2)%))" "bicl3\t$$~%[2.num],%[1],(%(regvar($2)%))"
setcc({regdef4,regvar($2)}) setcc({regdef4,regvar($2)})
| | | (6,12)+%[1]+%[2] | | | (6,12)+%[1]+%[2]
#endif REGVARS #endif /* REGVARS */
and sil $1==4 && $2<0 and sil $1==4 && $2<0
| source4 source4 | | source4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -2537,7 +2537,7 @@ ior stl $1==4 && inreg($2)==2
"bisl3\t%[1],%[2],%(regvar($2)%)" "bisl3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
ior stl $1==4 && $2<0 ior stl $1==4 && $2<0
| source4 source4 | | source4 source4 |
remove(displaced) remove(displaced)
@ -2556,7 +2556,7 @@ ior sil $1==4 && inreg($2)==2
REMEXTANDLOC REMEXTANDLOC
"bisl3\t%[1],%[2],(%(regvar($2)%))" "bisl3\t%[1],%[2],(%(regvar($2)%))"
setcc({regdef4,regvar($2)}) | | | setcc({regdef4,regvar($2)}) | | |
#endif REGVARS #endif /* REGVARS */
ior sil $1==4 && $2<0 ior sil $1==4 && $2<0
| source4 source4 | | source4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -2603,7 +2603,7 @@ xor stl $1==4 && inreg($2)==2
"xorl3\t%[1],%[2],%(regvar($2)%)" "xorl3\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
xor stl $1==4 && $2<0 xor stl $1==4 && $2<0
| source4 source4 | | source4 source4 |
remove(displaced) remove(displaced)
@ -2622,7 +2622,7 @@ xor sil $1==4 && inreg($2)==2
REMEXTANDLOC REMEXTANDLOC
"xorl3\t%[1],%[2],(%(regvar($2)%))" "xorl3\t%[1],%[2],(%(regvar($2)%))"
setcc({regdef4,regvar($2)}) | | | setcc({regdef4,regvar($2)}) | | |
#endif REGVARS #endif /* REGVARS */
xor sil $1==4 && $2<0 xor sil $1==4 && $2<0
| source4 source4 | | source4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -2657,7 +2657,7 @@ com stl $1==4 && inreg($2)==2
"mcoml\t%[1],%(regvar($2)%)" "mcoml\t%[1],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
com stl $1==4 && $2<0 com stl $1==4 && $2<0
| source4 | | source4 |
remove(displaced) remove(displaced)
@ -2676,7 +2676,7 @@ com sil $1==4 && inreg($2)==2
REMEXTANDLOC REMEXTANDLOC
"mcoml\t%[1],(%(regvar($2)%))" "mcoml\t%[1],(%(regvar($2)%))"
setcc({regdef4,regvar($2)}) | | | setcc({regdef4,regvar($2)}) | | |
#endif REGVARS #endif /* REGVARS */
com sil $1==4 && $2<0 com sil $1==4 && $2<0
| source4 | | source4 |
REMEXTANDLOC REMEXTANDLOC
@ -2712,7 +2712,7 @@ rol stl $1==4 && inreg($2)==2
"rotl\t%[1],%[2],%(regvar($2)%)" "rotl\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
rol stl $1==4 && $2<0 rol stl $1==4 && $2<0
| source4 source4 | | source4 source4 |
remove(displaced) remove(displaced)
@ -2731,7 +2731,7 @@ rol sil $1==4 && inreg($2)==2
REMEXTANDLOC REMEXTANDLOC
"rotl\t%[1],%[2],(%(regvar($2)%))" "rotl\t%[1],%[2],(%(regvar($2)%))"
setcc({regdef4,regvar($2)}) | | | setcc({regdef4,regvar($2)}) | | |
#endif REGVARS #endif /* REGVARS */
rol sil $1==4 && $2<0 rol sil $1==4 && $2<0
| source4 source4 | | source4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -2774,7 +2774,7 @@ ror stl $1==4 && inreg($2)==2
"rotl\t$$%(32-%[1.num]%),%[2],%(regvar($2)%)" "rotl\t$$%(32-%[1.num]%),%[2],%(regvar($2)%)"
erase(regvar($2)) erase(regvar($2))
setcc(regvar($2)) | | | setcc(regvar($2)) | | |
#endif REGVARS #endif /* REGVARS */
ror stl $1==4 && $2<0 ror stl $1==4 && $2<0
| source4 source4 | | source4 source4 |
remove(displaced) remove(displaced)
@ -2813,7 +2813,7 @@ ror sil $1==4 && inreg($2)==2
REMEXTANDLOC REMEXTANDLOC
"rotl\t$$%(32-%[1.num]%),%[2],(%(regvar($2)%))" "rotl\t$$%(32-%[1.num]%),%[2],(%(regvar($2)%))"
setcc({regdef4,regvar($2)}) | | | setcc({regdef4,regvar($2)}) | | |
#endif REGVARS #endif /* REGVARS */
ror sil $1==4 && $2<0 ror sil $1==4 && $2<0
| source4 source4 | | source4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -2867,7 +2867,7 @@ com and stl $1==4 && $2==4 && inreg($3)==2
"bicl3\t%[1],%[2],%(regvar($3)%)" "bicl3\t%[1],%[2],%(regvar($3)%)"
erase(regvar($3)) erase(regvar($3))
setcc(regvar($3)) | | | setcc(regvar($3)) | | |
#endif REGVARS #endif /* REGVARS */
com and stl $1==4 && $2==4 && $3<0 com and stl $1==4 && $2==4 && $3<0
| source4 source4 | | source4 source4 |
remove(displaced) remove(displaced)
@ -2886,7 +2886,7 @@ com and sil $1==4 && $2==4 && inreg($3)==2
REMEXTANDLOC REMEXTANDLOC
"bicl3\t%[1],%[2],(%(regvar($3)%))" "bicl3\t%[1],%[2],(%(regvar($3)%))"
setcc({regdef4,regvar($3)}) | | | setcc({regdef4,regvar($3)}) | | |
#endif REGVARS #endif /* REGVARS */
com and sil $1==4 && $2==4 && $3<0 com and sil $1==4 && $2==4 && $3<0
| source4 source4 | | source4 source4 |
REMEXTANDLOC REMEXTANDLOC
@ -3715,7 +3715,7 @@ cmf tgt $1==4 | source4 source4 |
#endif #endif
erase(%[a]) erase(%[a])
setcc(%[a]) | %[a] | | setcc(%[a]) | %[a] | |
#endif FLOAT4 #endif /* FLOAT4 */
#ifdef FLOAT8 #ifdef FLOAT8
cmf tlt $1==8 | source8 source8 | cmf tlt $1==8 | source8 source8 |
allocate(%[1],%[2],REG) allocate(%[1],%[2],REG)
@ -3814,7 +3814,7 @@ cmf tgt $1==8 | source8 source8 |
#endif #endif
erase(%[a]) erase(%[a])
setcc(%[a]) | %[a] | | setcc(%[a]) | %[a] | |
#endif FLOAT8 #endif /* FLOAT8 */
/* Remember that cmu was replaced by cmp. */ /* Remember that cmu was replaced by cmp. */
cmp tlt | source4 source4 | cmp tlt | source4 source4 |
allocate(REG={CONST1,0}) allocate(REG={CONST1,0})
@ -4313,9 +4313,9 @@ ret $1==8 | NC bigsource8 |
#ifdef REGVARS #ifdef REGVARS
asp $1==4 | bigsource4 - regch4 | | | | asp $1==4 | bigsource4 - regch4 | | | |
#else REGVARS #else /* REGVARS */
asp $1==4 | NC bigsource4 | | | | asp $1==4 | NC bigsource4 | | | |
#endif REGVARS #endif /* REGVARS */
... | STACK | ... | STACK |
"tstl\t(sp)+" | | | (2,7) "tstl\t(sp)+" | | | (2,7)
asp $1>0 | STACK | asp $1>0 | STACK |
@ -4388,9 +4388,9 @@ dup stl $1==4 | | | | stl $2 lol $2 |
dup $1==4 | dups4 | | %[1] %[1] | | dup $1==4 | dups4 | | %[1] %[1] | |
#ifdef REGVARS #ifdef REGVARS
dup $1==8 | bigsource8-regch8 | | %[1] %[1] | | dup $1==8 | bigsource8-regch8 | | %[1] %[1] | |
#else REGVARS #else /* REGVARS */
dup $1==8 | bigsource8 | | %[1] %[1] | | dup $1==8 | bigsource8 | | %[1] %[1] | |
#endif REGVARS #endif /* REGVARS */
... | dups4 dups4 | | %[2] %[1] %[2] %[1] | | ... | dups4 dups4 | | %[2] %[1] %[2] %[1] | |
dup | STACK | dup | STACK |
allocate(REG,REG={CONST1,$1/4}) allocate(REG,REG={CONST1,$1/4})
@ -4467,15 +4467,15 @@ rck !defined($1) | source4 |
move(%[1],R0) move(%[1],R0)
"jsb\t.rck" "jsb\t.rck"
erase(R0) | | | erase(R0) | | |
#else DORCK #else /* DORCK */
#ifdef REGVARS #ifdef REGVARS
rck defined($1) | bigsource4-regch4 | | | | rck defined($1) | bigsource4-regch4 | | | |
rck !defined($1) | bigsource4-regch4 bigsource4-regch4 | | | | rck !defined($1) | bigsource4-regch4 bigsource4-regch4 | | | |
#else REGVARS #else /* REGVARS */
rck defined($1) | bigsource4 | | | | rck defined($1) | bigsource4 | | | |
rck !defined($1) | bigsource4 bigsource4 | | | | rck !defined($1) | bigsource4 bigsource4 | | | |
#endif REGVARS #endif /* REGVARS */
#endif DORCK #endif /* DORCK */
rtt | | "ret" | | | rtt | | "ret" | | |
sig | STACK | sig | STACK |
"jsb\t.sig" | | | "jsb\t.sig" | | |
@ -4576,7 +4576,7 @@ MOVES:
setcc(%[2]) erase(%[2]),(3,4)+%[1]) setcc(%[2]) erase(%[2]),(3,4)+%[1])
(reginc8+regdec8,reg8, "movq\t%[1],%[2]" (reginc8+regdec8,reg8, "movq\t%[1],%[2]"
setcc(%[2]) erase(%[2]),(3,7)+%[1]) setcc(%[2]) erase(%[2]),(3,7)+%[1])
#endif REGVARS #endif /* REGVARS */
(source8,source8, "movq\t%[1],%[2]" (source8,source8, "movq\t%[1],%[2]"
setcc(%[2]), (3,4)+%[1]+%[2]) setcc(%[2]), (3,4)+%[1]+%[2])
(source4,source4, "movl\t%[1],%[2]" (source4,source4, "movl\t%[1],%[2]"

2
modules/src/em_opt/nopt.c
View file

@ -39,7 +39,7 @@ int OO_wrstats = 1; /* pattern statistics output */
#define printstate(s) dumpstate(s) #define printstate(s) dumpstate(s)
#else #else
#define printstate(s) #define printstate(s)
#endif DEBUG #endif /* DEBUG */
/**** WHICH IS FASTER? **** /**** WHICH IS FASTER? ****
#define BTSCPY(pp,qq,i,p,q,n) btscpy(p,q,(n)*sizeof(struct e_instr)) #define BTSCPY(pp,qq,i,p,q,n) btscpy(p,q,(n)*sizeof(struct e_instr))