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Do a move when coercing FREG to FREG or FSREG to FSREG.

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This commit is contained in:
George Koehler 2017-10-16 12:07:55 -04:00
parent f0619ea4ae
commit 5432bd03d6
1 changed files with 19 additions and 25 deletions
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44
mach/powerpc/ncg/table
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@ -630,13 +630,6 @@ STACKINGRULES
COERCIONS
from ANY_BHW
uses REG
gen
COMMENT("coerce ANY_BHW->REG")
move %1, %a
yields %a
from STACK
uses REG
gen
@ -645,18 +638,6 @@ COERCIONS
addi sp, sp, {CONST, 4}
yields %a
from FSREG
uses FSREG
gen
fmr %a, %1
yields %a
from FREG
uses FREG
gen
fmr %a, %1
yields %a
from STACK
uses FREG
gen
@ -673,21 +654,34 @@ COERCIONS
addi sp, sp, {CONST, 4}
yields %a
from IND_ALL_W
uses FSREG
from ANY_BHW
uses REG
gen
COMMENT("coerce ANY_BHW->REG")
move %1, %a
yields %a
/*
* from IND_RC_D to REG REG is not possible, because
* %1.off+4 might overflow a signed 16-bit integer in
* move {IND_RC_W, %1.val, %1.off+4}, %a
* There is no coercion from IND_ALL_D to REG REG, because
* coercions can't allocate registers for intermediate values.
*
* A coercion to split IND_RC_D into two IND_RC_W, without
* allocating an intermediate register, would yield
* {IND_RC_W, %1.val, %1.off+4}
* but %1.off+4 might overflow a signed 16-bit integer.
*/
from IND_ALL_D
from FREG+IND_ALL_D
uses FREG
gen
COMMENT("coerce FREG+IND_ALL_D->FREG")
move %1, %a
yields %a
from FSREG+IND_ALL_W
uses FSREG
gen
COMMENT("coerce FSREG+IND_ALL_W->FREG")
move %1, %a
yields %a