ACK VAX assembler, first version
This commit is contained in:
ceriel
parent
0004fd81ed
commit
57dfc84ee7
7 changed files with 1212 additions and 0 deletions
7
mach/vax4/as/.distr
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7
mach/vax4/as/.distr
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Makefile
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mach0.c
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mach1.c
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mach2.c
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mach3.c
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mach4.c
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mach5.c
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23
mach/vax4/as/mach0.c
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23
mach/vax4/as/mach0.c
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/*
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* (c) copyright 1990 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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#define RCSID0 "$Header$"
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/*
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* VAX-11 machine dependent options
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*/
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#define THREE_PASS
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#define LISTING
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#define RELOCATION
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#undef valu_t
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#define valu_t long
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#undef addr_t
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#define addr_t long
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#undef ALIGNWORD
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#define ALIGNWORD 4
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#undef ALIGNSECT
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#define ALIGNSECT 4
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51
mach/vax4/as/mach1.c
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51
mach/vax4/as/mach1.c
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/*
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* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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#define RCSID1 "$Header$"
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/*
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* VAX-11 Machine dependent C declarations
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*/
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/* Addressing modes */
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#define REG_MODE 5
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#define REGDEF_MODE 6
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#define AI_MODE 8
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#define AI_DEF_MODE 9
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#define AD_MODE 7
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#define DISPLB_MODE 10
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#define DISPLW_MODE 12
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#define DISPLL_MODE 14
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#define DISPLB_DEF_MODE 11
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#define DISPLW_DEF_MODE 13
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#define DISPLL_DEF_MODE 15
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#define INDEX_MODE 4
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#define DISPL 16 /* not an addressing mode; used for branch
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displacement addressing
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*/
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#define IMM 17 /* immediate mode (only for internal use) */
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#define ABS 18 /* absolute mode (only for internal use) */
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#define ABS_DEF 19 /* absolute deferred mode (only for internal use) */
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#define PC 15 /* special case */
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#define fit8(z) (lowb(z) == (z))
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#define fit16(z) (loww(z) == (z))
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#define literal(z) (((z) & ~0x3f) == 0)
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struct operand {
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expr_t exp;
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int mode; /* addressing mode */
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int reg; /* register used in addressing mode */
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int relo; /* index in relocation table for exp */
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int size; /* size as imposed by instruction */
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int index_reg; /* for indexed mode contains index reg,
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-1 if not index mode
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*/
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};
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extern struct operand opnd[6];
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extern int op_ind;
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38
mach/vax4/as/mach2.c
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38
mach/vax4/as/mach2.c
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/*
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* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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#define RCSID2 "$Header$"
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/*
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* VAX-11 machine dependent yacc declarations
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*/
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%token <y_word> REG
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%token <y_word> CASE_b_b_b, CASE_l_l_l, CASE_w_w_w
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%token <y_word> OP0
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%token <y_word> OP1_A, OP1_Bb, OP1_Bl, OP1_Bw, OP1_Bx, OP1_b, OP1_l, OP1_u,
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OP1_w, OP1_Be
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%token <y_word> OP2_A_A, OP2_A_l, OP2_b_b, OP2_b_l, OP2_b_u, OP2_b_w, OP2_l_A,
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OP2_l_Bb, OP2_l_b, OP2_l_l, OP2_l_u, OP2_l_w, OP2_u_b, OP2_u_l,
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OP2_u_u, OP2_u_w, OP2_w_b, OP2_w_l, OP2_w_u, OP2_w_w, OP2_l_Be
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%token <y_word> OP3_b_b_b, OP3_b_l_l, OP3_b_u_u, OP3_b_w_A, OP3_l_V_Bb,
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OP3_l_l_Bb, OP3_l_l_l, OP3_l_w_A, OP3_u_u_u, OP3_u_w_A,
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OP3_w_A_A, OP3_w_A_l, OP3_w_w_w, OP3_l_V_Be
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%token <y_word> OP4_A_l_w_A, OP4_b_b_b_Bw, OP4_l_b_V_l, OP4_l_l_b_V,
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OP4_l_l_l_Bw, OP4_l_l_l_u, OP4_l_u_l_l, OP4_u_u_u_Bw,
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OP4_w_A_A_A, OP4_w_A_A_b, OP4_w_A_w_A, OP4_w_w_w_Bw
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%token <y_word> OP5_u_b_u_l_u, OP5_u_w_u_l_u, OP5_w_A_A_w_A, OP5_w_A_b_w_A
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%token <y_word> OP6_b_w_A_b_w_A, OP6_l_l_l_l_l_l, OP6_w_A_b_A_w_A,
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OP6_w_A_w_A_w_A
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%token <y_word>
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%type <y_word> OP1_O, OP1_B
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%type <y_word> OP2_O_O, OP2_A_O, OP2_O_B, OP2_O_A
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%type <y_word> OP3_O_O_O, OP3_O_O_B, OP3_O_O_A, OP3_O_A_A, OP3_O_A_O
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%type <y_word> OP4_O_O_O_O, OP4_O_O_O_B, OP4_O_A_O_A, OP4_O_A_A_O,
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OP4_O_A_A_A, OP4_A_O_O_A
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%type <y_word> OP5_O_A_A_O_A, OP5_O_A_O_O_A, OP5_O_O_O_O_O
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%type <y_word> OP6_O_O_O_O_O_O, OP6_O_A_O_A_O_A, OP6_O_O_A_O_O_A
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%type <y_word> CASE_O_O_O
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%type <y_word> oper
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427
mach/vax4/as/mach3.c
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427
mach/vax4/as/mach3.c
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/* $Header$ */
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/*
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* (c) copyright 1990 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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/*
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* VAX-11 keywords
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*/
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0, REG, 0, "r0",
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0, REG, 1, "r1",
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0, REG, 2, "r2",
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0, REG, 3, "r3",
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0, REG, 4, "r4",
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0, REG, 5, "r5",
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0, REG, 6, "r6",
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0, REG, 7, "r7",
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0, REG, 8, "r8",
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0, REG, 9, "r9",
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0, REG, 10, "r10",
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0, REG, 11, "r11",
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0, REG, 12, "r12",
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0, REG, 12, "ap",
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0, REG, 13, "r13",
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0, REG, 13, "fp",
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0, REG, 14, "r14",
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0, REG, 14, "sp",
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0, REG, 15, "r15",
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0, REG, 15, "pc",
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/* For immediate mode, we need the size as specified by the instruction.
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Ordinary operands are therefore encoded as _w, _b, and _l to indicate
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size.
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For now, immediate floating point and immediate values of size > 4 are not
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implemented. _u is used for this.
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*/
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/* integer arithmetic and logical instructions */
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0, OP2_w_w, 0x58, "adawi",
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0, OP2_b_b, 0x80, "addb2",
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0, OP3_b_b_b, 0x81, "addb3",
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0, OP2_w_w, 0xa0, "addw2",
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0, OP3_w_w_w, 0xa1, "addw3",
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0, OP2_l_l, 0xc0, "addl2",
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0, OP3_l_l_l, 0xc1, "addl3",
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0, OP2_l_l, 0xd8, "adwc",
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0, OP3_b_l_l, 0x78, "ashl",
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0, OP3_b_u_u, 0x79, "ashq",
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0, OP2_b_b, 0x8a, "bicb2",
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0, OP3_b_b_b, 0x8b, "bicb3",
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0, OP2_w_w, 0xaa, "bicw2",
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0, OP3_w_w_w, 0xab, "bicw3",
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0, OP2_l_l, 0xca, "bicl2",
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0, OP3_l_l_l, 0xcb, "bicl3",
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0, OP2_b_b, 0x88, "bisb2",
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0, OP3_b_b_b, 0x89, "bisb3",
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0, OP2_w_w, 0xa8, "bisw2",
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0, OP3_w_w_w, 0xa9, "bisw3",
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0, OP2_l_l, 0xc8, "bisl2",
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0, OP3_l_l_l, 0xc9, "bisl3",
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0, OP2_b_b, 0x93, "bitb",
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0, OP2_w_w, 0xb3, "bitw",
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0, OP2_l_l, 0xd3, "bitl",
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0, OP1_b, 0x94, "clrb",
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0, OP1_w, 0xb4, "clrw",
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0, OP1_l, 0xd4, "clrl",
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0, OP1_u, 0x7c, "clrq",
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0, OP1_u, 0x7cfd, "clro",
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0, OP2_b_b, 0x91, "cmpb",
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0, OP2_w_w, 0xb1, "cmpw",
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0, OP2_l_l, 0xd1, "cmpl",
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0, OP2_b_w, 0x99, "cvtbw",
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0, OP2_b_l, 0x98, "cvtbl",
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0, OP2_w_b, 0x33, "cvtwb",
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0, OP2_w_l, 0x32, "cvtwl",
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0, OP2_l_b, 0xf6, "cvtlb",
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0, OP2_l_w, 0xf7, "cvtlw",
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0, OP1_b, 0x97, "decb",
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0, OP1_w, 0xb7, "decw",
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0, OP1_l, 0xd7, "decl",
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0, OP2_b_b, 0x86, "divb2",
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0, OP3_b_b_b, 0x87, "divb3",
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0, OP2_w_w, 0xa6, "divw2",
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0, OP3_w_w_w, 0xa7, "divw3",
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0, OP2_l_l, 0xc6, "divl2",
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0, OP3_l_l_l, 0xc7, "divl3",
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0, OP4_l_u_l_l, 0x7b, "ediv",
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0, OP4_l_l_l_u, 0x7a, "emul",
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0, OP1_b, 0x96, "incb",
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0, OP1_w, 0xb6, "incw",
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0, OP1_l, 0xd6, "incl",
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0, OP2_b_b, 0x92, "mcomb",
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0, OP2_w_w, 0xb2, "mcomw",
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0, OP2_l_l, 0xd2, "mcoml",
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0, OP2_b_b, 0x8e, "mnegb",
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0, OP2_w_w, 0xae, "mnegw",
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0, OP2_l_l, 0xce, "mnegl",
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0, OP2_b_b, 0x90, "movb",
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0, OP2_w_w, 0xb0, "movw",
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0, OP2_l_l, 0xd0, "movl",
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0, OP2_u_u, 0x7d, "movq",
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0, OP2_u_u, 0x7dfd, "movo",
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0, OP2_b_w, 0x9b, "movzbw",
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0, OP2_b_l, 0x9a, "movzbl",
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0, OP2_w_l, 0x3c, "movzwl",
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0, OP2_b_b, 0x84, "mulb2",
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0, OP3_b_b_b, 0x85, "mulb3",
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0, OP2_w_w, 0xa4, "mulw2",
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0, OP3_w_w_w, 0xa5, "mulw3",
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0, OP2_l_l, 0xc4, "mull2",
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0, OP3_l_l_l, 0xc5, "mull3",
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0, OP1_l, 0xdd, "pushl",
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0, OP3_b_l_l, 0x9c, "rotl",
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0, OP2_l_l, 0xd9, "sbwc",
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0, OP2_b_b, 0x82, "subb2",
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0, OP3_b_b_b, 0x83, "subb3",
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0, OP2_w_w, 0xa2, "subw2",
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0, OP3_w_w_w, 0xa3, "subw3",
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0, OP2_l_l, 0xc2, "subl2",
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0, OP3_l_l_l, 0xc3, "subl3",
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0, OP1_b, 0x95, "tstb",
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0, OP1_w, 0xb5, "tstw",
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0, OP1_l, 0xd5, "tstl",
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0, OP2_b_b, 0x8c, "xorb2",
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0, OP3_b_b_b, 0x8d, "xorb3",
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0, OP2_w_w, 0xac, "xorw2",
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0, OP3_w_w_w, 0xad, "xorw3",
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0, OP2_l_l, 0xcc, "xorl2",
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0, OP3_l_l_l, 0xcd, "xorl3",
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/* Address instructions */
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0, OP2_A_l, 0x9e, "movab",
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0, OP2_A_l, 0x3e, "movaw",
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0, OP2_A_l, 0xde, "moval",
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0, OP2_A_l, 0xde, "movaf",
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0, OP2_A_l, 0x7e, "movaq",
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0, OP2_A_l, 0x7e, "movad",
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0, OP2_A_l, 0x7e, "movag",
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0, OP2_A_l, 0x7efd, "movah",
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0, OP2_A_l, 0x7efd, "movao",
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0, OP1_A, 0x9f, "pushab",
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0, OP1_A, 0x3f, "pushaw",
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0, OP1_A, 0xdf, "pushal",
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0, OP1_A, 0xdf, "pushaf",
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0, OP1_A, 0x7f, "pushaq",
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0, OP1_A, 0x7f, "pushad",
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0, OP1_A, 0x7f, "pushag",
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0, OP1_A, 0x7ffd, "pushah",
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0, OP1_A, 0x7ffd, "pushao",
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/* Variable length bit-field instructions */
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0, OP4_l_b_V_l, 0xec, "cmpv",
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0, OP4_l_b_V_l, 0xed, "cmpzv",
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0, OP4_l_b_V_l, 0xee, "extv",
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0, OP4_l_b_V_l, 0xef, "extzv",
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0, OP4_l_b_V_l, 0xeb, "ffc",
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0, OP4_l_b_V_l, 0xea, "ffs",
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0, OP4_l_l_b_V, 0xf0, "insv",
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/* Control instructions */
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0, OP4_b_b_b_Bw, 0x9d, "acbb",
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0, OP4_w_w_w_Bw, 0x3d, "acbw",
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0, OP4_l_l_l_Bw, 0xf1, "acbl",
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0, OP4_u_u_u_Bw, 0x4f, "acbf",
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0, OP4_u_u_u_Bw, 0x6f, "acbd",
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0, OP4_u_u_u_Bw, 0x4ffd, "acbg",
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0, OP4_u_u_u_Bw, 0x6ffd, "acbh",
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0, OP3_l_l_Bb, 0xf3, "aobleq",
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0, OP3_l_l_Bb, 0xf2, "aoblss",
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0, OP1_Bb, 0x14, "bgtr",
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0, OP1_Bb, 0x15, "bleq",
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0, OP1_Bb, 0x12, "bneq",
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0, OP1_Bb, 0x12, "bnequ",
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0, OP1_Bb, 0x13, "beql",
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0, OP1_Bb, 0x13, "beqlu",
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0, OP1_Bb, 0x18, "bgeq",
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0, OP1_Bb, 0x19, "blss",
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0, OP1_Bb, 0x1a, "bgtru",
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0, OP1_Bb, 0x1b, "blequ",
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0, OP1_Bb, 0x1c, "bvc",
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0, OP1_Bb, 0x1d, "bvs",
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0, OP1_Bb, 0x1e, "bgequ",
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0, OP1_Bb, 0x1e, "bcc",
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0, OP1_Bb, 0x1f, "blssu",
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0, OP1_Bb, 0x1f, "bcs",
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0, OP3_l_V_Bb, 0xe0, "bbs",
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0, OP3_l_V_Bb, 0xe1, "bbc",
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0, OP3_l_V_Bb, 0xe2, "bbss",
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0, OP3_l_V_Bb, 0xe3, "bbcs",
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0, OP3_l_V_Bb, 0xe4, "bbsc",
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0, OP3_l_V_Bb, 0xe5, "bbcc",
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0, OP3_l_V_Bb, 0xe6, "bbssi",
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0, OP3_l_V_Bb, 0xe7, "bbcci",
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0, OP2_l_Bb, 0xe8, "blbs",
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0, OP2_l_Bb, 0xe9, "blbc",
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0, OP1_Be, 0x14, "jgtr",
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0, OP1_Be, 0x15, "jleq",
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0, OP1_Be, 0x12, "jneq",
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0, OP1_Be, 0x12, "jnequ",
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0, OP1_Be, 0x13, "jeql",
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0, OP1_Be, 0x13, "jeqlu",
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0, OP1_Be, 0x18, "jgeq",
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0, OP1_Be, 0x19, "jlss",
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0, OP1_Be, 0x1a, "jgtru",
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0, OP1_Be, 0x1b, "jlequ",
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0, OP1_Be, 0x1c, "jvc",
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0, OP1_Be, 0x1d, "jvs",
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0, OP1_Be, 0x1e, "jgequ",
|
||||
0, OP1_Be, 0x1e, "jcc",
|
||||
0, OP1_Be, 0x1f, "jlssu",
|
||||
0, OP1_Be, 0x1f, "jcs",
|
||||
0, OP2_l_Be, 0xe8, "jlbs",
|
||||
0, OP2_l_Be, 0xe9, "jlbc",
|
||||
0, OP3_l_V_Be, 0xe0, "jbs",
|
||||
0, OP3_l_V_Be, 0xe1, "jbc",
|
||||
0, OP3_l_V_Be, 0xe2, "jbss",
|
||||
0, OP3_l_V_Be, 0xe3, "jbcs",
|
||||
0, OP3_l_V_Be, 0xe4, "jbsc",
|
||||
0, OP3_l_V_Be, 0xe5, "jbcc",
|
||||
0, OP3_l_V_Be, 0xe6, "jbssi",
|
||||
0, OP3_l_V_Be, 0xe7, "jbcci",
|
||||
0, OP1_Bx, 0x11, "br",
|
||||
0, OP1_Bb, 0x11, "brb",
|
||||
0, OP1_Bw, 0x31, "brw",
|
||||
0, OP1_Be, 0x11, "jbr",
|
||||
0, OP1_Bx, 0x10, "bsb",
|
||||
0, CASE_b_b_b, 0x8f, "caseb",
|
||||
0, CASE_w_w_w, 0xaf, "casew",
|
||||
0, CASE_l_l_l, 0xcf, "casel",
|
||||
0, OP1_A, 0x17, "jmp",
|
||||
0, OP1_A, 0x16, "jsb",
|
||||
0, OP0, 0x05, "rsb",
|
||||
0, OP2_l_Bb, 0xf4, "sobgeq",
|
||||
0, OP2_l_Bb, 0xf5, "sobgtr",
|
||||
|
||||
/* Procedure call instructions */
|
||||
|
||||
0, OP2_A_A, 0xfa, "callg",
|
||||
0, OP2_l_A, 0xfb, "calls",
|
||||
0, OP0, 0x04, "ret",
|
||||
|
||||
/* Miscellaneous instructions */
|
||||
|
||||
0, OP1_w, 0xb9, "bicpsw",
|
||||
0, OP1_w, 0xb8, "bispsw",
|
||||
0, OP0, 0x03, "bpt",
|
||||
0, OP0, 0x00, "halt",
|
||||
0, OP6_l_l_l_l_l_l,0x0a, "index",
|
||||
0, OP1_l, 0xdc, "movpsl",
|
||||
0, OP0, 0x01, "nop",
|
||||
0, OP1_w, 0xba, "popr",
|
||||
0, OP1_w, 0xbb, "pushr",
|
||||
0, OP0, 0xfc, "xfc",
|
||||
|
||||
/* Queue instructions */
|
||||
|
||||
0, OP2_A_A, 0x5c, "insqhi",
|
||||
0, OP2_A_A, 0x5d, "insqti",
|
||||
0, OP2_A_A, 0x0e, "insque",
|
||||
0, OP2_A_l, 0x5e, "remqhi",
|
||||
0, OP2_A_l, 0x5f, "remqti",
|
||||
0, OP2_A_l, 0x0f, "remque",
|
||||
|
||||
/* Floating point instructions */
|
||||
|
||||
0, OP2_u_u, 0x40, "addf2",
|
||||
0, OP3_u_u_u, 0x41, "addf3",
|
||||
0, OP2_u_u, 0x60, "addd2",
|
||||
0, OP3_u_u_u, 0x61, "addd3",
|
||||
0, OP2_u_u, 0x40fd, "addg2",
|
||||
0, OP3_u_u_u, 0x41fd, "addg3",
|
||||
0, OP2_u_u, 0x60fd, "addh2",
|
||||
0, OP3_u_u_u, 0x61fd, "addh3",
|
||||
0, OP1_u, 0xd4, "clrf",
|
||||
0, OP1_u, 0x7c, "clrd",
|
||||
0, OP1_u, 0x7c, "clrg",
|
||||
0, OP1_u, 0x7cfd, "clrh",
|
||||
0, OP2_u_u, 0x51, "cmpf",
|
||||
0, OP2_u_u, 0x71, "cmpd",
|
||||
0, OP2_u_u, 0x51fd, "cmpg",
|
||||
0, OP2_u_u, 0x71fd, "cmph",
|
||||
0, OP2_b_u, 0x4c, "cvtbf",
|
||||
0, OP2_b_u, 0x6c, "cvtbd",
|
||||
0, OP2_b_u, 0x4cfd, "cvtbg",
|
||||
0, OP2_b_u, 0x6cfd, "cvtbh",
|
||||
0, OP2_w_u, 0x4d, "cvtwf",
|
||||
0, OP2_w_u, 0x6d, "cvtwd",
|
||||
0, OP2_w_u, 0x4dfd, "cvtwg",
|
||||
0, OP2_w_u, 0x6dfd, "cvtwh",
|
||||
0, OP2_l_u, 0x4e, "cvtlf",
|
||||
0, OP2_l_u, 0x6e, "cvtld",
|
||||
0, OP2_l_u, 0x4efd, "cvtlg",
|
||||
0, OP2_l_u, 0x6efd, "cvtlh",
|
||||
0, OP2_u_b, 0x48, "cvtfb",
|
||||
0, OP2_u_b, 0x68, "cvtdb",
|
||||
0, OP2_u_b, 0x48fd, "cvtgb",
|
||||
0, OP2_u_b, 0x68fd, "cvthb",
|
||||
0, OP2_u_w, 0x49, "cvtfw",
|
||||
0, OP2_u_w, 0x69, "cvtdw",
|
||||
0, OP2_u_w, 0x49fd, "cvtgw",
|
||||
0, OP2_u_w, 0x69fd, "cvthw",
|
||||
0, OP2_u_l, 0x4a, "cvtfl",
|
||||
0, OP2_u_l, 0x6a, "cvtdl",
|
||||
0, OP2_u_l, 0x4afd, "cvtgl",
|
||||
0, OP2_u_l, 0x6afd, "cvthl",
|
||||
0, OP2_u_l, 0x4b, "cvtrfl",
|
||||
0, OP2_u_l, 0x6b, "cvtrdl",
|
||||
0, OP2_u_l, 0x4bfd, "cvtrgl",
|
||||
0, OP2_u_l, 0x6bfd, "cvtrhl",
|
||||
0, OP2_u_u, 0x56, "cvtfd",
|
||||
0, OP2_u_u, 0x99fd, "cvtfg",
|
||||
0, OP2_u_u, 0x98fd, "cvtfh",
|
||||
0, OP2_u_u, 0x76, "cvtdf",
|
||||
0, OP2_u_u, 0x32fd, "cvtdh",
|
||||
0, OP2_u_u, 0x33fd, "cvtgf",
|
||||
0, OP2_u_u, 0x56fd, "cvtgh",
|
||||
0, OP2_u_u, 0xf6fd, "cvthf",
|
||||
0, OP2_u_u, 0xf7fd, "cvthd",
|
||||
0, OP2_u_u, 0x76fd, "cvthg",
|
||||
0, OP2_u_u, 0x46, "divf2",
|
||||
0, OP3_u_u_u, 0x47, "divf3",
|
||||
0, OP2_u_u, 0x66, "divd2",
|
||||
0, OP3_u_u_u, 0x67, "divd3",
|
||||
0, OP2_u_u, 0x46fd, "divg2",
|
||||
0, OP3_u_u_u, 0x47fd, "divg3",
|
||||
0, OP2_u_u, 0x66fd, "divh2",
|
||||
0, OP3_u_u_u, 0x67fd, "divh3",
|
||||
0, OP5_u_b_u_l_u, 0x54, "emodf",
|
||||
0, OP5_u_b_u_l_u, 0x74, "emodd",
|
||||
0, OP5_u_w_u_l_u, 0x54fd, "emodg",
|
||||
0, OP5_u_w_u_l_u, 0x74fd, "emodh",
|
||||
0, OP2_u_u, 0x52, "mnegf",
|
||||
0, OP2_u_u, 0x72, "mnegd",
|
||||
0, OP2_u_u, 0x52fd, "mnegg",
|
||||
0, OP2_u_u, 0x72fd, "mnegh",
|
||||
0, OP2_u_u, 0x50, "movf",
|
||||
0, OP2_u_u, 0x70, "movd",
|
||||
0, OP2_u_u, 0x50fd, "movg",
|
||||
0, OP2_u_u, 0x70fd, "movh",
|
||||
0, OP2_u_u, 0x44, "mulf2",
|
||||
0, OP3_u_u_u, 0x45, "mulf3",
|
||||
0, OP2_u_u, 0x64, "muld2",
|
||||
0, OP3_u_u_u, 0x65, "muld3",
|
||||
0, OP2_u_u, 0x44fd, "mulg2",
|
||||
0, OP3_u_u_u, 0x45fd, "mulg3",
|
||||
0, OP2_u_u, 0x64fd, "mulh2",
|
||||
0, OP3_u_u_u, 0x65fd, "mulh3",
|
||||
0, OP3_u_w_A, 0x55, "polyf",
|
||||
0, OP3_u_w_A, 0x75, "polyd",
|
||||
0, OP3_u_w_A, 0x55fd, "polyg",
|
||||
0, OP3_u_w_A, 0x75fd, "polyh",
|
||||
0, OP2_u_u, 0x42, "subf2",
|
||||
0, OP3_u_u_u, 0x43, "subf3",
|
||||
0, OP2_u_u, 0x62, "subd2",
|
||||
0, OP3_u_u_u, 0x63, "subd3",
|
||||
0, OP2_u_u, 0x42fd, "subg2",
|
||||
0, OP3_u_u_u, 0x43fd, "subg3",
|
||||
0, OP2_u_u, 0x62fd, "subh2",
|
||||
0, OP3_u_u_u, 0x63fd, "subh3",
|
||||
0, OP1_u, 0x53, "tstf",
|
||||
0, OP1_u, 0x73, "tstd",
|
||||
0, OP1_u, 0x53fd, "tstg",
|
||||
0, OP1_u, 0x73fd, "tsth",
|
||||
|
||||
/* Character string instructions */
|
||||
|
||||
0, OP3_w_A_A, 0x29, "cmpc3",
|
||||
0, OP5_w_A_b_w_A, 0x2d, "cmpc5",
|
||||
0, OP3_b_w_A, 0x3a, "locc",
|
||||
0, OP4_w_A_w_A, 0x39, "matchc",
|
||||
0, OP3_w_A_A, 0x28, "movc3",
|
||||
0, OP5_w_A_b_w_A, 0x2c, "movc5",
|
||||
0, OP6_w_A_b_A_w_A,0x2e, "movtc",
|
||||
0, OP6_w_A_b_A_w_A,0x2f, "movtuc",
|
||||
0, OP4_w_A_A_b, 0x2a, "scanc",
|
||||
0, OP3_b_w_A, 0x3b, "skpc",
|
||||
0, OP4_w_A_A_b, 0x2b, "spanc",
|
||||
|
||||
/* Cyclic redundancy check instructions */
|
||||
|
||||
0, OP4_A_l_w_A, 0x0b, "crc",
|
||||
|
||||
/* Decimal string instructions */
|
||||
|
||||
0, OP4_w_A_w_A, 0x20, "addp4",
|
||||
0, OP6_w_A_w_A_w_A,0x21, "addp6",
|
||||
0, OP6_b_w_A_b_w_A,0xf8, "ashp",
|
||||
0, OP3_w_A_A, 0x35, "cmpp3",
|
||||
0, OP4_w_A_w_A, 0x37, "cmpp4",
|
||||
0, OP3_l_w_A, 0xf9, "cvtlp",
|
||||
0, OP3_w_A_l, 0x36, "cvtpl",
|
||||
0, OP4_w_A_w_A, 0x08, "cvtps",
|
||||
0, OP5_w_A_A_w_A, 0x24, "cvtpt",
|
||||
0, OP4_w_A_w_A, 0x09, "cvtsp",
|
||||
0, OP5_w_A_A_w_A, 0x26, "cvttp",
|
||||
0, OP6_w_A_w_A_w_A,0x27, "divp",
|
||||
0, OP3_w_A_A, 0x34, "movp",
|
||||
0, OP6_w_A_w_A_w_A,0x25, "mulp",
|
||||
0, OP4_w_A_w_A, 0x22, "subp4",
|
||||
0, OP6_w_A_w_A_w_A,0x23, "subp6",
|
||||
|
||||
/* Edit instruction */
|
||||
|
||||
0, OP4_w_A_A_A, 0x38, "editpc",
|
||||
|
||||
/* Other VAX-11 instructions */
|
||||
|
||||
0, OP1_Bw, 0xfeff, "bugw", /* ??? */
|
||||
0, OP1_Bl, 0xfdff, "bugl", /* ??? */
|
||||
|
||||
0, OP3_b_w_A, 0x0c, "prober",
|
||||
0, OP3_b_w_A, 0x0d, "probew",
|
||||
|
||||
0, OP0, 0x02, "rei",
|
||||
0, OP1_w, 0xbc, "chmk",
|
||||
0, OP1_w, 0xbd, "chme",
|
||||
0, OP1_w, 0xbe, "chms",
|
||||
0, OP1_w, 0xbf, "chmu",
|
||||
|
||||
0, OP0, 0x06, "ldpctx",
|
||||
0, OP0, 0x07, "svpctx",
|
||||
0, OP2_l_l, 0xda, "mtpr",
|
||||
0, OP2_l_l, 0xdb, "mfpr",
|
||||
380
mach/vax4/as/mach4.c
Normal file
380
mach/vax4/as/mach4.c
Normal file
|
|
@ -0,0 +1,380 @@
|
|||
/*
|
||||
* (c) copyright 1990 by the Vrije Universiteit, Amsterdam, The Netherlands.
|
||||
* See the copyright notice in the ACK home directory, in the file "Copyright".
|
||||
*/
|
||||
#define RCSID4 "$Header$"
|
||||
|
||||
/*
|
||||
* VAX-11 machine dependent yacc syntax rules
|
||||
*/
|
||||
|
||||
/* _b, _w, and _l are ordinary READ/MODIFY/WRITE operands, the letter indicates
|
||||
the size,
|
||||
A means effective ADDRESS (must be memory),
|
||||
B means branch displacement,
|
||||
V means effective address or register;
|
||||
Here, no difference is made between Modify and Write.
|
||||
*/
|
||||
|
||||
operation
|
||||
:
|
||||
{ op_ind = 0; }
|
||||
oper
|
||||
{ if ((unsigned) $2 < 0x100) {
|
||||
emit1((int)$2);
|
||||
}
|
||||
else {
|
||||
emit1((int)$2&0xff);
|
||||
emit1((int)$2>>8);
|
||||
}
|
||||
operands(op_ind);
|
||||
}
|
||||
| OP1_Bx expr { branch($1, $2); }
|
||||
| OP1_Be expr { op_ind = 0; ext_branch($1, $2); }
|
||||
| OP2_l_Be { op_ind = 0; opnd[0].size = 4; }
|
||||
opnd ',' expr
|
||||
{ ext_branch($1, $5); }
|
||||
| OP3_l_V_Be { op_ind = 0; opnd[0].size = 4;
|
||||
opnd[1].size = -1;
|
||||
}
|
||||
opnd ',' opnd ',' expr
|
||||
{ ext_branch($1, $7); }
|
||||
;
|
||||
|
||||
OP1_O
|
||||
: OP1_b { opnd[0].size = 1; $$ = $1; }
|
||||
| OP1_w { opnd[0].size = 2; $$ = $1; }
|
||||
| OP1_l { opnd[0].size = 4; $$ = $1; }
|
||||
| OP1_u
|
||||
;
|
||||
|
||||
OP1_B
|
||||
: OP1_Bb { opnd[0].size = 1; $$ = $1; }
|
||||
| OP1_Bw { opnd[0].size = 2; $$ = $1; }
|
||||
| OP1_Bl { opnd[0].size = 4; $$ = $1; }
|
||||
;
|
||||
|
||||
OP2_O_O
|
||||
: OP2_b_b { opnd[0].size = 1; opnd[1].size = 1; $$ = $1; }
|
||||
| OP2_b_l { opnd[0].size = 1; opnd[1].size = 4; $$ = $1; }
|
||||
| OP2_b_u { opnd[0].size = 1; opnd[1].size = 0; $$ = $1; }
|
||||
| OP2_b_w { opnd[0].size = 1; opnd[1].size = 2; $$ = $1; }
|
||||
| OP2_l_b { opnd[0].size = 4; opnd[1].size = 1; $$ = $1; }
|
||||
| OP2_l_l { opnd[0].size = 4; opnd[1].size = 4; $$ = $1; }
|
||||
| OP2_l_u { opnd[0].size = 4; opnd[1].size = 0; $$ = $1; }
|
||||
| OP2_l_w { opnd[0].size = 4; opnd[1].size = 2; $$ = $1; }
|
||||
| OP2_u_b { opnd[0].size = 0; opnd[1].size = 1; $$ = $1; }
|
||||
| OP2_u_l { opnd[0].size = 0; opnd[1].size = 4; $$ = $1; }
|
||||
| OP2_u_u { opnd[0].size = 0; opnd[1].size = 0; $$ = $1; }
|
||||
| OP2_u_w { opnd[0].size = 0; opnd[1].size = 2; $$ = $1; }
|
||||
| OP2_w_b { opnd[0].size = 2; opnd[1].size = 1; $$ = $1; }
|
||||
| OP2_w_l { opnd[0].size = 2; opnd[1].size = 4; $$ = $1; }
|
||||
| OP2_w_u { opnd[0].size = 2; opnd[1].size = 0; $$ = $1; }
|
||||
| OP2_w_w { opnd[0].size = 2; opnd[1].size = 2; $$ = $1; }
|
||||
;
|
||||
|
||||
OP2_A_O
|
||||
: OP2_A_l { opnd[1].size = 4; $$ = $1; }
|
||||
;
|
||||
|
||||
OP2_O_B
|
||||
: OP2_l_Bb { opnd[0].size = 4; opnd[1].size = 1; $$ = $1; }
|
||||
;
|
||||
|
||||
OP2_O_A
|
||||
: OP2_l_A { opnd[0].size = 4; $$ = $1; }
|
||||
;
|
||||
|
||||
OP3_O_O_O
|
||||
: OP3_b_b_b { opnd[0].size = 1; opnd[1].size = 1;
|
||||
opnd[2].size = 1; $$ = $1;
|
||||
}
|
||||
| OP3_b_l_l { opnd[0].size = 1; opnd[1].size = 4;
|
||||
opnd[2].size = 4; $$ = $1;
|
||||
}
|
||||
| OP3_b_u_u { opnd[0].size = 1; opnd[1].size = 0;
|
||||
opnd[2].size = 0; $$ = $1;
|
||||
}
|
||||
| OP3_l_l_l { opnd[0].size = 4; opnd[1].size = 4;
|
||||
opnd[2].size = 4; $$ = $1;
|
||||
}
|
||||
| OP3_u_u_u { opnd[0].size = 0; opnd[1].size = 0;
|
||||
opnd[2].size = 0; $$ = $1;
|
||||
}
|
||||
| OP3_w_w_w { opnd[0].size = 2; opnd[1].size = 2;
|
||||
opnd[2].size = 2; $$ = $1;
|
||||
}
|
||||
;
|
||||
|
||||
OP3_O_O_B
|
||||
: OP3_l_l_Bb { opnd[0].size = 4; opnd[1].size = 4;
|
||||
opnd[2].size = 1; $$ = $1;
|
||||
}
|
||||
| OP3_l_V_Bb { opnd[0].size = 4; opnd[1].size = -1;
|
||||
opnd[2].size = 1; $$ = $1;
|
||||
}
|
||||
;
|
||||
|
||||
OP3_O_O_A
|
||||
: OP3_b_w_A { opnd[0].size = 1; opnd[1].size = 2; $$ = $1; }
|
||||
| OP3_l_w_A { opnd[0].size = 4; opnd[1].size = 2; $$ = $1; }
|
||||
| OP3_u_w_A { opnd[0].size = 0; opnd[1].size = 2; $$ = $1; }
|
||||
;
|
||||
|
||||
OP3_O_A_A
|
||||
: OP3_w_A_A { opnd[0].size = 2; $$ = $1; }
|
||||
;
|
||||
|
||||
OP3_O_A_O
|
||||
: OP3_w_A_l { opnd[0].size = 2; opnd[2].size = 4; $$ = $1; }
|
||||
;
|
||||
|
||||
OP4_O_O_O_O
|
||||
: OP4_l_b_V_l { opnd[0].size = 4; opnd[1].size = 1;
|
||||
opnd[2].size = -1; opnd[3].size = 4;
|
||||
$$ = $1;
|
||||
}
|
||||
| OP4_l_l_b_V { opnd[0].size = 4; opnd[1].size = 4;
|
||||
opnd[2].size = 1; opnd[3].size = -1;
|
||||
$$ = $1;
|
||||
}
|
||||
| OP4_l_l_l_u { opnd[0].size = 4; opnd[1].size = 4;
|
||||
opnd[2].size = 4; opnd[3].size = 0;
|
||||
$$ = $1;
|
||||
}
|
||||
| OP4_l_u_l_l { opnd[0].size = 4; opnd[1].size = 0;
|
||||
opnd[2].size = 4; opnd[3].size = 4;
|
||||
$$ = $1;
|
||||
}
|
||||
;
|
||||
|
||||
OP4_O_O_O_B
|
||||
: OP4_b_b_b_Bw { opnd[0].size = 1; opnd[1].size = 1;
|
||||
opnd[2].size = 1; opnd[3].size = 2;
|
||||
$$ = $1;
|
||||
}
|
||||
| OP4_l_l_l_Bw { opnd[0].size = 4; opnd[1].size = 4;
|
||||
opnd[2].size = 4; opnd[3].size = 2;
|
||||
$$ = $1;
|
||||
}
|
||||
| OP4_u_u_u_Bw { opnd[0].size = 0; opnd[1].size = 0;
|
||||
opnd[2].size = 0; opnd[3].size = 2;
|
||||
$$ = $1;
|
||||
}
|
||||
| OP4_w_w_w_Bw { opnd[0].size = 2; opnd[1].size = 2;
|
||||
opnd[2].size = 2; opnd[3].size = 2;
|
||||
$$ = $1;
|
||||
}
|
||||
;
|
||||
|
||||
OP4_O_A_O_A
|
||||
: OP4_w_A_w_A { opnd[0].size = 2; opnd[2].size = 2; $$ = $1; }
|
||||
;
|
||||
|
||||
OP4_O_A_A_O
|
||||
: OP4_w_A_A_b { opnd[0].size = 2; opnd[3].size = 1; $$ = $1; }
|
||||
;
|
||||
|
||||
OP4_O_A_A_A
|
||||
: OP4_w_A_A_A { opnd[0].size = 2; $$ = $1; }
|
||||
;
|
||||
|
||||
OP4_A_O_O_A
|
||||
: OP4_A_l_w_A { opnd[1].size = 4; opnd[2].size = 2; $$ = $1; }
|
||||
;
|
||||
|
||||
OP5_O_A_A_O_A
|
||||
: OP5_w_A_A_w_A { opnd[0].size = 2; opnd[3].size = 2; $$ = $1; }
|
||||
;
|
||||
|
||||
OP5_O_A_O_O_A
|
||||
: OP5_w_A_b_w_A { opnd[0].size = 2; opnd[3].size = 2;
|
||||
opnd[2].size = 1; $$ = $1;
|
||||
}
|
||||
;
|
||||
|
||||
OP5_O_O_O_O_O
|
||||
: OP5_u_b_u_l_u { opnd[0].size = 0; opnd[1].size = 1;
|
||||
opnd[2].size = 0; opnd[3].size = 4;
|
||||
opnd[4].size = 0; $$ = $1;
|
||||
}
|
||||
| OP5_u_w_u_l_u { opnd[0].size = 0; opnd[1].size = 2;
|
||||
opnd[2].size = 0; opnd[3].size = 4;
|
||||
opnd[4].size = 0; $$ = $1;
|
||||
}
|
||||
;
|
||||
|
||||
OP6_O_O_O_O_O_O
|
||||
: OP6_l_l_l_l_l_l { opnd[0].size = 4; opnd[1].size = 4;
|
||||
opnd[2].size = 4; opnd[3].size = 4;
|
||||
opnd[4].size = 4; opnd[5].size = 4;
|
||||
$$ = $1;
|
||||
}
|
||||
;
|
||||
|
||||
OP6_O_A_O_A_O_A
|
||||
: OP6_w_A_b_A_w_A { opnd[0].size = 2; opnd[2].size = 1;
|
||||
opnd[4].size = 2; $$ = $1;
|
||||
}
|
||||
| OP6_w_A_w_A_w_A { opnd[0].size = 2; opnd[2].size = 2;
|
||||
opnd[4].size = 2; $$ = $1;
|
||||
}
|
||||
;
|
||||
|
||||
OP6_O_O_A_O_O_A
|
||||
: OP6_b_w_A_b_w_A { opnd[0].size = 1; opnd[1].size = 2;
|
||||
opnd[3].size = 1; opnd[4].size = 2;
|
||||
$$ = $1;
|
||||
}
|
||||
;
|
||||
|
||||
CASE_O_O_O
|
||||
: CASE_b_b_b { opnd[0].size = 1; opnd[1].size = 1;
|
||||
opnd[2].size = 1; $$ = $1;
|
||||
}
|
||||
| CASE_w_w_w { opnd[0].size = 2; opnd[1].size = 2;
|
||||
opnd[2].size = 2; $$ = $1;
|
||||
}
|
||||
| CASE_l_l_l { opnd[0].size = 4; opnd[1].size = 4;
|
||||
opnd[2].size = 4; $$ = $1;
|
||||
}
|
||||
;
|
||||
|
||||
oper
|
||||
: OP0
|
||||
| OP1_O opnd { $$ = $1; }
|
||||
| OP1_A ea { $$ = $1; }
|
||||
| OP1_B expr { $$ = $1;
|
||||
opnd[0].exp = $2;
|
||||
RELOMOVE(opnd[0].relo, relonami);
|
||||
opnd[0].mode = DISPL;
|
||||
op_ind = 1;
|
||||
}
|
||||
| OP2_O_O opnd ',' opnd
|
||||
{ $$ = $1; }
|
||||
| OP2_A_O ea ',' opnd
|
||||
{ $$ = $1; }
|
||||
| OP2_O_B opnd ',' expr
|
||||
{ $$ = $1;
|
||||
opnd[op_ind].exp = $4;
|
||||
RELOMOVE(opnd[op_ind].relo, relonami);
|
||||
opnd[op_ind].mode = DISPL;
|
||||
op_ind++;
|
||||
}
|
||||
| OP2_A_A ea ',' ea
|
||||
{ $$ = $1; }
|
||||
| OP2_O_A opnd ',' ea
|
||||
{ $$ = $1; }
|
||||
| OP3_O_O_O opnd ',' opnd ',' opnd
|
||||
{ $$ = $1; }
|
||||
| OP3_O_O_B opnd ',' opnd ',' expr
|
||||
{ $$ = $1;
|
||||
opnd[op_ind].exp = $6;
|
||||
RELOMOVE(opnd[op_ind].relo, relonami);
|
||||
opnd[op_ind].mode = DISPL;
|
||||
op_ind++;
|
||||
}
|
||||
| OP3_O_O_A opnd ',' opnd ',' ea
|
||||
{ $$ = $1; }
|
||||
| OP3_O_A_A opnd ',' ea ',' ea
|
||||
{ $$ = $1; }
|
||||
| OP3_O_A_O opnd ',' ea ',' opnd
|
||||
{ $$ = $1; }
|
||||
| OP4_O_O_O_O opnd ',' opnd ',' opnd ',' opnd
|
||||
{ $$ = $1; }
|
||||
| OP4_O_O_O_B opnd ',' opnd ',' opnd ',' expr
|
||||
{ $$ = $1;
|
||||
opnd[op_ind].exp = $8;
|
||||
RELOMOVE(opnd[op_ind].relo, relonami);
|
||||
opnd[op_ind].mode = DISPL;
|
||||
op_ind++;
|
||||
}
|
||||
| OP4_O_A_O_A opnd ',' ea ',' opnd ',' ea
|
||||
{ $$ = $1; }
|
||||
| OP4_O_A_A_O opnd ',' ea ',' ea ',' opnd
|
||||
{ $$ = $1; }
|
||||
| OP4_A_O_O_A ea ',' opnd ',' opnd ',' ea
|
||||
{ $$ = $1; }
|
||||
| OP4_O_A_A_A opnd ',' ea ',' ea ',' ea
|
||||
{ $$ = $1; }
|
||||
| OP5_O_A_A_O_A opnd ',' ea ',' ea ',' opnd ',' ea
|
||||
{ $$ = $1; }
|
||||
| OP5_O_A_O_O_A opnd ',' ea ',' opnd ',' opnd ',' ea
|
||||
{ $$ = $1; }
|
||||
| OP5_O_O_O_O_O opnd ',' opnd ',' opnd ',' opnd ',' opnd
|
||||
{ $$ = $1; }
|
||||
| OP6_O_O_O_O_O_O opnd ',' opnd ',' opnd ',' opnd ',' opnd ',' opnd
|
||||
{ $$ = $1; }
|
||||
| OP6_O_A_O_A_O_A opnd ',' ea ',' opnd ',' ea ',' opnd ',' ea
|
||||
{ $$ = $1; }
|
||||
| OP6_O_O_A_O_O_A opnd ',' opnd ',' ea ',' opnd ',' opnd ',' ea
|
||||
{ $$ = $1; }
|
||||
| CASE_O_O_O opnd ',' opnd ',' opnd
|
||||
{ $$ = $1; }
|
||||
;
|
||||
|
||||
opnd
|
||||
: ea
|
||||
| immediate
|
||||
| REG { opnd[op_ind].mode = REG_MODE;
|
||||
opnd[op_ind].reg = $1;
|
||||
opnd[op_ind].index_reg = -1;
|
||||
op_ind++;
|
||||
}
|
||||
;
|
||||
|
||||
ea
|
||||
: eax { opnd[op_ind].index_reg = -1;
|
||||
op_ind++;
|
||||
}
|
||||
| eax '[' REG ']' { opnd[op_ind].index_reg = $3;
|
||||
op_ind++;
|
||||
}
|
||||
| immediate '[' REG ']'
|
||||
{ opnd[op_ind-1].index_reg = $3;
|
||||
}
|
||||
;
|
||||
eax
|
||||
: expr { opnd[op_ind].exp = $1;
|
||||
opnd[op_ind].mode = ABS;
|
||||
RELOMOVE(opnd[op_ind].relo, relonami);
|
||||
}
|
||||
| '*' expr { opnd[op_ind].exp = $2;
|
||||
opnd[op_ind].mode = ABS_DEF;
|
||||
RELOMOVE(opnd[op_ind].relo, relonami);
|
||||
}
|
||||
| '(' REG ')' { opnd[op_ind].mode = REGDEF_MODE;
|
||||
opnd[op_ind].reg = $2;
|
||||
}
|
||||
| '(' REG ')' '+' { opnd[op_ind].mode = AI_MODE;
|
||||
opnd[op_ind].reg = $2;
|
||||
}
|
||||
| '*' '(' REG ')' '+'
|
||||
{ opnd[op_ind].mode = AI_DEF_MODE;
|
||||
opnd[op_ind].reg = $3;
|
||||
}
|
||||
| '-' '(' REG ')' { opnd[op_ind].mode = AD_MODE;
|
||||
opnd[op_ind].reg = $3;
|
||||
}
|
||||
| expr '(' REG ')'
|
||||
{ opnd[op_ind].exp = $1;
|
||||
opnd[op_ind].mode = DISPLL_MODE;
|
||||
opnd[op_ind].reg = $3;
|
||||
RELOMOVE(opnd[op_ind].relo, relonami);
|
||||
}
|
||||
| '*' expr '(' REG ')'
|
||||
{ opnd[op_ind].exp = $2;
|
||||
opnd[op_ind].mode = DISPLL_DEF_MODE;
|
||||
opnd[op_ind].reg = $4;
|
||||
RELOMOVE(opnd[op_ind].relo, relonami);
|
||||
}
|
||||
;
|
||||
|
||||
immediate
|
||||
: '$' expr { opnd[op_ind].mode = IMM;
|
||||
opnd[op_ind].exp = $2;
|
||||
opnd[op_ind].index_reg = -1;
|
||||
RELOMOVE(opnd[op_ind].relo, relonami);
|
||||
op_ind++;
|
||||
}
|
||||
;
|
||||
286
mach/vax4/as/mach5.c
Normal file
286
mach/vax4/as/mach5.c
Normal file
|
|
@ -0,0 +1,286 @@
|
|||
/*
|
||||
* (c) copyright 1990 by the Vrije Universiteit, Amsterdam, The Netherlands.
|
||||
* See the copyright notice in the ACK home directory, in the file "Copyright".
|
||||
*/
|
||||
#define RCSID5 "$Header$"
|
||||
|
||||
/*
|
||||
* VAX-11 Machine dependent C declarations
|
||||
*/
|
||||
|
||||
static
|
||||
oprnd(p)
|
||||
register struct operand *p;
|
||||
{
|
||||
/* Process one operand */
|
||||
|
||||
int sm;
|
||||
|
||||
if (p->index_reg >= 0 && p->mode != DISPL) {
|
||||
/* indexed mode; emit */
|
||||
emit1((INDEX_MODE << 4) | p->index_reg);
|
||||
}
|
||||
|
||||
switch(p->mode) {
|
||||
case REG_MODE:
|
||||
emit1((REG_MODE << 4) | p->reg);
|
||||
break;
|
||||
case REGDEF_MODE:
|
||||
emit1((REGDEF_MODE << 4) | p->reg);
|
||||
break;
|
||||
case AI_MODE:
|
||||
emit1((AI_MODE << 4) | p->reg);
|
||||
break;
|
||||
case AI_DEF_MODE:
|
||||
emit1((AI_DEF_MODE << 4) | p->reg);
|
||||
break;
|
||||
case AD_MODE:
|
||||
emit1((AD_MODE << 4) | p->reg);
|
||||
break;
|
||||
case DISPLL_MODE:
|
||||
case DISPLL_DEF_MODE:
|
||||
if (small(p->exp.typ == S_ABS && fitw(p->exp.val), 2)) {
|
||||
if (small(fitb(p->exp.val), 1)) {
|
||||
/* DISPLB_MODE or DISPLB_DEF_MODE */
|
||||
emit1(((p->mode-4)<<4) | p->reg);
|
||||
emit1((int)(p->exp.val));
|
||||
}
|
||||
else {
|
||||
/* DISPLW_MODE or DISPLW_DEF_MODE */
|
||||
emit1(((p->mode-2)<<4) | p->reg);
|
||||
emit2((int)(p->exp.val));
|
||||
}
|
||||
}
|
||||
else {
|
||||
small(0, 1); /* dummy call */
|
||||
emit1((p->mode<<4) | p->reg);
|
||||
#ifdef RELOCATION
|
||||
RELOMOVE(relonami, p->relo);
|
||||
newrelo(p->exp.typ, RELO4);
|
||||
#endif
|
||||
emit4((long) p->exp.val);
|
||||
}
|
||||
break;
|
||||
case DISPL:
|
||||
/* a displacement */
|
||||
p->exp.val -= (DOTVAL + p->size);
|
||||
if ((pass == PASS_2) &&
|
||||
(p->exp.val > 0) &&
|
||||
((p->exp.typ & S_DOT) == 0)
|
||||
) {
|
||||
p->exp.val -= DOTGAIN;
|
||||
}
|
||||
if (p->size == 1) sm = fitb(p->exp.val);
|
||||
else if (p->size == 2) sm = fitw(p->exp.val);
|
||||
else sm = 1;
|
||||
if (pass >= PASS_2 &&
|
||||
((p->exp.typ & ~S_DOT) != DOTTYP || !sm)) {
|
||||
serror("label too far");
|
||||
}
|
||||
if (p->size == 1) emit1((int)(p->exp.val));
|
||||
else if (p->size == 2) emit2((int)(p->exp.val));
|
||||
else emit4(p->exp.val);
|
||||
break;
|
||||
case IMM:
|
||||
if (p->size < 0) {
|
||||
serror("immediate mode not allowed here");
|
||||
p->size = 4;
|
||||
}
|
||||
else if (p->size == 0) {
|
||||
serror("this immediate mode is not implemented");
|
||||
p->size = 4;
|
||||
}
|
||||
if (small(p->exp.typ == S_ABS && literal(p->exp.val), p->size)){
|
||||
emit1((int)(p->exp.val));
|
||||
}
|
||||
else {
|
||||
emit1((AI_MODE << 4) | PC);
|
||||
RELOMOVE(relonami, p->relo);
|
||||
switch(p->size) {
|
||||
case 1:
|
||||
#ifdef RELOCATION
|
||||
newrelo(p->exp.typ, RELO1);
|
||||
#endif
|
||||
emit1((int)(p->exp.val));
|
||||
break;
|
||||
case 2:
|
||||
#ifdef RELOCATION
|
||||
newrelo(p->exp.typ, RELO2);
|
||||
#endif
|
||||
emit2((int)(p->exp.val));
|
||||
break;
|
||||
case 4:
|
||||
#ifdef RELOCATION
|
||||
newrelo(p->exp.typ, RELO4);
|
||||
#endif
|
||||
emit4(p->exp.val);
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
}
|
||||
}
|
||||
break;
|
||||
case ABS:
|
||||
case ABS_DEF:
|
||||
if (p->mode == ABS) p->mode = DISPLL_MODE;
|
||||
else p->mode = DISPLL_DEF_MODE;
|
||||
p->reg = PC;
|
||||
p->exp.val -= (DOTVAL + 2);
|
||||
if ((pass == PASS_2)
|
||||
&&
|
||||
(p->exp.val > 0)
|
||||
&&
|
||||
((p->exp.typ & S_DOT) == 0)
|
||||
) {
|
||||
p->exp.val -= DOTGAIN;
|
||||
}
|
||||
sm = fitw(p->exp.val - 1);
|
||||
if ((p->exp.typ & ~S_DOT) != DOTTYP) sm = 0;
|
||||
if (small(sm, 2)) {
|
||||
if (small(fitb(p->exp.val), 1)) {
|
||||
/* DISPLB_MODE or DISPLB_DEF_MODE */
|
||||
emit1(((p->mode-4)<<4) | p->reg);
|
||||
emit1((int)(p->exp.val));
|
||||
}
|
||||
else {
|
||||
/* DISPLW_MODE or DISPLW_DEF_MODE */
|
||||
emit1(((p->mode-2)<<4) | p->reg);
|
||||
emit2((int)(p->exp.val - 1));
|
||||
}
|
||||
}
|
||||
else {
|
||||
small(0, 1); /* dummy call */
|
||||
emit1((p->mode<<4) | p->reg);
|
||||
#ifdef RELOCATION
|
||||
RELOMOVE(relonami, p->relo);
|
||||
newrelo(p->exp.typ, RELO4|RELPC);
|
||||
#endif
|
||||
emit4((long) p->exp.val - 3);
|
||||
}
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
size_ops()
|
||||
{
|
||||
/* Give an upper bound on the size of the operands
|
||||
*/
|
||||
register struct operand *p = &opnd[0];
|
||||
register int i;
|
||||
register int sz = 0;
|
||||
|
||||
for (i = 0; i < op_ind; i++) {
|
||||
if (p->index_reg >= 0 && p->mode != DISPL) {
|
||||
sz++;
|
||||
}
|
||||
switch(p->mode) {
|
||||
case REG_MODE:
|
||||
case REGDEF_MODE:
|
||||
case AI_MODE:
|
||||
case AI_DEF_MODE:
|
||||
case AD_MODE:
|
||||
sz++;
|
||||
break;
|
||||
case DISPLL_MODE:
|
||||
case DISPLL_DEF_MODE:
|
||||
case ABS:
|
||||
case ABS_DEF:
|
||||
case IMM:
|
||||
sz += 5;
|
||||
break;
|
||||
case DISPL:
|
||||
sz += p->size;
|
||||
break;
|
||||
default:
|
||||
assert(0);
|
||||
}
|
||||
p++;
|
||||
}
|
||||
return sz;
|
||||
}
|
||||
|
||||
branch(opc, exp)
|
||||
expr_t exp;
|
||||
{
|
||||
exp.val -= (DOTVAL + 2);
|
||||
if ((pass == PASS_2) &&
|
||||
(exp.val > 0) &&
|
||||
((exp.typ & S_DOT) == 0)
|
||||
) {
|
||||
exp.val -= DOTGAIN;
|
||||
}
|
||||
if (pass >= PASS_2 &&
|
||||
((exp.typ & ~S_DOT) != DOTTYP || ! fitw(exp.val))) {
|
||||
serror("label too far");
|
||||
}
|
||||
if (small(fitb(exp.val) && ((exp.typ & ~S_DOT) == DOTTYP), 1)) {
|
||||
emit1(opc);
|
||||
emit1((int) exp.val);
|
||||
}
|
||||
else {
|
||||
emit1(opc|0x20);
|
||||
emit2((int) exp.val);
|
||||
}
|
||||
}
|
||||
|
||||
ext_branch(opc, exp)
|
||||
expr_t exp;
|
||||
{
|
||||
int sm;
|
||||
int gain = opc == 0x11 ? 1 : 3;
|
||||
valu_t val, d2 = DOTVAL + 2;
|
||||
|
||||
exp.val -= d2;
|
||||
if ((pass == PASS_2) &&
|
||||
(exp.val > 0) &&
|
||||
((exp.typ & S_DOT) == 0)
|
||||
) {
|
||||
exp.val -= DOTGAIN;
|
||||
}
|
||||
if (exp.val < 0) val = exp.val - size_ops();
|
||||
else val = exp.val;
|
||||
sm = fitw(val);
|
||||
if ((exp.typ & ~S_DOT) != DOTTYP) sm = 0;
|
||||
if (small(sm, 3)) {
|
||||
if (small(fitb(val), gain)) {
|
||||
emit1(opc);
|
||||
operands(op_ind);
|
||||
emit1((int) (exp.val - (DOTVAL + 1 - d2)));
|
||||
}
|
||||
else {
|
||||
if (opc != 0x11) {
|
||||
emit1(opc^1);
|
||||
operands(op_ind);
|
||||
emit1(3);
|
||||
}
|
||||
emit1(0x31);
|
||||
emit2((int) (exp.val - (DOTVAL + 2 - d2)));
|
||||
}
|
||||
}
|
||||
else {
|
||||
small(0, gain); /* dummy call */
|
||||
if (opc != 0x11) {
|
||||
emit1(opc ^ 1);
|
||||
operands(op_ind);
|
||||
emit1(6);
|
||||
}
|
||||
emit1(0x17); /* jmp */
|
||||
emit1((DISPLL_MODE << 4) | PC);
|
||||
#ifdef RELOCATION
|
||||
newrelo(exp.typ, RELO4|RELPC);
|
||||
#endif
|
||||
emit4(exp.val - (DOTVAL + 4 - d2));
|
||||
}
|
||||
}
|
||||
|
||||
operands(cnt)
|
||||
{
|
||||
register int i;
|
||||
|
||||
for (i = 0; i < cnt; i++) {
|
||||
oprnd(&opnd[i]);
|
||||
}
|
||||
}
|
||||
Loading…
Reference in a new issue