Changed to be printed on laserprinter.
Removed paragraph about bug, since bug is now solved
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doc/ncg.doc
347
doc/ncg.doc
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@ -57,7 +57,7 @@ and the assembly code of the machine at hand.
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.NH 1
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What has changed since version 1 ?
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.PP
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This chapter can be skipped by anyone not familiar with the first version.
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This section can be skipped by anyone not familiar with the first version.
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It is not needed to understand the current version.
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.PP
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This paper describes the second version of the code generator system.
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@ -116,39 +116,40 @@ Alternatively one can think of the real stack as an infinite extension
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at the bottom of the fake stack.
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Both ways, the concatenation of the real stack and the fake stack
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will be the stack as it would have been on a real EM machine (see figure).
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.KF
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.DS L
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.ta 8 16 24 32 40 48 56 64 72
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EM machine target machine
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| | | |
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| | | |
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| | | |
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| | | |
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| | | real stack |
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| | | | |
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| | | | | growing
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| EM stack | | | |
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| | |_______________| \e|/
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| | | |
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| | | |
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| | | |
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| | | fake stack |
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| | | |
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|_______________| |_______________|
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.TS
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center;
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cw(3.5c) cw(3c) cw(3.5c)
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cw(3.5c) cw(3c) cw(3.5c)
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|cw(3.5c)| cw(3c) |cw(3.5c)| .
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EM machine target machine
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.I
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Relation between EM stack, real stack and fake stack.
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.R
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.DE
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.KE
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real stack
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stack
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grows
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EM stack \s+2\(br\s0
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\s+2\(br\s0
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\s+2\(br\s0 _
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\s+2\(br\s0
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\s+2\(da\s0
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fake stack
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_ _
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.T&
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ci s s.
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Relation between EM stack, real stack and fake stack.
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.TE
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During code generation tokens will be kept on the fake stack as long
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as possible but when they are moved to the real stack,
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by generating code for the push,
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all tokens above\u*\d
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all tokens above\v'-.25m'\(dg\v'.25m'
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.FS
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* in this document the stack is assumed to grow downwards,
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\(dg in this document the stack is assumed to grow downwards,
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although the top of the stack will mean the first element that will
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be popped.
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.FE
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@ -297,8 +298,9 @@ at will to improve legibility.
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Identifiers used in the table have the same syntax as C identifiers,
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upper and lower case considered different, all characters significant.
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Here is a list of reserved words; all of these are unavailable as identifiers.
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.DS L
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.ta 14 28 42 56
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.TS
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box;
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l l l l l.
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ADDR STACK from reg_any test
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COERCIONS STACKINGRULES gen reg_float to
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INSTRUCTIONS TESTS highw reg_loop ufit
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@ -309,7 +311,7 @@ PROPERTIES cost loww reusing
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REGISTERS defined move rom
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SETS exact pat samesign
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SIZEFACTOR example proc sfit
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.DE
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.TE
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C style comments are accepted.
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.DS
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/* this is a comment */
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@ -330,7 +332,7 @@ NAME=value
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.DE
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value being an integer or string.
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Three constants must be defined here:
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.IP EM_WSIZE 10
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.IP EM_WSIZE 14
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Number of bytes in a machine word.
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This is the number of bytes
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a \fBloc\fP instruction will put on the stack.
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@ -368,13 +370,13 @@ FORMAT= "0%o"
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to satisfy the old UNIX assembler that reads octal unless followed by
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a period, and the ACK assembler that follows C conventions.
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.PP
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Tables under control of programs like
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Tables under control of source code control systems like
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.I sccs
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or
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.I rcs
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can put their id-string here, for example
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.DS
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rcsid="$Header$"
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rcsid="$\&Header$"
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.DE
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These strings, like all strings in the table, will eventually
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end up in the binary code generator produced.
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@ -385,6 +387,7 @@ same order of magnitude.
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This can be done as
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.DS
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SIZEFACTOR = C\d3\u/C\d4\u
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.sp
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TIMEFACTOR = C\d1\u/C\d2\u
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.DE
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Above numbers must be read as rational numbers.
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@ -403,32 +406,28 @@ It consists of a list of user-defined
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identifiers optionally followed by the size
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of the property in parentheses, default EM_WSIZE.
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Example for the PDP-11:
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.DS
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.ta 8 16 24 32 40
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PROPERTIES /* The header word for this section */
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.TS
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l l.
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PROPERTIES /* The header word for this section */
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GENREG /* All PDP registers */
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REG /* Normal registers (allocatable) */
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ODDREG /* All odd registers (allocatable) */
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REGPAIR(4) /* Register pairs for division */
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FLTREG(4) /* Floating point registers */
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DBLREG(8) /* Same, double precision */
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GENFREG(4) /* generic floating point */
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GENDREG(8) /* Same, double precision */
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FLTREGPAIR(8) /* register pair for modf */
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DBLREGPAIR(16) /* Same, double precision */
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LOCALBASE /* Guess what */
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GENREG /* All PDP registers */
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REG /* Normal registers (allocatable) */
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ODDREG /* All odd registers (allocatable) */
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REGPAIR(4) /* Register pairs for division */
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FLTREG(4) /* Floating point registers */
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DBLREG(8) /* Same, double precision */
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GENFREG(4) /* generic floating point */
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GENDREG(8) /* Same, double precision */
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FLTREGPAIR(8) /* register pair for modf */
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DBLREGPAIR(16) /* Same, double precision */
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LOCALBASE /* Guess what */
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STACKPOINTER
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PROGRAMCOUNTER
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.DE
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.TE
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Registers are allocated by asking for a property,
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so if for some reason in later parts of the table
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one particular register must be allocated it
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has to have a unique property.
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.PP
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There is a bug in the codegenerator that can be circumvented by
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providing a dummy property at the start of the property list.
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The example has not been updated to show this.
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.NH 2
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Register definition
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.PP
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@ -442,22 +441,22 @@ Syntax:
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<register> : ident [ '(' string ')' ] [ '=' ident [ '+' ident ] ]
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.DE
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Example for the PDP-11:
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.DS L
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.ta 8 16 24 32 40 48 56 64
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.TS
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l l.
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REGISTERS
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r0,r2,r4 : GENREG,REG.
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r1,r3 : GENREG,REG,ODDREG.
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r01("r0")=r0+r1 : REGPAIR.
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fr0("r0"),fr1("r1"),fr2("r2"),fr3("r3") : GENFREG,FLTREG.
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r0,r2,r4 : GENREG,REG.
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r1,r3 : GENREG,REG,ODDREG.
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r01("r0")=r0+r1 : REGPAIR.
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fr0("r0"),fr1("r1"),fr2("r2"),fr3("r3") : GENFREG,FLTREG.
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dr0("r0")=fr0,dr1("r1")=fr1,
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dr2("r2")=fr2,dr3("r3")=fr3 : GENDREG,DBLREG.
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dr2("r2")=fr2,dr3("r3")=fr3 : GENDREG,DBLREG.
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fr01("r0")=fr0+fr1,fr23("r2")=fr2+fr3 : FLTREGPAIR.
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dr01("r0")=dr0+dr1,dr23("r2")=dr2+dr3 : DBLREGPAIR.
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lb("r5") : GENREG,LOCALBASE.
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sp : GENREG,STACKPOINTER.
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pc : GENREG,PROGRAMCOUNTER.
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.DE
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lb("r5") : GENREG,LOCALBASE.
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sp : GENREG,STACKPOINTER.
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pc : GENREG,PROGRAMCOUNTER.
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.TE
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.PP
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The names in the left hand lists are names of registers as used
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in the table.
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@ -529,20 +528,21 @@ Tokens should usually be declared for every addressing mode
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of the machine at hand and for every size directly usable in
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a machine instruction.
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Example for the PDP-11 (incomplete):
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.DS L
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.TS
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l l.
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TOKENS
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const2 = { INT num; } 2 cost(2,300) "$" num .
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addr_local = { INT ind; } 2 .
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addr_external = { ADDR off; } 2 "$" off.
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const2 = { INT num; } 2 cost(2,300) "$" num .
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addr_local = { INT ind; } 2 .
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addr_external = { ADDR off; } 2 "$" off.
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regdef2 = { GENREG reg; } 2 "*" reg.
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regind2 = { GENREG reg; ADDR off; } 2 off "(" reg ")" .
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reginddef2 = { GENREG reg; ADDR off; } 2 "*" off "(" reg ")" .
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regdef2 = { GENREG reg; } 2 "*" reg.
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regind2 = { GENREG reg; ADDR off; } 2 off "(" reg ")" .
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reginddef2 = { GENREG reg; ADDR off; } 2 "*" off "(" reg ")" .
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regconst2 = { GENREG reg; ADDR off; } 2 .
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relative2 = { ADDR off; } 2 off .
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reldef2 = { ADDR off; } 2 "*" off.
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.DE
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reldef2 = { ADDR off; } 2 "*" off.
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.TE
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.PP
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Types allowed in the struct are ADDR, INT and all register properties.
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The type ADDR means a string and an integer,
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@ -624,21 +624,21 @@ in the remainder of the table,
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but for clarity it is usually better not to.
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.LP
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Example for the PDP-11 (incomplete):
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.DS L
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.ta 8 16 24 32 40 48 56 64
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.TS
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l l.
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SETS
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src2 = GENREG + regdef2 + regind2 + reginddef2 + relative2 +
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reldef2 + addr_external + const2 + LOCAL + ILOCAL +
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autodec + autoinc .
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dst2 = src2 - ( const2 + addr_external ) .
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xsrc2 = src2 + ftoint .
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src1 = regdef1 + regind1 + reginddef1 + relative1 + reldef1 .
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dst1 = src1 .
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src1or2 = src1 + src2 .
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src4 = relative4 + regdef4 + DLOCAL + regind4 .
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dst4 = src4 .
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.DE
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src2 = GENREG + regdef2 + regind2 + reginddef2 + relative2 +
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\h'\w'= 'u'reldef2 + addr_external + const2 + LOCAL + ILOCAL +
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\h'\w'= 'u'autodec + autoinc .
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dst2 = src2 - ( const2 + addr_external ) .
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xsrc2 = src2 + ftoint .
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src1 = regdef1 + regind1 + reginddef1 + relative1 + reldef1 .
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dst1 = src1 .
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src1or2 = src1 + src2 .
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src4 = relative4 + regdef4 + DLOCAL + regind4 .
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dst4 = src4 .
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.TE
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Permissible in the set construction are all the usual set operators, i.e.
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.IP +
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set union
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@ -1252,7 +1252,7 @@ The author of
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.I cgg
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could not get
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.I yacc
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to be silent without it.
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to accept his syntax without it.
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Sorry about this.
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.IP 2)
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a
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@ -1370,20 +1370,19 @@ A list of examples for the PDP-11 is given here.
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Far from being complete it gives examples of most kinds
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of instructions.
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.DS
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.ta 8 16 24 32 40 48 56 64
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pat loc yields {const2, $1}
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.ta 7.5c
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pat loc yields {const2, $1}
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pat ldc yields {const2, loww($1)}
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{const2, highw($1)}
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pat ldc yields {const2, loww($1)} {const2, highw($1)}
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.DE
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These simple patterns just push one or more tokens onto the fake stack.
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.DS
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.ta 8 16 24 32 40 48 56 64
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.ta 7.5c
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pat lof
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with REG yields {regind2,%1,$1}
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with exact regconst2 yields {regind2,%1.reg,$1+%1.off}
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with exact addr_external yields {relative2,$1+%1.off}
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with exact addr_local yields {LOCAL, %1.ind + $1,2}
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with REG yields {regind2,%1,$1}
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with exact regconst2 yields {regind2,%1.reg,$1+%1.off}
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with exact addr_external yields {relative2,$1+%1.off}
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with exact addr_local yields {LOCAL, %1.ind + $1,2}
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.DE
|
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This pattern shows the possibility to do different things
|
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depending on the fake stack contents,
|
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|
|
@ -1393,13 +1392,12 @@ not preceded by
|
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that can always be taken after a coercion,
|
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if necessary.
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.DS
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.ta 8 16 24 32 40 48 56 64
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.ta 7.5c
|
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pat lxl $1>3
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uses REG={LOCAL, SL, 2},
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REG={const2,$1-1}
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uses REG={LOCAL, SL, 2}, REG={const2,$1-1}
|
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gen 1:
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move {regind2,%a, SL},%a
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sob %b,{label,1b} yields %a
|
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sob %b,{label,1b} yields %a
|
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.DE
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||||
This rule shows register allocation with initialisation,
|
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and the use of a temporary label.
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|
|
@ -1408,7 +1406,7 @@ of the static link,
|
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that is pushed by the Pascal compiler as the last argument of
|
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a function.
|
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.DS
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.ta 8 16 24 32 40 48 56 64
|
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.ta 7.5c
|
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pat stf
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with regconst2 xsrc2
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kills allexeptcon
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|
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@ -1423,7 +1421,7 @@ part in a store instruction.
|
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The set allexeptcon contains all tokens that can be the destination
|
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of an indirect store.
|
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.DS
|
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.ta 8 16 24 32 40 48 56 64
|
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.ta 7.5c
|
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pat sde
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with exact FLTREG
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kills posextern
|
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|
|
@ -1449,51 +1447,52 @@ The third rule is taken by default,
|
|||
resulting in two separate stores,
|
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nothing better exists on the PDP-11.
|
||||
.DS
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||||
.ta 8 16 24 32 40 48 56 64
|
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.ta 7.5c
|
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pat sbi $1==2
|
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with src2 REG
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gen sub %1,%2 yields %2
|
||||
gen sub %1,%2 yields %2
|
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with exact REG src2-REG
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gen sub %2,%1
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neg %1 yields %1
|
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neg %1 yields %1
|
||||
.DE
|
||||
This rule for
|
||||
.I sbi
|
||||
has a normal first part,
|
||||
and a hand optimized special case as it's second part.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
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.ta 7.5c
|
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pat mli $1==2
|
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with ODDREG src2
|
||||
gen mul %2,%1 yields %1
|
||||
gen mul %2,%1 yields %1
|
||||
with src2 ODDREG
|
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gen mul %1,%2 yields %2
|
||||
gen mul %1,%2 yields %2
|
||||
.DE
|
||||
This shows the general property for rules with commutative
|
||||
operators,
|
||||
heuristics or look ahead will have to decide which rule is the best.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
pat loc sli $1==1 && $2==2
|
||||
with REG
|
||||
gen asl %1 yields %1
|
||||
gen asl %1 yields %1
|
||||
.DE
|
||||
A simple rule involving a longer EM-pattern,
|
||||
to make use of a specialized instruction available.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
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.ta 7.5c
|
||||
pat loc loc cii $1==1 && $2==2
|
||||
with src1or2
|
||||
uses reusing %1,REG
|
||||
gen movb %1,%a yields %a
|
||||
gen movb %1,%a yields %a
|
||||
.DE
|
||||
A somewhat more complicated example of the same.
|
||||
Note the
|
||||
.I reusing
|
||||
clause.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
pat loc loc loc cii $1>=0 && $2==2 && $3==4 leaving loc $1 loc 0
|
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.ta 7.5c
|
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pat loc loc loc cii $1>=0 && $2==2 && $3==4
|
||||
leaving loc $1 loc 0
|
||||
.DE
|
||||
Shows a trivial example of EM-replacement.
|
||||
This is a rule that could be done by the
|
||||
|
|
@ -1502,40 +1501,40 @@ if word order in longs was defined in EM.
|
|||
On a `big-endian' machine the two replacement
|
||||
instructions would be the other way around.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
pat and $1==2
|
||||
with const2 REG
|
||||
gen bic {const2,~%1.num},%2 yields %2
|
||||
gen bic {const2,~%1.num},%2 yields %2
|
||||
with REG const2
|
||||
gen bic {const2,~%2.num},%1 yields %1
|
||||
gen bic {const2,~%2.num},%1 yields %1
|
||||
with REG REG
|
||||
gen com %1
|
||||
bic %1,%2 yields %2
|
||||
bic %1,%2 yields %2
|
||||
.DE
|
||||
Shows the way you have to twist the table,
|
||||
if an
|
||||
.I and -instruction
|
||||
is not available on your machine.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
pat set $1==2
|
||||
with REG
|
||||
uses REG={const2,1}
|
||||
gen ash %1,%a yields %a
|
||||
gen ash %1,%a yields %a
|
||||
.DE
|
||||
Shows the building of a word-size set.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
pat lae aar $2==2 && rom($1,3)==1 && rom($1,1)==0
|
||||
leaving adi 2
|
||||
leaving adi 2
|
||||
|
||||
pat lae aar $2==2 && rom($1,3)==1 && rom($1,1)!=0
|
||||
leaving adi 2 adp 0-rom($1,1)
|
||||
leaving adi 2 adp 0-rom($1,1)
|
||||
.DE
|
||||
Two rules showing the use of the rom pseudo function,
|
||||
and some array optimalisation.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
pat bra
|
||||
with STACK
|
||||
gen jbr {label, $1}
|
||||
|
|
@ -1544,7 +1543,7 @@ A simple jump.
|
|||
The stack pattern guarantees that everything will be stacked
|
||||
before the jump is taken.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
pat cal
|
||||
with STACK
|
||||
gen jsr pc,{label, $1}
|
||||
|
|
@ -1552,9 +1551,9 @@ gen jsr pc,{label, $1}
|
|||
A simple call.
|
||||
Same comments as previous rule.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
pat lfr $1==2 yields r0
|
||||
pat lfr $1==4 yields r1 r0
|
||||
.ta 7.5c
|
||||
pat lfr $1==2 yields r0
|
||||
pat lfr $1==4 yields r1 r0
|
||||
.DE
|
||||
Shows the return area conventions of the PDP-11 table.
|
||||
At this point a reminder:
|
||||
|
|
@ -1564,7 +1563,7 @@ instruction, and some other instructions must leave
|
|||
the function return area intact.
|
||||
See the defining document for EM for exact information.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
pat ret $1==0
|
||||
with STACK
|
||||
gen mov lb,sp
|
||||
|
|
@ -1578,7 +1577,7 @@ In a table with register variables the
|
|||
part would just contain
|
||||
.I return .
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
pat blm
|
||||
with REG REG
|
||||
uses REG={const2,$1/2}
|
||||
|
|
@ -1596,15 +1595,15 @@ It uses the marriage thesis from Hall,
|
|||
a thesis from combinatorial mathematics,
|
||||
to accomplish this.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
pat exg $1==2
|
||||
with src2 src2 yields %1 %2
|
||||
with src2 src2 yields %1 %2
|
||||
.DE
|
||||
This rule shows the exchanging of two elements on the fake stack.
|
||||
.NH 2
|
||||
Code rules using procedures
|
||||
.PP
|
||||
To start this chapter it must be admitted at once that the
|
||||
To start this section it must be admitted at once that the
|
||||
word procedure is chosen here mainly for it's advertising
|
||||
value.
|
||||
It more resembles a glorified goto but this of course can
|
||||
|
|
@ -1664,12 +1663,12 @@ The string `*' can be used as an equivalent for `[1]'.
|
|||
Just in case this is not clear, here is an example for
|
||||
a procedure to increment/decrement a register.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
incop REG:rw:cc . /* in the INSTRUCTIONS part of course */
|
||||
|
||||
proc incdec
|
||||
with REG
|
||||
gen incop* %1 yields %1
|
||||
gen incop* %1 yields %1
|
||||
.DE
|
||||
The procedure is called with parameter "inc" or "dec".
|
||||
.PP
|
||||
|
|
@ -1680,18 +1679,18 @@ call <identifier> '(' string [ ',' string ] ')'
|
|||
.DE
|
||||
which leads to the following large example:
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
proc bxx example beq
|
||||
with src2 src2 STACK
|
||||
gen cmp %2,%1
|
||||
jxx* {label, $1}
|
||||
|
||||
pat blt call bxx("jlt")
|
||||
pat ble call bxx("jle")
|
||||
pat beq call bxx("jeq")
|
||||
pat bne call bxx("jne")
|
||||
pat bgt call bxx("jgt")
|
||||
pat bge call bxx("jge")
|
||||
pat blt call bxx("jlt")
|
||||
pat ble call bxx("jle")
|
||||
pat beq call bxx("jeq")
|
||||
pat bne call bxx("jne")
|
||||
pat bgt call bxx("jgt")
|
||||
pat bge call bxx("jge")
|
||||
.DE
|
||||
.NH 2
|
||||
Move definitions
|
||||
|
|
@ -1856,38 +1855,38 @@ The next part of the table defines the coercions that are possible
|
|||
on the defined tokens.
|
||||
Example for the PDP-11:
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
COERCIONS
|
||||
|
||||
from STACK
|
||||
uses REG
|
||||
gen mov {autoinc,sp},%a yields %a
|
||||
gen mov {autoinc,sp},%a yields %a
|
||||
|
||||
from STACK
|
||||
uses DBLREG
|
||||
gen movf {autoinc,sp},%a yields %a
|
||||
gen movf {autoinc,sp},%a yields %a
|
||||
|
||||
from STACK
|
||||
uses REGPAIR
|
||||
gen mov {autoinc,sp},%a.1
|
||||
mov {autoinc,sp},%a.2 yields %a
|
||||
mov {autoinc,sp},%a.2 yields %a
|
||||
.DE
|
||||
These three coercions just deliver a certain type
|
||||
of register by popping it from the real stack.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
from LOCAL yields {regind2,lb,%1.ind}
|
||||
.ta 7.5c
|
||||
from LOCAL yields {regind2,lb,%1.ind}
|
||||
|
||||
from DLOCAL yields {regind4,lb,%1.ind}
|
||||
from DLOCAL yields {regind4,lb,%1.ind}
|
||||
|
||||
from REG yields {regconst2, %1, 0}
|
||||
from REG yields {regconst2, %1, 0}
|
||||
.DE
|
||||
These three are zero-cost rewriting rules.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
from regconst2 %1.off==1
|
||||
uses reusing %1,REG=%1.reg
|
||||
gen inc %a yields %a
|
||||
gen inc %a yields %a
|
||||
|
||||
from regconst2
|
||||
uses reusing %1,REG=%1.reg
|
||||
|
|
@ -1896,7 +1895,7 @@ gen add {addr_external, %1.off},%a yields %a
|
|||
from addr_local
|
||||
uses REG
|
||||
gen mov lb,%a
|
||||
add {const2, %1.ind},%a yields %a
|
||||
add {const2, %1.ind},%a yields %a
|
||||
.DE
|
||||
The last three are three different cases of the coercion
|
||||
register+constant to register.
|
||||
|
|
@ -1904,19 +1903,19 @@ Only in the last case is it always necessary to allocate
|
|||
an extra register,
|
||||
since arithmetic on the localbase is unthinkable.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
from xsrc2
|
||||
uses reusing %1, REG=%1 yields %a
|
||||
uses reusing %1, REG=%1 yields %a
|
||||
|
||||
from longf4
|
||||
uses FLTREG=%1 yields %a
|
||||
uses FLTREG=%1 yields %a
|
||||
|
||||
from double8
|
||||
uses DBLREG=%1 yields %a
|
||||
uses DBLREG=%1 yields %a
|
||||
|
||||
from src1
|
||||
uses REG={const2,0}
|
||||
gen bisb %1,%a yields %a
|
||||
gen bisb %1,%a yields %a
|
||||
.DE
|
||||
These examples show the coercion of different
|
||||
tokens to a register of the needed type.
|
||||
|
|
@ -1925,14 +1924,14 @@ ensure bytes are not sign-extended.
|
|||
In EM it is defined that the result of a \fBloi\fP\ 1
|
||||
instruction is an integer in the range 0..255.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
from REGPAIR yields %1.2 %1.1
|
||||
.ta 7.5c
|
||||
from REGPAIR yields %1.2 %1.1
|
||||
|
||||
from regind4 yields {regind2,%1.reg,2+%1.off}
|
||||
{regind2,%1.reg,%1.off}
|
||||
from regind4 yields {regind2,%1.reg,2+%1.off}
|
||||
{regind2,%1.reg,%1.off}
|
||||
|
||||
from relative4 yields {relative2,2+%1.off}
|
||||
{relative2,%1.off}
|
||||
from relative4 yields {relative2,2+%1.off}
|
||||
{relative2,%1.off}
|
||||
.DE
|
||||
The last examples are splitting rules.
|
||||
.PP
|
||||
|
|
@ -2086,23 +2085,23 @@ If omitted no initialization is assumed.
|
|||
.NH 3
|
||||
Example mach.h for the PDP-11
|
||||
.DS L
|
||||
.ta 8 16 24 32 40 48 56
|
||||
.ta 4c
|
||||
#define ex_ap(y) fprintf(codefile,"\et.globl %s\en",y)
|
||||
#define in_ap(y) /* nothing */
|
||||
|
||||
#define newplb(x) fprintf(codefile,"%s:\en",x)
|
||||
#define newilb(x) fprintf(codefile,"%s:\en",x)
|
||||
#define newdlb(x) fprintf(codefile,"%s:\en",x)
|
||||
#define dlbdlb(x,y) fprintf(codefile,"%s=%s\en",x,y)
|
||||
#define dlbdlb(x,y) fprintf(codefile,"%s=%s\en",x,y)
|
||||
#define newlbss(l,x) fprintf(codefile,"%s:.=.+%d.\en",l,x);
|
||||
|
||||
#define cst_fmt "$%d."
|
||||
#define off_fmt "%d."
|
||||
#define ilb_fmt "I%02x%x"
|
||||
#define dlb_fmt "_%d"
|
||||
#define hol_fmt "hol%d"
|
||||
#define cst_fmt "$%d."
|
||||
#define off_fmt "%d."
|
||||
#define ilb_fmt "I%02x%x"
|
||||
#define dlb_fmt "_%d"
|
||||
#define hol_fmt "hol%d"
|
||||
|
||||
#define hol_off "%d.+hol%d"
|
||||
#define hol_off "%d.+hol%d"
|
||||
|
||||
#define con_cst(x) fprintf(codefile,"%d.\en",x)
|
||||
#define con_ilb(x) fprintf(codefile,"%s\en",x)
|
||||
|
|
@ -2157,7 +2156,7 @@ mes(w_mesno)
|
|||
This function is called when a
|
||||
.B mes
|
||||
pseudo is seen that is not handled by the machine independent part.
|
||||
Example below shows all you probably have to know about that.
|
||||
The example below shows all you probably have to know about that.
|
||||
.IP -
|
||||
segname[]
|
||||
.br
|
||||
|
|
@ -2216,7 +2215,7 @@ Example mach.c for the PDP-11
|
|||
As an example of the sort of code expected,
|
||||
the mach.c for the PDP-11 is presented here.
|
||||
.DS L
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 0.5i 1i 1.5i 2i 2.5i 3i 3.5i 4i 4.5i
|
||||
/*
|
||||
* machine dependent back end routines for the PDP-11
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in a new issue