Changed to be printed on laserprinter.
Removed paragraph about bug, since bug is now solved
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doc/ncg.doc
173
doc/ncg.doc
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@ -57,7 +57,7 @@ and the assembly code of the machine at hand.
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.NH 1
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What has changed since version 1 ?
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.PP
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This chapter can be skipped by anyone not familiar with the first version.
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This section can be skipped by anyone not familiar with the first version.
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It is not needed to understand the current version.
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.PP
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This paper describes the second version of the code generator system.
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@ -116,39 +116,40 @@ Alternatively one can think of the real stack as an infinite extension
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at the bottom of the fake stack.
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Both ways, the concatenation of the real stack and the fake stack
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will be the stack as it would have been on a real EM machine (see figure).
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.KF
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.DS L
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.ta 8 16 24 32 40 48 56 64 72
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EM machine target machine
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| | | |
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| | | |
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| | | |
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| | | |
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| | | real stack |
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| | | | |
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| | | | | growing
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| EM stack | | | |
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| | |_______________| \e|/
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| | | |
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| | | |
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| | | |
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| | | fake stack |
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| | | |
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|_______________| |_______________|
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.TS
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center;
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cw(3.5c) cw(3c) cw(3.5c)
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cw(3.5c) cw(3c) cw(3.5c)
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|cw(3.5c)| cw(3c) |cw(3.5c)| .
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EM machine target machine
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.I
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Relation between EM stack, real stack and fake stack.
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.R
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.DE
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.KE
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real stack
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stack
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grows
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EM stack \s+2\(br\s0
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\s+2\(br\s0
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\s+2\(br\s0 _
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\s+2\(br\s0
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\s+2\(da\s0
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fake stack
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_ _
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.T&
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ci s s.
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Relation between EM stack, real stack and fake stack.
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.TE
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During code generation tokens will be kept on the fake stack as long
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as possible but when they are moved to the real stack,
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by generating code for the push,
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all tokens above\u*\d
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all tokens above\v'-.25m'\(dg\v'.25m'
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.FS
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* in this document the stack is assumed to grow downwards,
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\(dg in this document the stack is assumed to grow downwards,
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although the top of the stack will mean the first element that will
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be popped.
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.FE
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@ -297,8 +298,9 @@ at will to improve legibility.
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Identifiers used in the table have the same syntax as C identifiers,
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upper and lower case considered different, all characters significant.
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Here is a list of reserved words; all of these are unavailable as identifiers.
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.DS L
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.ta 14 28 42 56
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.TS
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box;
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l l l l l.
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ADDR STACK from reg_any test
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COERCIONS STACKINGRULES gen reg_float to
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INSTRUCTIONS TESTS highw reg_loop ufit
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@ -309,7 +311,7 @@ PROPERTIES cost loww reusing
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REGISTERS defined move rom
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SETS exact pat samesign
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SIZEFACTOR example proc sfit
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.DE
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.TE
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C style comments are accepted.
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.DS
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/* this is a comment */
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@ -330,7 +332,7 @@ NAME=value
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.DE
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value being an integer or string.
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Three constants must be defined here:
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.IP EM_WSIZE 10
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.IP EM_WSIZE 14
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Number of bytes in a machine word.
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This is the number of bytes
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a \fBloc\fP instruction will put on the stack.
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@ -368,13 +370,13 @@ FORMAT= "0%o"
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to satisfy the old UNIX assembler that reads octal unless followed by
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a period, and the ACK assembler that follows C conventions.
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.PP
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Tables under control of programs like
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Tables under control of source code control systems like
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.I sccs
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or
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.I rcs
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can put their id-string here, for example
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.DS
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rcsid="$Header$"
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rcsid="$\&Header$"
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.DE
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These strings, like all strings in the table, will eventually
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end up in the binary code generator produced.
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@ -385,6 +387,7 @@ same order of magnitude.
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This can be done as
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.DS
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SIZEFACTOR = C\d3\u/C\d4\u
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.sp
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TIMEFACTOR = C\d1\u/C\d2\u
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.DE
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Above numbers must be read as rational numbers.
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@ -403,8 +406,8 @@ It consists of a list of user-defined
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identifiers optionally followed by the size
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of the property in parentheses, default EM_WSIZE.
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Example for the PDP-11:
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.DS
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.ta 8 16 24 32 40
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.TS
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l l.
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PROPERTIES /* The header word for this section */
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GENREG /* All PDP registers */
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@ -420,15 +423,11 @@ DBLREGPAIR(16) /* Same, double precision */
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LOCALBASE /* Guess what */
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STACKPOINTER
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PROGRAMCOUNTER
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.DE
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.TE
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Registers are allocated by asking for a property,
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so if for some reason in later parts of the table
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one particular register must be allocated it
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has to have a unique property.
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.PP
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There is a bug in the codegenerator that can be circumvented by
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providing a dummy property at the start of the property list.
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The example has not been updated to show this.
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.NH 2
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Register definition
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.PP
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@ -442,8 +441,8 @@ Syntax:
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<register> : ident [ '(' string ')' ] [ '=' ident [ '+' ident ] ]
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.DE
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Example for the PDP-11:
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.DS L
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.ta 8 16 24 32 40 48 56 64
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.TS
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l l.
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REGISTERS
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r0,r2,r4 : GENREG,REG.
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@ -457,7 +456,7 @@ dr01("r0")=dr0+dr1,dr23("r2")=dr2+dr3 : DBLREGPAIR.
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lb("r5") : GENREG,LOCALBASE.
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sp : GENREG,STACKPOINTER.
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pc : GENREG,PROGRAMCOUNTER.
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.DE
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.TE
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.PP
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The names in the left hand lists are names of registers as used
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in the table.
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@ -529,7 +528,8 @@ Tokens should usually be declared for every addressing mode
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of the machine at hand and for every size directly usable in
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a machine instruction.
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Example for the PDP-11 (incomplete):
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.DS L
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.TS
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l l.
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TOKENS
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const2 = { INT num; } 2 cost(2,300) "$" num .
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@ -542,7 +542,7 @@ reginddef2 = { GENREG reg; ADDR off; } 2 "*" off "(" reg ")" .
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regconst2 = { GENREG reg; ADDR off; } 2 .
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relative2 = { ADDR off; } 2 off .
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reldef2 = { ADDR off; } 2 "*" off.
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.DE
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.TE
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.PP
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Types allowed in the struct are ADDR, INT and all register properties.
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The type ADDR means a string and an integer,
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@ -624,13 +624,13 @@ in the remainder of the table,
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but for clarity it is usually better not to.
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.LP
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Example for the PDP-11 (incomplete):
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.DS L
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.ta 8 16 24 32 40 48 56 64
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.TS
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l l.
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SETS
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src2 = GENREG + regdef2 + regind2 + reginddef2 + relative2 +
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reldef2 + addr_external + const2 + LOCAL + ILOCAL +
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autodec + autoinc .
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\h'\w'= 'u'reldef2 + addr_external + const2 + LOCAL + ILOCAL +
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\h'\w'= 'u'autodec + autoinc .
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dst2 = src2 - ( const2 + addr_external ) .
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xsrc2 = src2 + ftoint .
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src1 = regdef1 + regind1 + reginddef1 + relative1 + reldef1 .
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@ -638,7 +638,7 @@ dst1 = src1 .
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src1or2 = src1 + src2 .
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src4 = relative4 + regdef4 + DLOCAL + regind4 .
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dst4 = src4 .
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.DE
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.TE
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Permissible in the set construction are all the usual set operators, i.e.
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.IP +
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set union
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@ -1252,7 +1252,7 @@ The author of
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.I cgg
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could not get
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.I yacc
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to be silent without it.
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to accept his syntax without it.
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Sorry about this.
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.IP 2)
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a
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@ -1370,15 +1370,14 @@ A list of examples for the PDP-11 is given here.
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Far from being complete it gives examples of most kinds
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of instructions.
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.DS
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.ta 8 16 24 32 40 48 56 64
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.ta 7.5c
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pat loc yields {const2, $1}
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pat ldc yields {const2, loww($1)}
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{const2, highw($1)}
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pat ldc yields {const2, loww($1)} {const2, highw($1)}
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.DE
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These simple patterns just push one or more tokens onto the fake stack.
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.DS
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.ta 8 16 24 32 40 48 56 64
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.ta 7.5c
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pat lof
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with REG yields {regind2,%1,$1}
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with exact regconst2 yields {regind2,%1.reg,$1+%1.off}
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@ -1393,10 +1392,9 @@ not preceded by
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that can always be taken after a coercion,
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if necessary.
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.DS
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.ta 8 16 24 32 40 48 56 64
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.ta 7.5c
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pat lxl $1>3
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uses REG={LOCAL, SL, 2},
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REG={const2,$1-1}
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uses REG={LOCAL, SL, 2}, REG={const2,$1-1}
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gen 1:
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move {regind2,%a, SL},%a
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sob %b,{label,1b} yields %a
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@ -1408,7 +1406,7 @@ of the static link,
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that is pushed by the Pascal compiler as the last argument of
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a function.
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.DS
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.ta 8 16 24 32 40 48 56 64
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.ta 7.5c
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pat stf
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with regconst2 xsrc2
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kills allexeptcon
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@ -1423,7 +1421,7 @@ part in a store instruction.
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The set allexeptcon contains all tokens that can be the destination
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of an indirect store.
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.DS
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.ta 8 16 24 32 40 48 56 64
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.ta 7.5c
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pat sde
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with exact FLTREG
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kills posextern
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@ -1449,7 +1447,7 @@ The third rule is taken by default,
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resulting in two separate stores,
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nothing better exists on the PDP-11.
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.DS
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.ta 8 16 24 32 40 48 56 64
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.ta 7.5c
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pat sbi $1==2
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with src2 REG
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gen sub %1,%2 yields %2
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|
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@ -1462,7 +1460,7 @@ This rule for
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has a normal first part,
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and a hand optimized special case as it's second part.
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.DS
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.ta 8 16 24 32 40 48 56 64
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.ta 7.5c
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pat mli $1==2
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with ODDREG src2
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gen mul %2,%1 yields %1
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|
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@ -1473,7 +1471,7 @@ This shows the general property for rules with commutative
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operators,
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heuristics or look ahead will have to decide which rule is the best.
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.DS
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.ta 8 16 24 32 40 48 56 64
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.ta 7.5c
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pat loc sli $1==1 && $2==2
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with REG
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gen asl %1 yields %1
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|
|
@ -1481,7 +1479,7 @@ gen asl %1 yields %1
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A simple rule involving a longer EM-pattern,
|
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to make use of a specialized instruction available.
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.DS
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.ta 8 16 24 32 40 48 56 64
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.ta 7.5c
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pat loc loc cii $1==1 && $2==2
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with src1or2
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uses reusing %1,REG
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|
|
@ -1492,8 +1490,9 @@ Note the
|
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.I reusing
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clause.
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.DS
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.ta 8 16 24 32 40 48 56 64
|
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pat loc loc loc cii $1>=0 && $2==2 && $3==4 leaving loc $1 loc 0
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.ta 7.5c
|
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pat loc loc loc cii $1>=0 && $2==2 && $3==4
|
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leaving loc $1 loc 0
|
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.DE
|
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Shows a trivial example of EM-replacement.
|
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This is a rule that could be done by the
|
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|
|
@ -1502,7 +1501,7 @@ if word order in longs was defined in EM.
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On a `big-endian' machine the two replacement
|
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instructions would be the other way around.
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.DS
|
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.ta 8 16 24 32 40 48 56 64
|
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.ta 7.5c
|
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pat and $1==2
|
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with const2 REG
|
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gen bic {const2,~%1.num},%2 yields %2
|
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|
|
@ -1517,7 +1516,7 @@ if an
|
|||
.I and -instruction
|
||||
is not available on your machine.
|
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.DS
|
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.ta 8 16 24 32 40 48 56 64
|
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.ta 7.5c
|
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pat set $1==2
|
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with REG
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uses REG={const2,1}
|
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|
|
@ -1525,7 +1524,7 @@ gen ash %1,%a yields %a
|
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.DE
|
||||
Shows the building of a word-size set.
|
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.DS
|
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.ta 8 16 24 32 40 48 56 64
|
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.ta 7.5c
|
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pat lae aar $2==2 && rom($1,3)==1 && rom($1,1)==0
|
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leaving adi 2
|
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|
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|
|
@ -1535,7 +1534,7 @@ pat lae aar $2==2 && rom($1,3)==1 && rom($1,1)!=0
|
|||
Two rules showing the use of the rom pseudo function,
|
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and some array optimalisation.
|
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.DS
|
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.ta 8 16 24 32 40 48 56 64
|
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.ta 7.5c
|
||||
pat bra
|
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with STACK
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gen jbr {label, $1}
|
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|
|
@ -1544,7 +1543,7 @@ A simple jump.
|
|||
The stack pattern guarantees that everything will be stacked
|
||||
before the jump is taken.
|
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.DS
|
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.ta 8 16 24 32 40 48 56 64
|
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.ta 7.5c
|
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pat cal
|
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with STACK
|
||||
gen jsr pc,{label, $1}
|
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|
|
@ -1552,7 +1551,7 @@ gen jsr pc,{label, $1}
|
|||
A simple call.
|
||||
Same comments as previous rule.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
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.ta 7.5c
|
||||
pat lfr $1==2 yields r0
|
||||
pat lfr $1==4 yields r1 r0
|
||||
.DE
|
||||
|
|
@ -1564,7 +1563,7 @@ instruction, and some other instructions must leave
|
|||
the function return area intact.
|
||||
See the defining document for EM for exact information.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
pat ret $1==0
|
||||
with STACK
|
||||
gen mov lb,sp
|
||||
|
|
@ -1578,7 +1577,7 @@ In a table with register variables the
|
|||
part would just contain
|
||||
.I return .
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
pat blm
|
||||
with REG REG
|
||||
uses REG={const2,$1/2}
|
||||
|
|
@ -1596,7 +1595,7 @@ It uses the marriage thesis from Hall,
|
|||
a thesis from combinatorial mathematics,
|
||||
to accomplish this.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
pat exg $1==2
|
||||
with src2 src2 yields %1 %2
|
||||
.DE
|
||||
|
|
@ -1604,7 +1603,7 @@ This rule shows the exchanging of two elements on the fake stack.
|
|||
.NH 2
|
||||
Code rules using procedures
|
||||
.PP
|
||||
To start this chapter it must be admitted at once that the
|
||||
To start this section it must be admitted at once that the
|
||||
word procedure is chosen here mainly for it's advertising
|
||||
value.
|
||||
It more resembles a glorified goto but this of course can
|
||||
|
|
@ -1664,7 +1663,7 @@ The string `*' can be used as an equivalent for `[1]'.
|
|||
Just in case this is not clear, here is an example for
|
||||
a procedure to increment/decrement a register.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
incop REG:rw:cc . /* in the INSTRUCTIONS part of course */
|
||||
|
||||
proc incdec
|
||||
|
|
@ -1680,7 +1679,7 @@ call <identifier> '(' string [ ',' string ] ')'
|
|||
.DE
|
||||
which leads to the following large example:
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
proc bxx example beq
|
||||
with src2 src2 STACK
|
||||
gen cmp %2,%1
|
||||
|
|
@ -1856,7 +1855,7 @@ The next part of the table defines the coercions that are possible
|
|||
on the defined tokens.
|
||||
Example for the PDP-11:
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
COERCIONS
|
||||
|
||||
from STACK
|
||||
|
|
@ -1875,7 +1874,7 @@ gen mov {autoinc,sp},%a.1
|
|||
These three coercions just deliver a certain type
|
||||
of register by popping it from the real stack.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
from LOCAL yields {regind2,lb,%1.ind}
|
||||
|
||||
from DLOCAL yields {regind4,lb,%1.ind}
|
||||
|
|
@ -1884,7 +1883,7 @@ from REG yields {regconst2, %1, 0}
|
|||
.DE
|
||||
These three are zero-cost rewriting rules.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
from regconst2 %1.off==1
|
||||
uses reusing %1,REG=%1.reg
|
||||
gen inc %a yields %a
|
||||
|
|
@ -1904,7 +1903,7 @@ Only in the last case is it always necessary to allocate
|
|||
an extra register,
|
||||
since arithmetic on the localbase is unthinkable.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
from xsrc2
|
||||
uses reusing %1, REG=%1 yields %a
|
||||
|
||||
|
|
@ -1925,7 +1924,7 @@ ensure bytes are not sign-extended.
|
|||
In EM it is defined that the result of a \fBloi\fP\ 1
|
||||
instruction is an integer in the range 0..255.
|
||||
.DS
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 7.5c
|
||||
from REGPAIR yields %1.2 %1.1
|
||||
|
||||
from regind4 yields {regind2,%1.reg,2+%1.off}
|
||||
|
|
@ -2086,7 +2085,7 @@ If omitted no initialization is assumed.
|
|||
.NH 3
|
||||
Example mach.h for the PDP-11
|
||||
.DS L
|
||||
.ta 8 16 24 32 40 48 56
|
||||
.ta 4c
|
||||
#define ex_ap(y) fprintf(codefile,"\et.globl %s\en",y)
|
||||
#define in_ap(y) /* nothing */
|
||||
|
||||
|
|
@ -2157,7 +2156,7 @@ mes(w_mesno)
|
|||
This function is called when a
|
||||
.B mes
|
||||
pseudo is seen that is not handled by the machine independent part.
|
||||
Example below shows all you probably have to know about that.
|
||||
The example below shows all you probably have to know about that.
|
||||
.IP -
|
||||
segname[]
|
||||
.br
|
||||
|
|
@ -2216,7 +2215,7 @@ Example mach.c for the PDP-11
|
|||
As an example of the sort of code expected,
|
||||
the mach.c for the PDP-11 is presented here.
|
||||
.DS L
|
||||
.ta 8 16 24 32 40 48 56 64
|
||||
.ta 0.5i 1i 1.5i 2i 2.5i 3i 3.5i 4i 4.5i
|
||||
/*
|
||||
* machine dependent back end routines for the PDP-11
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in a new issue