Initial revision
This commit is contained in:
ceriel
parent
4c76583aba
commit
6833adfb50
6 changed files with 1146 additions and 0 deletions
16
mach/i386/as/mach0.c
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16
mach/i386/as/mach0.c
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/*
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* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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#define RCSID0 "$Header$"
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/*
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* INTEL 80386 options
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*/
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#define THREE_PASS /* branch and offset optimization */
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#define LISTING /* enable listing facilities */
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#define RELOCATION /* generate relocation info */
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#define DEBUG 2
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#undef valu_t
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#define valu_t long
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73
mach/i386/as/mach1.c
Normal file
73
mach/i386/as/mach1.c
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/*
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* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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#define RCSID1 "$Header$"
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/*
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* INTEL 80386 C declarations
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*/
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#define low6(z) (z & 077)
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#define fit6(z) (low6(z) == z)
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#define ufitb(z) ((unsigned)(z) <= 255)
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#define IS_R8 0x100
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#define IS_R32 0x200
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#define IS_EXPR 0x400
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#define IS_RSEG 0x800
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#define is_expr(reg) ((reg)&IS_EXPR)
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#define is_segreg(reg) ((reg)&IS_RSEG)
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#define is_reg(reg) (((reg)&(IS_R8|IS_R32)) != 0)
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#define is_acc(reg) (((reg)&(IS_R8|IS_R32)) == (reg))
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struct operand {
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int mod;
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int rm;
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int reg;
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int sib; /* scale-index-base */
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expr_t exp;
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};
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extern struct operand op_1, op_2;
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#define mod_1 op_1.mod
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#define mod_2 op_2.mod
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#define rm_1 op_1.rm
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#define rm_2 op_2.rm
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#define reg_1 op_1.reg
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#define reg_2 op_2.reg
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#define sib_1 op_1.sib
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#define sib_2 op_2.sib
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#define exp_1 op_1.exp
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#define exp_2 op_2.exp
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#ifdef RELOCATION
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extern int rel_1, rel_2;
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#endif
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#ifndef extern
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extern char regindex_ind[8][8];
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#else
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/* First index is base register; second index is index register;
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sp cannot be an index register.
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For base and index register indirect mode, bp cannot be the
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base register, but this info is not included in this array.
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This can always be handled by using the base and index register with
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displacement mode.
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*/
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char regindex_ind[8][8] = {
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000, 010, 020, 030, -1, 050, 060, 070,
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001, 011, 021, 031, -1, 051, 061, 071,
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002, 012, 022, 032, -1, 052, 062, 072,
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003, 013, 023, 033, -1, 053, 063, 073,
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004, 014, 024, 034, -1, 054, 064, 074,
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005, 015, 025, 035, -1, 055, 065, 075,
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006, 016, 026, 036, -1, 056, 066, 076,
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007, 017, 027, 037, -1, 057, 067, 077,
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};
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#endif
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extern int address_long INIT(1), operand_long INIT(1);
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47
mach/i386/as/mach2.c
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47
mach/i386/as/mach2.c
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/*
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* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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#define RCSID2 "$Header$"
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/*
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* INTEL 80386 tokens
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*/
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%token <y_word> R32
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%token <y_word> R16
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%token <y_word> R8
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%token <y_word> RSEG
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%token <y_word> RSYSCR
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%token <y_word> RSYSDR
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%token <y_word> RSYSTR
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%token <y_word> PREFIX
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%token <y_word> ADDOP
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%token <y_word> BITTEST
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%token <y_word> BOUND
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%token <y_word> CALFOP
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%token <y_word> CALLOP
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%token <y_word> ENTER
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%token <y_word> EXTEND
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%token <y_word> EXTOP
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%token <y_word> EXTOP1
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%token <y_word> IMUL
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%token <y_word> IMULB
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%token <y_word> INCOP
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%token <y_word> INT
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%token <y_word> IOOP
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%token <y_word> JOP
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%token <y_word> JOP2
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%token <y_word> LEAOP
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%token <y_word> LEAOP2
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%token <y_word> LSHFT
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%token <y_word> MOV
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%token <y_word> NOOP_1
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%token <y_word> NOOP_2
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%token <y_word> NOTOP
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%token <y_word> PUSHOP
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%token <y_word> RET
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%token <y_word> ROLOP
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%token <y_word> SETCC
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%token <y_word> TEST
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%token <y_word> XCHG
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279
mach/i386/as/mach3.c
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279
mach/i386/as/mach3.c
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/*
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* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
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* See the copyright notice in the ACK home directory, in the file "Copyright".
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*/
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#define RCSID3 "$Header$"
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/*
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* INTEL 80386 keywords
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*
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* No system registers for now ...
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*/
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0, R32, 0, "ax",
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0, R32, 1, "cx",
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0, R32, 2, "dx",
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0, R32, 3, "bx",
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0, R32, 4, "sp",
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0, R32, 5, "bp",
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0, R32, 6, "si",
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0, R32, 7, "di",
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0, R32, 0, "eax",
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0, R32, 1, "ecx",
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0, R32, 2, "edx",
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0, R32, 3, "ebx",
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0, R32, 4, "esp",
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0, R32, 5, "ebp",
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0, R32, 6, "esi",
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0, R32, 7, "edi",
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0, R8, 0, "al",
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0, R8, 1, "cl",
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0, R8, 2, "dl",
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0, R8, 3, "bl",
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0, R8, 4, "ah",
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0, R8, 5, "ch",
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0, R8, 6, "dh",
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0, R8, 7, "bh",
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0, RSEG, 0, "es",
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0, RSEG, 1, "cs",
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0, RSEG, 2, "ss",
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0, RSEG, 3, "ds",
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0, RSEG, 4, "fs",
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0, RSEG, 5, "gs",
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0, RSYSCR, 0, "cr0",
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0, RSYSCR, 2, "cr2",
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0, RSYSCR, 3, "cr3",
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0, RSYSDR, 0, "dr0",
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0, RSYSDR, 1, "dr1",
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0, RSYSDR, 2, "dr2",
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0, RSYSDR, 3, "dr3",
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0, RSYSDR, 6, "dr6",
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0, RSYSDR, 7, "dr7",
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0, RSYSTR, 6, "tr6",
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0, RSYSTR, 7, "tr7",
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0, ADDOP, 000, "addb",
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0, ADDOP, 001, "add",
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0, ADDOP, 010, "orb",
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0, ADDOP, 011, "or",
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0, ADDOP, 020, "adcb",
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0, ADDOP, 021, "adc",
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0, ADDOP, 030, "sbbb",
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0, ADDOP, 031, "sbb",
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0, ADDOP, 040, "andb",
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0, ADDOP, 041, "and",
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0, ADDOP, 050, "subb",
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0, ADDOP, 051, "sub",
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0, ADDOP, 060, "xorb",
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0, ADDOP, 061, "xor",
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0, ADDOP, 070, "cmpb",
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0, ADDOP, 071, "cmp",
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0, BITTEST, 04, "bt",
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0, BITTEST, 05, "bts",
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0, BITTEST, 06, "btr",
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0, BITTEST, 07, "btc",
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0, CALFOP, 030+(0232<<8), "callf",
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0, CALFOP, 050+(0352<<8), "jmpf",
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0, CALLOP, 020+(0350<<8), "call",
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0, CALLOP, 040+(0351<<8), "jmp",
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0, ENTER, 0310, "enter",
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0, EXTEND, 0266, "movzx",
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0, EXTEND, 0276, "movsx",
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0, EXTOP, 0002, "lar",
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0, EXTOP, 0003, "lsl",
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0, EXTOP, 0274, "bsf",
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0, EXTOP, 0275, "bsr",
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0, EXTOP1, 0000, "sldt",
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0, EXTOP1, 0001, "sgdt",
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0, EXTOP1, 0010, "str",
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0, EXTOP1, 0011, "sidt",
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0, EXTOP1, 0020, "lldt",
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0, EXTOP1, 0021, "lgdt",
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0, EXTOP1, 0030, "ltr",
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0, EXTOP1, 0031, "lidt",
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0, EXTOP1, 0040, "verr",
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0, EXTOP1, 0041, "smsw",
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0, EXTOP1, 0050, "verw",
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0, EXTOP1, 0061, "lmsw",
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0, IMUL, 0, "imul",
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0, IMULB, 0, "imulb",
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0, INCOP, 000, "incb",
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0, INCOP, 001, "inc",
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0, INCOP, 010, "decb",
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0, INCOP, 011, "dec",
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0, INT, 0, "int",
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0, IOOP, 0344, "inb",
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0, IOOP, 0345, "in",
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0, IOOP, 0346, "outb",
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0, IOOP, 0347, "out",
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0, JOP, 0340, "loopne",
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0, JOP, 0340, "loopnz",
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0, JOP, 0341, "loope",
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0, JOP, 0341, "loopz",
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0, JOP, 0342, "loop",
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0, JOP, 0343, "jcxz",
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0, JOP, 0343, "jecxz",
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0, JOP2, 0000, "jo",
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0, JOP2, 0001, "jno",
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0, JOP2, 0002, "jb",
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0, JOP2, 0002, "jnae",
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0, JOP2, 0003, "jae",
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0, JOP2, 0003, "jnb",
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0, JOP2, 0004, "je",
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0, JOP2, 0004, "jz",
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0, JOP2, 0005, "jne",
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0, JOP2, 0005, "jnz",
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0, JOP2, 0006, "jbe",
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0, JOP2, 0006, "jna",
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0, JOP2, 0007, "ja",
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0, JOP2, 0007, "jnbe",
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0, JOP2, 0010, "js",
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0, JOP2, 0011, "jns",
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0, JOP2, 0012, "jp",
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0, JOP2, 0012, "jpe",
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0, JOP2, 0013, "jnp",
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0, JOP2, 0013, "jpo",
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0, JOP2, 0014, "jl",
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0, JOP2, 0014, "jnge",
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0, JOP2, 0015, "jge",
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0, JOP2, 0015, "jnl",
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0, JOP2, 0016, "jle",
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0, JOP2, 0016, "jng",
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0, JOP2, 0017, "jg",
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0, JOP2, 0017, "jnle",
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0, LEAOP, 0142, "bound",
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0, LEAOP, 0215, "lea",
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0, LEAOP, 0304, "les",
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0, LEAOP, 0305, "lds",
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0, LEAOP2, 0262, "lss",
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0, LEAOP2, 0264, "lfs",
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0, LEAOP2, 0265, "lgs",
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0, LSHFT, 0244, "shld",
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0, LSHFT, 0254, "shrd",
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0, MOV, 0, "movb",
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0, MOV, 1, "mov",
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0, NOOP_1, 0140, "pusha",
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0, NOOP_1, 0140, "pushad",
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0, NOOP_1, 0141, "popa",
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0, NOOP_1, 0141, "popad",
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0, NOOP_1, 0156, "outsb",
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0, NOOP_1, 0157, "outs",
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0, NOOP_1, 0220, "nop",
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0, NOOP_1, 0230, "cbw",
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0, NOOP_1, 0230, "cwde", /* same opcode as cbw! */
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0, NOOP_1, 0231, "cdq", /* same opcode as cwd! */
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0, NOOP_1, 0231, "cwd",
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0, NOOP_1, 0233, "wait",
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0, NOOP_1, 0234, "pushf",
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0, NOOP_1, 0235, "popf",
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0, NOOP_1, 0236, "sahf",
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0, NOOP_1, 0237, "lahf",
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0, NOOP_1, 0244, "movsb",
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0, NOOP_1, 0245, "movs",
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0, NOOP_1, 0246, "cmpsb",
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0, NOOP_1, 0246, "insb",
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0, NOOP_1, 0247, "cmps",
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0, NOOP_1, 0247, "ins",
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0, NOOP_1, 0252, "stosb",
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0, NOOP_1, 0253, "stos",
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0, NOOP_1, 0254, "lodsb",
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0, NOOP_1, 0255, "lods",
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0, NOOP_1, 0256, "scasb",
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0, NOOP_1, 0257, "scas",
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0, NOOP_1, 0311, "leave",
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0, NOOP_1, 0316, "into",
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0, NOOP_1, 0317, "iret",
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0, NOOP_1, 0317, "iretd",
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0, NOOP_1, 0327, "xlat",
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0, NOOP_1, 0364, "hlt",
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0, NOOP_1, 0365, "cmc",
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0, NOOP_1, 0370, "clc",
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0, NOOP_1, 0371, "stc",
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||||
0, NOOP_1, 0372, "cli",
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||||
0, NOOP_1, 0373, "sti",
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||||
0, NOOP_1, 0374, "cld",
|
||||
0, NOOP_1, 0375, "std",
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||||
0, NOOP_1, 047, "daa",
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||||
0, NOOP_1, 057, "das",
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||||
0, NOOP_1, 067, "aaa",
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||||
0, NOOP_1, 077, "aas",
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||||
0, NOOP_2, 017+06<<8, "clts",
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||||
0, NOOP_2, 0324+012<<8, "aam",
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||||
0, NOOP_2, 0325+012<<8, "aad",
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||||
0, NOTOP, 020, "notb",
|
||||
0, NOTOP, 021, "not",
|
||||
0, NOTOP, 030, "negb",
|
||||
0, NOTOP, 031, "neg",
|
||||
0, NOTOP, 040, "mulb",
|
||||
0, NOTOP, 041, "mul",
|
||||
0, NOTOP, 060, "divb",
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||||
0, NOTOP, 061, "div",
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||||
0, NOTOP, 070, "idivb",
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||||
0, NOTOP, 071, "idiv",
|
||||
0, PREFIX, 0144, "fseg",
|
||||
0, PREFIX, 0145, "gseg",
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||||
0, PREFIX, 0146, "o16", /* operand size toggle */
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||||
0, PREFIX, 0146, "o32", /* operand size toggle */
|
||||
0, PREFIX, 0147, "a16", /* address size toggle */
|
||||
0, PREFIX, 0147, "a32", /* address size toggle */
|
||||
0, PREFIX, 0360, "lock",
|
||||
0, PREFIX, 0362, "rep",
|
||||
0, PREFIX, 0362, "repne",
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0, PREFIX, 0362, "repnz",
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0, PREFIX, 0363, "repe",
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0, PREFIX, 0363, "repz",
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0, PREFIX, 046, "eseg",
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0, PREFIX, 056, "cseg",
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0, PREFIX, 066, "sseg",
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0, PREFIX, 076, "dseg",
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0, PUSHOP, 0, "push",
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0, PUSHOP, 1, "pop",
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0, RET, 0303, "ret",
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||||
0, RET, 0313, "retf",
|
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0, ROLOP, 000, "rolb",
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0, ROLOP, 001, "rol",
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0, ROLOP, 010, "rorb",
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||||
0, ROLOP, 011, "ror",
|
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0, ROLOP, 020, "rclb",
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||||
0, ROLOP, 021, "rcl",
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||||
0, ROLOP, 030, "rcrb",
|
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0, ROLOP, 031, "rcr",
|
||||
0, ROLOP, 040, "salb",
|
||||
0, ROLOP, 040, "shlb",
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||||
0, ROLOP, 041, "sal",
|
||||
0, ROLOP, 041, "shl",
|
||||
0, ROLOP, 050, "shrb",
|
||||
0, ROLOP, 051, "shr",
|
||||
0, ROLOP, 070, "sarb",
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||||
0, ROLOP, 071, "sar",
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||||
0, SETCC, 0000, "seto",
|
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0, SETCC, 0001, "setno",
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||||
0, SETCC, 0002, "setb",
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||||
0, SETCC, 0002, "setnae",
|
||||
0, SETCC, 0003, "setae",
|
||||
0, SETCC, 0003, "setnb",
|
||||
0, SETCC, 0004, "sete",
|
||||
0, SETCC, 0004, "setz",
|
||||
0, SETCC, 0005, "setne",
|
||||
0, SETCC, 0005, "setnz",
|
||||
0, SETCC, 0006, "setbe",
|
||||
0, SETCC, 0006, "setna",
|
||||
0, SETCC, 0007, "seta",
|
||||
0, SETCC, 0007, "setnbe",
|
||||
0, SETCC, 0010, "sets",
|
||||
0, SETCC, 0011, "setns",
|
||||
0, SETCC, 0012, "setp",
|
||||
0, SETCC, 0012, "setpe",
|
||||
0, SETCC, 0013, "setnp",
|
||||
0, SETCC, 0013, "setpo",
|
||||
0, SETCC, 0014, "setl",
|
||||
0, SETCC, 0014, "setnge",
|
||||
0, SETCC, 0015, "setge",
|
||||
0, SETCC, 0015, "setnl",
|
||||
0, SETCC, 0016, "setle",
|
||||
0, SETCC, 0016, "setng",
|
||||
0, SETCC, 0017, "setg",
|
||||
0, SETCC, 0017, "setnle",
|
||||
0, TEST, 0, "testb",
|
||||
0, TEST, 1, "test",
|
||||
0, XCHG, 0, "xchgb",
|
||||
0, XCHG, 1, "xchg",
|
||||
198
mach/i386/as/mach4.c
Normal file
198
mach/i386/as/mach4.c
Normal file
|
|
@ -0,0 +1,198 @@
|
|||
#define RCSID4 "$Header$"
|
||||
|
||||
/*
|
||||
* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
|
||||
* See the copyright notice in the ACK home directory, in the file "Copyright".
|
||||
*
|
||||
*/
|
||||
|
||||
operation
|
||||
: { address_long = 1; operand_long = 1; }
|
||||
prefix oper
|
||||
;
|
||||
prefix : /* empty */
|
||||
| prefix PREFIX
|
||||
{ if ($2 == 0146) operand_long = ! operand_long;
|
||||
if ($2 == 0147) address_long = ! address_long;
|
||||
emit1($2);
|
||||
}
|
||||
;
|
||||
oper : NOOP_1
|
||||
{ emit1($1);}
|
||||
| NOOP_2
|
||||
{ emit2($1);}
|
||||
| JOP expr
|
||||
{ branch($1,$2);}
|
||||
| JOP2 expr
|
||||
{ ebranch($1,$2);}
|
||||
| PUSHOP ea_1
|
||||
{ pushop($1);}
|
||||
| IOOP absexp
|
||||
{ emit1($1);
|
||||
fit(ufitb($2));
|
||||
emit1((int)$2);
|
||||
}
|
||||
| IOOP R32
|
||||
{ if ($2!=2) serror("register error");
|
||||
emit1($1+010);
|
||||
}
|
||||
| BITTEST ea_ea
|
||||
{ bittestop($1);}
|
||||
| BOUND R32 ',' mem
|
||||
{ emit1($1); ea_2($2<<3); }
|
||||
| ADDOP ea_ea
|
||||
{ addop($1);}
|
||||
| ROLOP ea_ea
|
||||
{ rolop($1);}
|
||||
| INCOP ea_1
|
||||
{ incop($1);}
|
||||
| NOTOP ea_1
|
||||
{ regsize($1); emit1(0366|($1&1)); ea_1($1&070);}
|
||||
| CALLOP ea_1
|
||||
{ callop($1&0xFFFF);}
|
||||
| CALFOP expr ':' expr
|
||||
{ emit1($1>>8);
|
||||
#ifdef RELOCATION
|
||||
newrelo($4.typ, RELO4);
|
||||
#endif
|
||||
emit4((long)($4.val));
|
||||
#ifdef RELOCATION
|
||||
newrelo($2.typ, RELO2);
|
||||
#endif
|
||||
emit2((int)($2.val));
|
||||
}
|
||||
| CALFOP mem
|
||||
{ emit1(0377); ea_2($1&0xFF);}
|
||||
| ENTER absexp ',' absexp
|
||||
{ fit(fitw($2)); fit(fitb($4));
|
||||
emit1($1); emit2((int)$2); emit1((int)$4);
|
||||
}
|
||||
| LEAOP R32 ',' mem
|
||||
{ emit1($1); ea_2($2<<3);}
|
||||
| LEAOP2 R32 ',' mem
|
||||
{ emit1(0xF); emit1($1); ea_2($2<<3);}
|
||||
| LSHFT ea_1 ',' R32 ',' ea_2
|
||||
{ extshft($1, $4);}
|
||||
| EXTEND R32 ',' ea_2
|
||||
{ emit1(0xF); emit1($1|1); ea_2($2<<3);}
|
||||
| EXTOP R32 ',' ea_2
|
||||
{ emit1(0xF); emit1($1); ea_2($2<<3);}
|
||||
| EXTOP1 ea_1
|
||||
{ emit1(0xF); emit1($1&07); ea_1($1&070);}
|
||||
| IMULB ea_1
|
||||
{ regsize(0); emit1(0366); ea_1($1&070);}
|
||||
| IMUL ea_2
|
||||
{ reg_1 = IS_R32; imul(0); }
|
||||
| IMUL R32 ',' ea_2
|
||||
{ reg_1 = $2 | IS_R32; imul($2); }
|
||||
| IMUL R32 ',' ea_ea
|
||||
{ imul($2);}
|
||||
| INT absexp
|
||||
{ if ($2==3)
|
||||
emit1(0314);
|
||||
else {
|
||||
fit(ufitb($2));
|
||||
emit1(0315); emit1((int)$2);
|
||||
}
|
||||
}
|
||||
| RET
|
||||
{ emit1($1);}
|
||||
| RET expr
|
||||
{ emit1($1-1);
|
||||
#ifdef RELOCATION
|
||||
newrelo($2.typ, RELO2);
|
||||
#endif
|
||||
emit2((int)($2.val));
|
||||
}
|
||||
| SETCC ea_2
|
||||
{ emit1(0xF); emit1($1); ea_2(0);}
|
||||
| XCHG ea_ea
|
||||
{ xchg($1);}
|
||||
| TEST ea_ea
|
||||
{ test($1);}
|
||||
| MOV ea_ea
|
||||
{ mov($1);}
|
||||
| /* What is really needed is just
|
||||
MOV R32 ',' RSYSCR
|
||||
but this gives a bad yacc conflict
|
||||
*/
|
||||
MOV ea_1 ',' RSYSCR
|
||||
{
|
||||
if ($1 != 1 || !(reg_1 & IS_R32))
|
||||
serror("syntax error");
|
||||
emit1(0xF); emit1(042); emit1(0200|($4<<3)|(reg_1&07));}
|
||||
| MOV ea_1 ',' RSYSDR
|
||||
{
|
||||
if ($1 != 1 || !(reg_1 & IS_R32))
|
||||
serror("syntax error");
|
||||
emit1(0xF); emit1(043); emit1(0200|($4<<3)|(reg_1&07));}
|
||||
| MOV ea_1 ',' RSYSTR
|
||||
{
|
||||
if ($1 != 1 || !(reg_1 & IS_R32))
|
||||
serror("syntax error");
|
||||
emit1(0xF); emit1(046); emit1(0200|($4<<3)|(reg_1&07));}
|
||||
| MOV RSYSCR ',' R32
|
||||
{
|
||||
if ($1 != 1) serror("syntax error");
|
||||
emit1(0xF); emit1(040); emit1(0200|($4<<3)|$2);}
|
||||
| MOV RSYSDR ',' R32
|
||||
{
|
||||
if ($1 != 1) serror("syntax error");
|
||||
emit1(0xF); emit1(041); emit1(0200|($4<<3)|$2);}
|
||||
| MOV RSYSTR ',' R32
|
||||
{
|
||||
if ($1 != 1) serror("syntax error");
|
||||
emit1(0xF); emit1(044); emit1(0200|($4<<3)|$2);}
|
||||
;
|
||||
mem : '(' expr ')'
|
||||
{ rm_2 = 05; exp_2 = $2; reg_2 = 05; mod_2 = 0;
|
||||
RELOMOVE(rel_2, relonami);
|
||||
}
|
||||
| bases
|
||||
{ exp_2.val = 0; exp_2.typ = S_ABS; indexed();}
|
||||
| expr bases
|
||||
{ exp_2 = $1; indexed();
|
||||
RELOMOVE(rel_2, relonami);
|
||||
}
|
||||
;
|
||||
bases : '(' R32 ')'
|
||||
{ reg_2 = $2; sib_2 = 0; rm_2 = 0;}
|
||||
| '(' R32 ')' '(' R32 scale ')'
|
||||
{ rm_2 = 04; sib_2 |= regindex_ind[$2][$5];
|
||||
reg_2 = $2;
|
||||
}
|
||||
| '(' R32 '*' absexp ')'
|
||||
{ if ($4 == 1) {
|
||||
reg_2 = $2; sib_2 = 0; rm_2 = 0;
|
||||
}
|
||||
else {
|
||||
rm_2 = 04;
|
||||
sib_2 = checkscale($4) | regindex_ind[05][$2];
|
||||
reg_2 = 015;
|
||||
}
|
||||
}
|
||||
;
|
||||
scale : /* empty */
|
||||
{ sib_2 = 0;}
|
||||
| '*' absexp
|
||||
{ sib_2 = checkscale($2);}
|
||||
;
|
||||
ea_2 : mem
|
||||
| R8
|
||||
{ reg_2 = $1 | IS_R8; rm_2 = 0;}
|
||||
| R32
|
||||
{ reg_2 = $1 | IS_R32; rm_2 = 0;}
|
||||
| RSEG
|
||||
{ reg_2 = $1 | IS_RSEG; rm_2 = 0;}
|
||||
| expr
|
||||
{ reg_2 = IS_EXPR; exp_2 = $1; rm_2 = 0;
|
||||
RELOMOVE(rel_2, relonami);
|
||||
}
|
||||
;
|
||||
ea_1 : ea_2
|
||||
{ op_1 = op_2;
|
||||
RELOMOVE(rel_1, rel_2);
|
||||
}
|
||||
;
|
||||
ea_ea : ea_1 ',' ea_2
|
||||
;
|
||||
533
mach/i386/as/mach5.c
Normal file
533
mach/i386/as/mach5.c
Normal file
|
|
@ -0,0 +1,533 @@
|
|||
/*
|
||||
* (c) copyright 1987 by the Vrije Universiteit, Amsterdam, The Netherlands.
|
||||
* See the copyright notice in the ACK home directory, in the file "Copyright".
|
||||
*/
|
||||
#define RCSID5 "$Header$"
|
||||
|
||||
/*
|
||||
* INTEL 80386 special routines
|
||||
*/
|
||||
|
||||
ea_1(param) {
|
||||
if (is_expr(reg_1)) {
|
||||
serror("bad operand");
|
||||
return;
|
||||
}
|
||||
if (is_reg(reg_1)) {
|
||||
switch(reg_1&07) {
|
||||
case 4:
|
||||
emit1(0300 | param | 04);
|
||||
emit1(0300 | 0100);
|
||||
default:
|
||||
emit1(0300 | param | (reg_1&07));
|
||||
}
|
||||
return;
|
||||
}
|
||||
if (rm_1 == 04) {
|
||||
/* sib field use here */
|
||||
emit1(mod_1 << 6 | param | 04);
|
||||
emit1(sib_1 | reg_1);
|
||||
if ((mod_1 == 0 && reg_1 == 5) || mod_1 == 2) {
|
||||
#ifdef RELOCATION
|
||||
RELOMOVE(relonami, rel_1);
|
||||
newrelo(exp_1.typ, RELO4);
|
||||
#endif
|
||||
emit4((long)(exp_1.val));
|
||||
}
|
||||
else if (mod_1 == 1) emit1((int)(exp_1.val));
|
||||
return;
|
||||
}
|
||||
emit1(mod_1<<6 | param | (reg_1&07));
|
||||
if ((mod_1 == 0 && reg_1 == 5) || mod_1 == 2) {
|
||||
#ifdef RELOCATION
|
||||
RELOMOVE(relonami, rel_1);
|
||||
newrelo(exp_1.typ, RELO4);
|
||||
#endif
|
||||
emit4((long)(exp_1.val));
|
||||
}
|
||||
else if (mod_1 == 1) {
|
||||
emit1((int)(exp_1.val));
|
||||
}
|
||||
}
|
||||
|
||||
ea_2(param) {
|
||||
|
||||
op_1 = op_2;
|
||||
RELOMOVE(rel_1, rel_2);
|
||||
ea_1(param);
|
||||
}
|
||||
|
||||
int
|
||||
checkscale(val)
|
||||
valu_t val;
|
||||
{
|
||||
int v = val;
|
||||
|
||||
if (v != val) v = 0;
|
||||
switch(v) {
|
||||
case 1:
|
||||
return 0;
|
||||
case 2:
|
||||
return 1 << 6;
|
||||
case 4:
|
||||
return 2 << 6;
|
||||
case 8:
|
||||
return 3 << 6;
|
||||
default:
|
||||
serror("bad scale");
|
||||
return 0;
|
||||
}
|
||||
/*NOTREACHED*/
|
||||
}
|
||||
|
||||
reverse() {
|
||||
struct operand op;
|
||||
#ifdef RELOCATION
|
||||
int r = rel_1;
|
||||
|
||||
rel_1 = rel_2; rel_2 = r;
|
||||
#endif
|
||||
op = op_1; op_1 = op_2; op_2 = op;
|
||||
}
|
||||
|
||||
badsyntax() {
|
||||
|
||||
serror("bad operands");
|
||||
}
|
||||
|
||||
regsize(sz)
|
||||
int sz;
|
||||
{
|
||||
register int bit;
|
||||
|
||||
bit = (sz&1) ? 0 : IS_R8;
|
||||
if ((is_reg(reg_1) && (reg_1 & IS_R8) != bit) ||
|
||||
(is_reg(reg_2) && (reg_2 & IS_R8) != bit))
|
||||
serror("register error");
|
||||
}
|
||||
|
||||
indexed() {
|
||||
mod_2 = 0;
|
||||
if (sib_2 == -1)
|
||||
serror("register error");
|
||||
if (rm_2 == 0 && reg_2 == 4) {
|
||||
/* base register sp, no index register; use
|
||||
indexed mode without index register
|
||||
*/
|
||||
rm_2 = 04;
|
||||
sib_2 = 044;
|
||||
}
|
||||
if (reg_2 == 015) {
|
||||
reg_2 = 05;
|
||||
return;
|
||||
}
|
||||
if (exp_2.typ != S_ABS || fitb(exp_2.val) == 0)
|
||||
mod_2 = 02;
|
||||
else if (exp_2.val != 0 || reg_2 == 5)
|
||||
mod_2 = 01;
|
||||
}
|
||||
|
||||
ebranch(opc,exp)
|
||||
register int opc;
|
||||
expr_t exp;
|
||||
{
|
||||
/* Conditional branching; Full displacements are available
|
||||
on the 80386, so the welknown trick with the reverse branch
|
||||
over a jump is not needed here.
|
||||
The only complication here is with the address size, which
|
||||
can be set with a prefix. In this case, the user gets what
|
||||
he asked for.
|
||||
*/
|
||||
register int sm;
|
||||
register long dist;
|
||||
int saving = address_long ? 4 : 2;
|
||||
|
||||
dist = exp.val - (DOTVAL + 2);
|
||||
if (pass == PASS_2 && dist > 0 && !(exp.typ & S_DOT))
|
||||
dist -= DOTGAIN;
|
||||
sm = dist > 0 ? fitb(dist-saving) : fitb(dist);
|
||||
if ((exp.typ & ~S_DOT) != DOTTYP)
|
||||
sm = 0;
|
||||
if ((sm = small(sm,saving)) == 0) {
|
||||
emit1(0xF);
|
||||
emit1(opc | 0x80);
|
||||
dist -= 2;
|
||||
exp.val = dist;
|
||||
adsize_exp(exp);
|
||||
}
|
||||
else {
|
||||
emit1(opc | 0x70);
|
||||
emit1((int)dist);
|
||||
}
|
||||
}
|
||||
|
||||
branch(opc,exp)
|
||||
register int opc;
|
||||
expr_t exp;
|
||||
{
|
||||
/* LOOP, JCXZ, etc. branch instructions.
|
||||
Here, the offset just must fit in a byte.
|
||||
*/
|
||||
register long dist;
|
||||
|
||||
dist = exp.val - (DOTVAL + 2);
|
||||
if (pass == PASS_2 && dist > 0 && !(exp.typ & S_DOT))
|
||||
dist -= DOTGAIN;
|
||||
fit((exp.typ & ~S_DOT) == DOTTYP && fitb(dist));
|
||||
emit1(opc);
|
||||
emit1((int)dist);
|
||||
}
|
||||
|
||||
pushop(opc)
|
||||
register int opc;
|
||||
{
|
||||
|
||||
regsize(1);
|
||||
if (is_segreg(reg_1)) {
|
||||
/* segment register */
|
||||
if ((reg_1 & 07) <= 3)
|
||||
emit1(6 | opc | (reg_1&7)<<3);
|
||||
else {
|
||||
emit1(0xF);
|
||||
emit1(0200 | opc | ((reg_1&7)<<3));
|
||||
}
|
||||
} else if (is_reg(reg_1)) {
|
||||
/* normal register */
|
||||
emit1(0120 | opc<<3 | (reg_1&7));
|
||||
} else if (opc == 0) {
|
||||
if (is_expr(reg_1)) {
|
||||
if (exp_1.typ == S_ABS && fitb(exp_1.val)) {
|
||||
emit1(0152);
|
||||
emit1((int)(exp_1.val));
|
||||
}
|
||||
else {
|
||||
emit1(0150);
|
||||
RELOMOVE(relonami, rel_1);
|
||||
opsize_exp(exp_1, 1);
|
||||
}
|
||||
}
|
||||
else {
|
||||
emit1(0377); ea_1(6<<3);
|
||||
}
|
||||
} else {
|
||||
emit1(0217); ea_1(0<<3);
|
||||
}
|
||||
}
|
||||
|
||||
opsize_exp(exp, nobyte)
|
||||
expr_t exp;
|
||||
{
|
||||
if (! nobyte) {
|
||||
#ifdef RELOCATION
|
||||
newrelo(exp.typ, RELO1);
|
||||
#endif
|
||||
emit1((int)(exp.val));
|
||||
}
|
||||
else if (operand_long) {
|
||||
#ifdef RELOCATION
|
||||
newrelo(exp.typ, RELO4);
|
||||
#endif
|
||||
emit4((long)(exp.val));
|
||||
}
|
||||
else {
|
||||
#ifdef RELOCATION
|
||||
newrelo(exp.typ, RELO2);
|
||||
#endif
|
||||
emit2((int)(exp.val));
|
||||
}
|
||||
}
|
||||
|
||||
adsize_exp(exp)
|
||||
expr_t exp;
|
||||
{
|
||||
if (address_long) {
|
||||
#ifdef RELOCATION
|
||||
newrelo(exp.typ, RELO4 | RELPC);
|
||||
#endif
|
||||
emit4((long)(exp.val));
|
||||
}
|
||||
else {
|
||||
if (! fitw(exp.val)) {
|
||||
warning("offset does not fit in 2 bytes; remove prefix");
|
||||
}
|
||||
#ifdef RELOCATION
|
||||
newrelo(exp.typ, RELO2 | RELPC);
|
||||
#endif
|
||||
emit2((int)(exp.val));
|
||||
}
|
||||
}
|
||||
|
||||
addop(opc)
|
||||
register int opc;
|
||||
{
|
||||
|
||||
regsize(opc);
|
||||
if (is_reg(reg_2)) {
|
||||
/* Add register to register or memory */
|
||||
emit1(opc); ea_1((reg_2&7)<<3);
|
||||
} else if (is_acc(reg_1) && is_expr(reg_2)) {
|
||||
/* Add immediate to accumulator */
|
||||
emit1(opc | 4);
|
||||
RELOMOVE(relonami, rel_2);
|
||||
opsize_exp(exp_2, (opc&1));
|
||||
} else if (is_expr(reg_2)) {
|
||||
/* Add immediate to register or memory */
|
||||
if ((opc&1) == 0) {
|
||||
emit1(0200);
|
||||
} else if (exp_2.typ != S_ABS || fitb(exp_2.val) == 0) {
|
||||
emit1(0201);
|
||||
} else {
|
||||
emit1(0203); opc &= ~1;
|
||||
}
|
||||
ea_1(opc & 070);
|
||||
RELOMOVE(relonami, rel_2);
|
||||
opsize_exp(exp_2, (opc&1));
|
||||
} else if (is_reg(reg_1)) {
|
||||
/* Add register or memory to register */
|
||||
emit1(opc | 2);
|
||||
ea_2((reg_1&7)<<3);
|
||||
} else
|
||||
badsyntax();
|
||||
}
|
||||
|
||||
rolop(opc)
|
||||
register int opc;
|
||||
{
|
||||
register int oreg;
|
||||
|
||||
oreg = reg_2;
|
||||
reg_2 = reg_1;
|
||||
regsize(opc);
|
||||
if (oreg == (IS_R8 | 1)) {
|
||||
/* cl register */
|
||||
emit1(0322 | (opc&1)); ea_1(opc&070);
|
||||
} else if (is_expr(oreg) && exp_2.typ == S_ABS && exp_2.val == 1) {
|
||||
/* shift by 1 */
|
||||
emit1(0320 | (opc&1)); ea_1(opc&070);
|
||||
} else if (is_expr(oreg)) {
|
||||
/* shift by byte count */
|
||||
emit1(0300 | (opc & 1));
|
||||
ea_1(opc & 070);
|
||||
#ifdef RELOCATION
|
||||
RELOMOVE(relonami, rel_2);
|
||||
newrelo(exp_2.typ, RELO1);
|
||||
#endif
|
||||
emit1((int)(exp_2.val));
|
||||
}
|
||||
else
|
||||
badsyntax();
|
||||
}
|
||||
|
||||
incop(opc)
|
||||
register int opc;
|
||||
{
|
||||
|
||||
regsize(opc);
|
||||
if ((opc&1) && is_reg(reg_1)) {
|
||||
/* word register */
|
||||
emit1(0100 | (opc&010) | (reg_1&7));
|
||||
} else {
|
||||
emit1(0376 | (opc&1));
|
||||
ea_1(opc & 010);
|
||||
}
|
||||
}
|
||||
|
||||
callop(opc)
|
||||
register int opc;
|
||||
{
|
||||
|
||||
regsize(1);
|
||||
if (is_expr(reg_1)) {
|
||||
if (opc == (040+(0351<<8))) {
|
||||
RELOMOVE(relonami, rel_1);
|
||||
ebranch(0353,exp_1);
|
||||
} else {
|
||||
exp_1.val -= (DOTVAL+3);
|
||||
emit1(opc>>8);
|
||||
RELOMOVE(relonami, rel_1);
|
||||
adsize_exp(exp_1);
|
||||
}
|
||||
} else {
|
||||
emit1(0377); ea_1(opc&070);
|
||||
}
|
||||
}
|
||||
|
||||
xchg(opc)
|
||||
register int opc;
|
||||
{
|
||||
|
||||
regsize(opc);
|
||||
if (! is_reg(reg_1) || is_acc(reg_2)) {
|
||||
reverse();
|
||||
}
|
||||
if (opc == 1 && is_acc(reg_1) && is_reg(reg_2)) {
|
||||
emit1(0220 | (reg_2&7));
|
||||
} else if (is_reg(reg_1)) {
|
||||
emit1(0206 | opc); ea_2((reg_1&7)<<3);
|
||||
} else
|
||||
badsyntax();
|
||||
}
|
||||
|
||||
test(opc)
|
||||
register int opc;
|
||||
{
|
||||
|
||||
regsize(opc);
|
||||
if (is_reg(reg_2) || is_expr(reg_1))
|
||||
reverse();
|
||||
if (is_expr(reg_2)) {
|
||||
if (is_acc(reg_1)) {
|
||||
emit1(0250 | opc);
|
||||
RELOMOVE(relonami, rel_2);
|
||||
opsize_exp(exp_2, (opc&1));
|
||||
}
|
||||
else {
|
||||
emit1(0366 | opc);
|
||||
ea_1(0<<3);
|
||||
RELOMOVE(relonami, rel_2);
|
||||
opsize_exp(exp_2, (opc&1));
|
||||
}
|
||||
} else if (is_reg(reg_1)) {
|
||||
emit1(0204 | opc); ea_2((reg_1&7)<<3);
|
||||
} else
|
||||
badsyntax();
|
||||
}
|
||||
|
||||
mov(opc)
|
||||
register int opc;
|
||||
{
|
||||
|
||||
regsize(opc);
|
||||
if (is_segreg(reg_1)) {
|
||||
/* to segment register */
|
||||
emit1(0216); ea_2((reg_1&3)<<3);
|
||||
} else if (is_segreg(reg_2)) {
|
||||
/* from segment register */
|
||||
emit1(0214); ea_1((reg_2&3)<<3);
|
||||
} else if (is_expr(reg_2)) {
|
||||
/* from immediate */
|
||||
if (is_reg(reg_1)) {
|
||||
/* to register */
|
||||
emit1(0260 | opc<<3 | (reg_1&7));
|
||||
} else {
|
||||
/* to memory */
|
||||
emit1(0306 | opc); ea_1(0<<3);
|
||||
}
|
||||
RELOMOVE(relonami, rel_2);
|
||||
opsize_exp(exp_2, (opc&1));
|
||||
} else if (rm_1 == 05 && is_acc(reg_2)) {
|
||||
/* from accumulator to memory (displacement) */
|
||||
emit1(0242 | opc);
|
||||
RELOMOVE(relonami, rel_1);
|
||||
adsize_exp(exp_1);
|
||||
} else if (rm_2 == 05 && is_acc(reg_1)) {
|
||||
/* from memory (displacement) to accumulator */
|
||||
emit1(0240 | opc);
|
||||
RELOMOVE(relonami, rel_2);
|
||||
adsize_exp(exp_2);
|
||||
} else if (is_reg(reg_2)) {
|
||||
/* from register to memory or register */
|
||||
emit1(0210 | opc); ea_1((reg_2&7)<<3);
|
||||
} else if (is_reg(reg_1)) {
|
||||
/* from memory or register to register */
|
||||
emit1(0212 | opc); ea_2((reg_1&7)<<3);
|
||||
} else
|
||||
badsyntax();
|
||||
}
|
||||
|
||||
extshft(opc, reg)
|
||||
int opc;
|
||||
{
|
||||
int oreg2 = reg_2;
|
||||
|
||||
reg_2 = reg_1;
|
||||
regsize(1);
|
||||
|
||||
emit1(0xF);
|
||||
if (oreg2 == (IS_R8 | 1)) {
|
||||
/* cl register */
|
||||
emit1(opc|1);
|
||||
ea_1(reg << 3);
|
||||
}
|
||||
else if (is_expr(oreg2)) {
|
||||
emit1(opc);
|
||||
ea_1(reg << 3);
|
||||
#ifdef RELOCATION
|
||||
RELOMOVE(relonami, rel_2);
|
||||
newrelo(exp_2.typ, RELO1);
|
||||
#endif
|
||||
emit1((int)(exp_2.val));
|
||||
}
|
||||
else badsyntax();
|
||||
}
|
||||
|
||||
bittestop(opc)
|
||||
int opc;
|
||||
{
|
||||
regsize(1);
|
||||
emit1(0xF);
|
||||
if (is_expr(reg_2)) {
|
||||
emit1(0272);
|
||||
ea_1(opc << 3);
|
||||
#ifdef RELOCATION
|
||||
RELOMOVE(relonami, rel_2);
|
||||
newrelo(exp_2.typ, RELO1);
|
||||
#endif
|
||||
emit1((int)(exp_2.val));
|
||||
}
|
||||
else if (is_reg(reg_2)) {
|
||||
emit1(0203 | opc);
|
||||
ea_1((reg_2&7)<<3);
|
||||
}
|
||||
else badsyntax();
|
||||
}
|
||||
|
||||
imul(reg)
|
||||
int reg;
|
||||
{
|
||||
/* This instruction is more elaborate on the 80386. Its most
|
||||
general form is:
|
||||
imul reg, reg_or_mem, immediate.
|
||||
This is the form processed here.
|
||||
*/
|
||||
regsize(1);
|
||||
if (is_expr(reg_1)) {
|
||||
/* To also handle
|
||||
imul reg, immediate, reg_or_mem
|
||||
*/
|
||||
reverse();
|
||||
}
|
||||
if (is_expr(reg_2)) {
|
||||
/* The immediate form; two cases: */
|
||||
if (exp_2.typ == S_ABS && fitb(exp_2.val)) {
|
||||
/* case 1: 1 byte encoding of immediate */
|
||||
emit1(0153);
|
||||
ea_1(reg << 3);
|
||||
emit1((int)(exp_2.val));
|
||||
}
|
||||
else {
|
||||
/* case 2: WORD or DWORD encoding of immediate */
|
||||
emit1(0151);
|
||||
ea_1(reg << 3);
|
||||
RELOMOVE(relonami, rel_2);
|
||||
opsize_exp(exp_2, 1);
|
||||
}
|
||||
}
|
||||
else if (is_reg(reg_1) && ((reg_1&7) == reg)) {
|
||||
/* the "reg" field and the "reg_or_mem" field are the same,
|
||||
and the 3rd operand is not an immediate ...
|
||||
*/
|
||||
if (reg == 0) {
|
||||
/* how lucky we are, the target is the ax register */
|
||||
emit1(0367);
|
||||
ea_2(06 << 3);
|
||||
}
|
||||
else {
|
||||
/* another register ... */
|
||||
emit1(0xF);
|
||||
emit1(0257);
|
||||
ea_2(reg << 3);
|
||||
}
|
||||
}
|
||||
else badsyntax();
|
||||
}
|
||||
Loading…
Reference in a new issue