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move to address register does not set condition codes

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ceriel 1989-02-06 15:11:49 +00:00
parent 929716a621
commit 687d428026
4 changed files with 4 additions and 0 deletions
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1
mach/m68020/ncg/table
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@ -490,6 +490,7 @@ lsl_l "lsl.l" shconreg:ro, D_REG:rw:cc cost(2,4).
lsl "lsl #1," memalt2:rw:cc cost(2,4).
lsr_l "lsr.l" shconreg:ro, D_REG:rw:cc cost(2,4).
lsr "lsr #1," memalt2:rw:cc cost(2,4).
move_l "move.l" any4:ro, A_REG:wo cost(2,2).
move_l "move.l" any4:ro, alterable4:wo:cc cost(2,2).
move_w "move.w" any2:ro, alterable2:wo:cc cost(2,2).
move_b "move.b" any1:ro, alterable1:wo:cc cost(2,2).

1
mach/m68k2/ncg/table
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@ -490,6 +490,7 @@ lsl_l "lsl.l" shconreg:ro, D_REG:rw:cc cost(2,4).
lsl "lsl #1," memalt2:rw:cc cost(2,4).
lsr_l "lsr.l" shconreg:ro, D_REG:rw:cc cost(2,4).
lsr "lsr #1," memalt2:rw:cc cost(2,4).
move_l "move.l" any4:ro, A_REG:wo cost(2,2).
move_l "move.l" any4:ro, alterable4:wo:cc cost(2,2).
move_w "move.w" any2:ro, alterable2:wo:cc cost(2,2).
move_b "move.b" any1:ro, alterable1:wo:cc cost(2,2).

1
mach/m68k4/ncg/table
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@ -490,6 +490,7 @@ lsl_l "lsl.l" shconreg:ro, D_REG:rw:cc cost(2,4).
lsl "lsl #1," memalt2:rw:cc cost(2,4).
lsr_l "lsr.l" shconreg:ro, D_REG:rw:cc cost(2,4).
lsr "lsr #1," memalt2:rw:cc cost(2,4).
move_l "move.l" any4:ro, A_REG:wo cost(2,2).
move_l "move.l" any4:ro, alterable4:wo:cc cost(2,2).
move_w "move.w" any2:ro, alterable2:wo:cc cost(2,2).
move_b "move.b" any1:ro, alterable1:wo:cc cost(2,2).

1
mach/moon3/ncg/table
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@ -490,6 +490,7 @@ lsl_l "lsl.l" shconreg:ro, D_REG:rw:cc cost(2,4).
lsl "lsl #1," memalt2:rw:cc cost(2,4).
lsr_l "lsr.l" shconreg:ro, D_REG:rw:cc cost(2,4).
lsr "lsr #1," memalt2:rw:cc cost(2,4).
move_l "move.l" any4:ro, A_REG:wo cost(2,2).
move_l "move.l" any4:ro, alterable4:wo:cc cost(2,2).
move_w "move.w" any2:ro, alterable2:wo:cc cost(2,2).
move_b "move.b" any1:ro, alterable1:wo:cc cost(2,2).