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Bug fixed for pattern 'sti $1 > 4' (ADDREG -> ADDSCR)

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Bug was present since version 1.1
This commit is contained in:
bal 1985-04-16 15:24:23 +00:00
parent d10d14acac
commit 7b745d6fb2
1 changed files with 1 additions and 1 deletions
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2
mach/m68k2/cg/table
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@ -461,7 +461,7 @@ sti $1 == 2 | ADDREG ANY | remove(MEM_ALL)
move(%[2],{IADDREG,%[1]}) | | |
sti $1 == 4 | ADDREG ANY4 | remove(MEM_ALL)
move(%[2],{IADDREG4,%[1]}) | | |
sti $1 > 4 | ADDREG | remove(ALL)
sti $1 > 4 | ADDSCR | remove(ALL)
allocate(DATAREG4={IMMEDIATE4,$1/2-1})
"1:"
"move.w (sp)+,(%[1])+"