Use ha16/lo16 to load or store 1, 2, 8 bytes from labels.
Add the tokens IND_RL_B, IND_RL_H, IND_RL_H_S, IND_RL_D, along with the rules to use them. These rules emit shorter code. For example, loading a byte becomes lis, lbz instead of lis, addi, lbz. While making this, I wrongly set IND_RL_D to size 4. Then ncg made infinite recursion in codegen() and stackupto(), until it crashed by stack overflow. I correctly set IND_RL_D to size 8, preventing the crash.
This commit is contained in:
George Koehler
parent
5e00e1fce2
commit
85391399a4
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@ -189,15 +189,19 @@ TOKENS
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SEX_H = { GPR reg; } 4.
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IND_RC_B = { GPR reg; INT off; } 4 off "(" reg ")".
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IND_RL_B = { GPR reg; ADDR adr; } 4 "lo16[" adr "](" reg ")".
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IND_RR_B = { GPR reg1; GPR reg2; } 4.
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IND_RC_H = { GPR reg; INT off; } 4 off "(" reg ")".
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IND_RL_H = { GPR reg; ADDR adr; } 4 "lo16[" adr "](" reg ")".
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IND_RR_H = { GPR reg1; GPR reg2; } 4.
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IND_RC_H_S = { GPR reg; INT off; } 4 off "(" reg ")".
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IND_RL_H_S = { GPR reg; ADDR adr; } 4 "lo16[" adr "](" reg ")".
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IND_RR_H_S = { GPR reg1; GPR reg2; } 4.
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IND_RC_W = { GPR reg; INT off; } 4 off "(" reg ")".
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IND_RL_W = { GPR reg; ADDR adr; } 4 "lo16[" adr "](" reg ")".
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IND_RR_W = { GPR reg1; GPR reg2; } 4.
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IND_RC_D = { GPR reg; INT off; } 8 off "(" reg ")".
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IND_RL_D = { GPR reg; ADDR adr; } 8 "lo16[" adr "](" reg ")".
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IND_RR_D = { GPR reg1; GPR reg2; } 8.
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NOT_R = { GPR reg; } 4.
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@ -244,11 +248,11 @@ SETS
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LOGICAL_ALL = NOT_R + AND_RR + OR_RR + OR_RC + XOR_RR +
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XOR_RC.
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/* indirect values */
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IND_ALL_B = IND_RC_B + IND_RR_B.
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IND_ALL_H = IND_RC_H + IND_RR_H + IND_RC_H_S + IND_RR_H_S.
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IND_ALL_B = IND_RC_B + IND_RL_B + IND_RR_B.
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IND_ALL_H = IND_RC_H + IND_RL_H + IND_RR_H +
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IND_RC_H_S + IND_RL_H_S + IND_RR_H_S.
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IND_ALL_W = IND_RC_W + IND_RL_W + IND_RR_W.
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IND_ALL_D = IND_RC_D + IND_RR_D.
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IND_ALL_D = IND_RC_D + IND_RL_D + IND_RR_D.
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IND_ALL_BHW = IND_ALL_B + IND_ALL_H + IND_ALL_W.
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/* anything killed by sti (store indirect) */
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@ -326,17 +330,17 @@ INSTRUCTIONS
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frsp FSREG:wo, FREG:ro cost(4, 5).
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fsub FREG:wo, FREG:ro, FREG:ro cost(4, 5).
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fsubs FSREG:wo, FSREG:ro, FSREG:ro cost(4, 5).
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lbz GPR:wo, IND_RC_B:ro cost(4, 3).
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lbz GPR:wo, IND_RC_B+IND_RL_B:ro cost(4, 3).
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lbzx GPR:wo, GPR:ro, GPR:ro cost(4, 3).
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lfd FPR:wo, IND_RC_D:ro cost(4, 5).
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lfd FPR:wo, IND_RC_D+IND_RL_D:ro cost(4, 5).
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lfdu FPR:wo, IND_RC_D:ro cost(4, 5).
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lfdx FPR:wo, GPR:ro, GPR:ro cost(4, 5).
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lfs FSREG:wo, IND_RC_W+IND_RL_W:ro cost(4, 4).
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lfsu FSREG:wo, IND_RC_W:rw cost(4, 4).
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lfsx FSREG:wo, GPR:ro, GPR:ro cost(4, 4).
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lha GPR:wo, IND_RC_H_S:ro cost(4, 3).
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lha GPR:wo, IND_RC_H_S+IND_RL_H_S:ro cost(4, 3).
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lhax GPR:wo, GPR:ro, GPR:ro cost(4, 3).
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lhz GPR:wo, IND_RC_H:ro cost(4, 3).
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lhz GPR:wo, IND_RC_H+IND_RL_H:ro cost(4, 3).
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lhzx GPR:wo, GPR:ro, GPR:ro cost(4, 3).
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lwzu GPR:wo, IND_RC_W:ro cost(4, 3).
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lwzx GPR:wo, GPR:ro, GPR:ro cost(4, 3).
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@ -362,15 +366,15 @@ INSTRUCTIONS
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sraw GPR:wo, GPR:ro, GPR:ro cost(4, 2).
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srawi GPR:wo, GPR:ro, CONST:ro cost(4, 2).
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srw GPR:wo, GPR:ro, GPR:ro.
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stb GPR:ro, IND_RC_B:rw cost(4, 3).
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stb GPR:ro, IND_RC_B+IND_RL_B:rw cost(4, 3).
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stbx GPR:ro, GPR:ro, GPR:ro cost(4, 3).
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stfd FPR:ro, IND_RC_D:rw cost(4, 4).
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stfd FPR:ro, IND_RC_D+IND_RL_D:rw cost(4, 4).
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stfdu FPR:ro, IND_RC_D:rw cost(4, 4).
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stfdx FPR:ro, GPR:ro, GPR:ro cost(4, 4).
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stfs FSREG:ro, IND_RC_W+IND_RL_W:rw cost(4, 3).
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stfsu FSREG:ro, IND_RC_W:rw cost(4, 3).
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stfsx FSREG:ro, GPR:ro, GPR:ro cost(4, 3).
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sth GPR:ro, IND_RC_H:rw cost(4, 3).
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sth GPR:ro, IND_RC_H+IND_RL_H:rw cost(4, 3).
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sthx GPR:ro, GPR:ro, GPR:ro cost(4, 3).
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stw GPR:ro, IND_RC_W+IND_RL_W:rw cost(4, 3).
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stwx GPR:ro, GPR:ro, GPR:ro cost(4, 3).
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@ -440,7 +444,7 @@ MOVES
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/* Read byte */
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from IND_RC_B to GPR
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from IND_RC_B+IND_RL_B to GPR
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gen lbz %2, %1
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from IND_RR_B to GPR
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@ -448,7 +452,7 @@ MOVES
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/* Write byte */
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from GPR to IND_RC_B
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from GPR to IND_RC_B+IND_RL_B
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gen stb %1, %2
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from GPR to IND_RR_B
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@ -456,13 +460,13 @@ MOVES
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/* Read halfword (short) */
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from IND_RC_H to GPR
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from IND_RC_H+IND_RL_H to GPR
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gen lhz %2, %1
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from IND_RR_H to GPR
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gen lhzx %2, %1.reg1, %1.reg2
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from IND_RC_H_S to GPR
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from IND_RC_H_S+IND_RL_H_S to GPR
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gen lha %2, %1
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from IND_RR_H_S to GPR
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@ -470,7 +474,7 @@ MOVES
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/* Write halfword */
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from GPR to IND_RC_H
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from GPR to IND_RC_H+IND_RL_H
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gen sth %1, %2
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from GPR to IND_RR_H
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@ -478,19 +482,13 @@ MOVES
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/* Read word */
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from IND_RC_W to GPR
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gen lwz %2, %1
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from IND_RL_W to GPR
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from IND_RC_W+IND_RL_W to GPR
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gen lwz %2, %1
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from IND_RR_W to GPR
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gen lwzx %2, %1.reg1, %1.reg2
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from IND_RC_W to FSREG
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gen lfs %2, %1
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from IND_RL_W to FSREG
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from IND_RC_W+IND_RL_W to FSREG
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gen lfs %2, %1
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from IND_RR_W to FSREG
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@ -498,19 +496,13 @@ MOVES
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/* Write word */
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from GPR to IND_RC_W
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gen stw %1, %2
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from GPR to IND_RL_W
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from GPR to IND_RC_W+IND_RL_W
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gen stw %1, %2
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from GPR to IND_RR_W
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gen stwx %1, %2.reg1, %2.reg2
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from FSREG to IND_RC_W
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gen stfs %1, %2
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from FSREG to IND_RL_W
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from FSREG to IND_RC_W+IND_RL_W
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gen stfs %1, %2
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from FSREG to IND_RR_W
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@ -518,16 +510,16 @@ MOVES
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/* Read double */
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from IND_RC_D to FPR
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gen lfd %2, {IND_RC_D, %1.reg, %1.off}
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from IND_RC_D+IND_RL_D to FPR
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gen lfd %2, %1
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from IND_RR_D to FPR
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gen lfdx %2, %1.reg1, %1.reg2
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/* Write double */
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from FPR to IND_RC_D
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gen stfd %1, {IND_RC_D, %2.reg, %2.off}
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from FPR to IND_RC_D+IND_RL_D
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gen stfd %1, %2
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from FPR to IND_RR_D
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gen stfdx %1, %2.reg1, %2.reg2
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@ -1018,6 +1010,8 @@ PATTERNS
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yields {IND_RC_B, %1, 0}
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with exact SUM_RC
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yields {IND_RC_B, %1.reg, %1.off}
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with exact SUM_RL
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yields {IND_RL_B, %1.reg, %1.adr}
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with exact SUM_RR
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yields {IND_RR_B, %1.reg1, %1.reg2}
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@ -1027,6 +1021,8 @@ PATTERNS
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yields {IND_RC_H_S, %1, 0}
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with exact SUM_RC
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yields {IND_RC_H_S, %1.reg, %1.off}
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with exact SUM_RL
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yields {IND_RL_H_S, %1.reg, %1.adr}
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with exact SUM_RR
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yields {IND_RR_H_S, %1.reg1, %1.reg2}
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@ -1035,6 +1031,8 @@ PATTERNS
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yields {IND_RC_H, %1, 0}
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with exact SUM_RC
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yields {IND_RC_H, %1.reg, %1.off}
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with exact SUM_RL
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yields {IND_RL_H, %1.reg, %1.adr}
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with exact SUM_RR
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yields {IND_RR_H, %1.reg1, %1.reg2}
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@ -1053,6 +1051,8 @@ PATTERNS
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yields {IND_RC_D, %1, 0}
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with exact SUM_RC
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yields {IND_RC_D, %1.reg, %1.off}
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with exact SUM_RL
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yields {IND_RL_D, %1.reg, %1.adr}
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with exact SUM_RR
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yields {IND_RR_D, %1.reg1, %1.reg2}
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@ -1074,6 +1074,9 @@ PATTERNS
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with SUM_RC REG
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kills MEMORY
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gen move %2, {IND_RC_B, %1.reg, %1.off}
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with SUM_RL REG
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kills MEMORY
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gen move %2, {IND_RL_B, %1.reg, %1.adr}
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with SUM_RR REG
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kills MEMORY
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gen move %2, {IND_RR_B, %1.reg1, %1.reg2}
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@ -1085,6 +1088,9 @@ PATTERNS
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with SUM_RC REG
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kills MEMORY
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gen move %2, {IND_RC_H, %1.reg, %1.off}
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with SUM_RL REG
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kills MEMORY
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gen move %2, {IND_RL_H, %1.reg, %1.adr}
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with SUM_RR REG
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kills MEMORY
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gen move %2, {IND_RR_H, %1.reg1, %1.reg2}
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@ -1110,6 +1116,9 @@ PATTERNS
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with SUM_RC FREG
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kills MEMORY
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gen move %2, {IND_RC_D, %1.reg, %1.off}
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with SUM_RL FREG
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kills MEMORY
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gen move %2, {IND_RL_D, %1.reg, %1.adr}
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with SUM_RR FREG
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kills MEMORY
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gen move %2, {IND_RR_D, %1.reg1, %1.reg2}
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