From 9bb69bbb9890c104a8cbd803cc487c0f0bfd1ff5 Mon Sep 17 00:00:00 2001 From: carl Date: Tue, 14 May 2019 23:21:19 +0800 Subject: [PATCH] Fix several compiler warnings by adding braces --- mach/6500/as/mach3.c | 126 ++--- mach/6800/as/mach3.c | 218 ++++---- mach/6805/as/mach3.c | 174 +++--- mach/6809/as/mach3.c | 320 +++++------ mach/arm/as/mach3.c | 204 +++---- mach/i386/as/mach3.c | 796 +++++++++++++------------- mach/i80/as/mach3.c | 202 +++---- mach/i86/as/mach3.c | 628 ++++++++++----------- mach/m68020/as/mach3.c | 782 +++++++++++++------------- mach/m68k2/as/mach3.c | 662 +++++++++++----------- mach/ns/as/mach3.c | 824 +++++++++++++-------------- mach/pdp/as/mach3.c | 292 +++++----- mach/powerpc/as/mach3.c | 1174 +++++++++++++++++++-------------------- mach/proto/as/comm3.c | 46 +- mach/s2650/as/mach3.c | 170 +++--- mach/vax4/as/mach3.c | 742 ++++++++++++------------- mach/vc4/as/mach3.c | 254 ++++----- mach/z80/as/mach3.c | 184 +++--- mach/z8000/as/mach3.c | 552 +++++++++--------- 19 files changed, 4175 insertions(+), 4175 deletions(-) diff --git a/mach/6500/as/mach3.c b/mach/6500/as/mach3.c index e235b80ac..ab8d90ff7 100644 --- a/mach/6500/as/mach3.c +++ b/mach/6500/as/mach3.c @@ -8,66 +8,66 @@ * Mostek 6500 keywords */ -0, EXTENSION, 0, ".l", -0, EXTENSION, 8, ".h", -0, A, 0, "a", -0, X, 0, "x", -0, Y, 0, "y", -0, ADDOP, 0x60, "adc", -0, ADDOP, 0x20, "and", -0, ADDOP, 0xC0, "cmp", -0, ADDOP, 0x40, "eor", -0, ADDOP, 0xA0, "lda", -0, ADDOP, 0x00, "ora", -0, ADDOP, 0xE0, "sbc", -0, ADDOP, 0x80, "sta", -0, ROLOP, 0x00, "asl", -0, ROLOP, 0x40, "lsr", -0, ROLOP, 0x20, "rol", -0, ROLOP, 0x60, "ror", -0, BRAOP, 0x90, "bcc", -0, BRAOP, 0xB0, "bcs", -0, BRAOP, 0xF0, "beq", -0, BRAOP, 0x30, "bmi", -0, BRAOP, 0xD0, "bne", -0, BRAOP, 0x10, "bpl", -0, BRAOP, 0x50, "bvc", -0, BRAOP, 0x70, "bvs", -0, BITOP, 0x24, "bit", -0, NOPOP, 0x00, "brk", -0, NOPOP, 0x18, "clc", -0, NOPOP, 0xD8, "cld", -0, NOPOP, 0x58, "cli", -0, NOPOP, 0xB8, "clv", -0, NOPOP, 0xCA, "dex", -0, NOPOP, 0x88, "dey", -0, NOPOP, 0xE8, "inx", -0, NOPOP, 0xC8, "iny", -0, NOPOP, 0xEA, "nop", -0, NOPOP, 0x48, "pha", -0, NOPOP, 0x08, "php", -0, NOPOP, 0x68, "pla", -0, NOPOP, 0x28, "plp", -0, NOPOP, 0x40, "rti", -0, NOPOP, 0x60, "rts", -0, NOPOP, 0x38, "sec", -0, NOPOP, 0xF8, "sed", -0, NOPOP, 0x78, "sei", -0, NOPOP, 0xAA, "tax", -0, NOPOP, 0xA8, "tay", -0, NOPOP, 0x98, "tya", -0, NOPOP, 0xBA, "tsx", -0, NOPOP, 0x8A, "txa", -0, NOPOP, 0x9A, "txs", -0, CPXOP, 0xE0, "cpx", -0, CPXOP, 0xC0, "cpy", -0, INCOP, 0xC0, "dec", -0, INCOP, 0xE0, "inc", -0, JMPOP, 0x4C, "jmp", -0, JSROP, 0x20, "jsr", -0, LDXOP, 0xA0, "ldx", -0, LDYOP, 0xA0, "ldy", -0, STXOP, 0x80, "stx", -0, STYOP, 0x80, "sty", -0, PSEU, 0x1860, "add", -0, PSEU, 0x38E0, "sub", +{0, EXTENSION, 0, ".l"}, +{0, EXTENSION, 8, ".h"}, +{0, A, 0, "a"}, +{0, X, 0, "x"}, +{0, Y, 0, "y"}, +{0, ADDOP, 0x60, "adc"}, +{0, ADDOP, 0x20, "and"}, +{0, ADDOP, 0xC0, "cmp"}, +{0, ADDOP, 0x40, "eor"}, +{0, ADDOP, 0xA0, "lda"}, +{0, ADDOP, 0x00, "ora"}, +{0, ADDOP, 0xE0, "sbc"}, +{0, ADDOP, 0x80, "sta"}, +{0, ROLOP, 0x00, "asl"}, +{0, ROLOP, 0x40, "lsr"}, +{0, ROLOP, 0x20, "rol"}, +{0, ROLOP, 0x60, "ror"}, +{0, BRAOP, 0x90, "bcc"}, +{0, BRAOP, 0xB0, "bcs"}, +{0, BRAOP, 0xF0, "beq"}, +{0, BRAOP, 0x30, "bmi"}, +{0, BRAOP, 0xD0, "bne"}, +{0, BRAOP, 0x10, "bpl"}, +{0, BRAOP, 0x50, "bvc"}, +{0, BRAOP, 0x70, "bvs"}, +{0, BITOP, 0x24, "bit"}, +{0, NOPOP, 0x00, "brk"}, +{0, NOPOP, 0x18, "clc"}, +{0, NOPOP, 0xD8, "cld"}, +{0, NOPOP, 0x58, "cli"}, +{0, NOPOP, 0xB8, "clv"}, +{0, NOPOP, 0xCA, "dex"}, +{0, NOPOP, 0x88, "dey"}, +{0, NOPOP, 0xE8, "inx"}, +{0, NOPOP, 0xC8, "iny"}, +{0, NOPOP, 0xEA, "nop"}, +{0, NOPOP, 0x48, "pha"}, +{0, NOPOP, 0x08, "php"}, +{0, NOPOP, 0x68, "pla"}, +{0, NOPOP, 0x28, "plp"}, +{0, NOPOP, 0x40, "rti"}, +{0, NOPOP, 0x60, "rts"}, +{0, NOPOP, 0x38, "sec"}, +{0, NOPOP, 0xF8, "sed"}, +{0, NOPOP, 0x78, "sei"}, +{0, NOPOP, 0xAA, "tax"}, +{0, NOPOP, 0xA8, "tay"}, +{0, NOPOP, 0x98, "tya"}, +{0, NOPOP, 0xBA, "tsx"}, +{0, NOPOP, 0x8A, "txa"}, +{0, NOPOP, 0x9A, "txs"}, +{0, CPXOP, 0xE0, "cpx"}, +{0, CPXOP, 0xC0, "cpy"}, +{0, INCOP, 0xC0, "dec"}, +{0, INCOP, 0xE0, "inc"}, +{0, JMPOP, 0x4C, "jmp"}, +{0, JSROP, 0x20, "jsr"}, +{0, LDXOP, 0xA0, "ldx"}, +{0, LDYOP, 0xA0, "ldy"}, +{0, STXOP, 0x80, "stx"}, +{0, STYOP, 0x80, "sty"}, +{0, PSEU, 0x1860, "add"}, +{0, PSEU, 0x38E0, "sub"}, diff --git a/mach/6800/as/mach3.c b/mach/6800/as/mach3.c index 390d08ebc..eddf26d83 100644 --- a/mach/6800/as/mach3.c +++ b/mach/6800/as/mach3.c @@ -7,112 +7,112 @@ /* * Motorola 6800 keywords */ -0, X, 0, "x", -0, BRANCH, 0x20, "bra", -0, BRANCH, 0x22, "bhi", -0, BRANCH, 0x23, "bls", -0, BRANCH, 0x24, "bhs", /* bcc */ -0, BRANCH, 0x24, "bcc", -0, BRANCH, 0x25, "blo", /* bcs */ -0, BRANCH, 0x25, "bcs", -0, BRANCH, 0x26, "bne", -0, BRANCH, 0x27, "beq", -0, BRANCH, 0x28, "bvc", -0, BRANCH, 0x29, "bvs", -0, BRANCH, 0x2A, "bpl", -0, BRANCH, 0x2B, "bmi", -0, BRANCH, 0x2C, "bge", -0, BRANCH, 0x2D, "blt", -0, BRANCH, 0x2E, "bgt", -0, BRANCH, 0x2F, "ble", -0, BRANCH, 0x8D, "bsr", -0, XOP, 0xA0, "suba", -0, XOP, 0xA1, "cmpa", -0, XOP, 0xA2, "sbca", -0, XOP, 0xA4, "anda", -0, XOP, 0xA5, "bita", -0, XOP, 0xA6, "ldaa", -0, XOP, 0xA8, "eora", -0, XOP, 0xA9, "adca", -0, XOP, 0xAA, "oraa", -0, XOP, 0xAB, "adda", -0, XOP, 0xE0, "subb", -0, XOP, 0xE1, "cmpb", -0, XOP, 0xE2, "sbcb", -0, XOP, 0xE4, "andb", -0, XOP, 0xE5, "bitb", -0, XOP, 0xE6, "ldab", -0, XOP, 0xE8, "eorb", -0, XOP, 0xE9, "adcb", -0, XOP, 0xEA, "orab", -0, XOP, 0xEB, "addb", -0, AOP, 0x60, "neg", -0, NOARG, 0x40, "nega", -0, NOARG, 0x50, "negb", -0, AOP, 0x63, "com", -0, NOARG, 0x43, "coma", -0, NOARG, 0x53, "comb", -0, AOP, 0x64, "lsr", -0, NOARG, 0x44, "lsra", -0, NOARG, 0x54, "lsrb", -0, AOP, 0x66, "ror", -0, NOARG, 0x46, "rora", -0, NOARG, 0x56, "rorb", -0, AOP, 0x67, "asr", -0, NOARG, 0x47, "asra", -0, NOARG, 0x57, "asrb", -0, AOP, 0x68, "asl", -0, NOARG, 0x48, "asla", -0, NOARG, 0x58, "aslb", -0, AOP, 0x68, "lsl", -0, NOARG, 0x48, "lsla", -0, NOARG, 0x58, "lslb", -0, AOP, 0x69, "rol", -0, NOARG, 0x49, "rola", -0, NOARG, 0x59, "rolb", -0, AOP, 0x6A, "dec", -0, NOARG, 0x4A, "deca", -0, NOARG, 0x5A, "decb", -0, AOP, 0x6C, "inc", -0, NOARG, 0x4C, "inca", -0, NOARG, 0x5C, "incb", -0, AOP, 0x6D, "tst", -0, NOARG, 0x4D, "tsta", -0, NOARG, 0x5D, "tstb", -0, AOP, 0x6F, "clr", -0, NOARG, 0x4F, "clra", -0, NOARG, 0x5F, "clrb", -0, XOP, 0x6E, "jmp", -0, XOP, 0xAD, "jsr", -0, XOP, 0xAC, "cpx", -0, XOP, 0xAE, "ldx", -0, XOP, 0xEE, "lds", -0, XOP, 0xA7, "sta", -0, XOP, 0xE7, "stb", -0, XOP, 0xAF, "stx", -0, XOP, 0xEF, "sts", -0, NOARG, 0x19, "daa", -0, NOARG, 0x01, "nop", -0, NOARG, 0x3B, "rti", -0, NOARG, 0x39, "rts", -0, NOARG, 0x3F, "swi", -0, NOARG, 0x0C, "clc", -0, NOARG, 0x0D, "sec", -0, NOARG, 0x0E, "cli", -0, NOARG, 0x0F, "sei", -0, NOARG, 0x0A, "clv", -0, NOARG, 0x0B, "sev", -0, NOARG, 0x3E, "wai", -0, NOARG, 0x06, "tap", -0, NOARG, 0x07, "tpa", -0, NOARG, 0x1B, "aba", -0, NOARG, 0x11, "cba", -0, NOARG, 0x10, "sba", -0, NOARG, 0x16, "tab", -0, NOARG, 0x17, "tba", -0, NOARG, 0x09, "dex", -0, NOARG, 0x08, "inx", -0, NOARG, 0x34, "des", -0, NOARG, 0x31, "ins", -0, NOARG, 0x35, "txs", -0, NOARG, 0x30, "tsx", +{0, X, 0, "x"}, +{0, BRANCH, 0x20, "bra"}, +{0, BRANCH, 0x22, "bhi"}, +{0, BRANCH, 0x23, "bls"}, +{0, BRANCH, 0x24, "bhs"}, /* bcc */ +{0, BRANCH, 0x24, "bcc"}, +{0, BRANCH, 0x25, "blo"}, /* bcs */ +{0, BRANCH, 0x25, "bcs"}, +{0, BRANCH, 0x26, "bne"}, +{0, BRANCH, 0x27, "beq"}, +{0, BRANCH, 0x28, "bvc"}, +{0, BRANCH, 0x29, "bvs"}, +{0, BRANCH, 0x2A, "bpl"}, +{0, BRANCH, 0x2B, "bmi"}, +{0, BRANCH, 0x2C, "bge"}, +{0, BRANCH, 0x2D, "blt"}, +{0, BRANCH, 0x2E, "bgt"}, +{0, BRANCH, 0x2F, "ble"}, +{0, BRANCH, 0x8D, "bsr"}, +{0, XOP, 0xA0, "suba"}, +{0, XOP, 0xA1, "cmpa"}, +{0, XOP, 0xA2, "sbca"}, +{0, XOP, 0xA4, "anda"}, +{0, XOP, 0xA5, "bita"}, +{0, XOP, 0xA6, "ldaa"}, +{0, XOP, 0xA8, "eora"}, +{0, XOP, 0xA9, "adca"}, +{0, XOP, 0xAA, "oraa"}, +{0, XOP, 0xAB, "adda"}, +{0, XOP, 0xE0, "subb"}, +{0, XOP, 0xE1, "cmpb"}, +{0, XOP, 0xE2, "sbcb"}, +{0, XOP, 0xE4, "andb"}, +{0, XOP, 0xE5, "bitb"}, +{0, XOP, 0xE6, "ldab"}, +{0, XOP, 0xE8, "eorb"}, +{0, XOP, 0xE9, "adcb"}, +{0, XOP, 0xEA, "orab"}, +{0, XOP, 0xEB, "addb"}, +{0, AOP, 0x60, "neg"}, +{0, NOARG, 0x40, "nega"}, +{0, NOARG, 0x50, "negb"}, +{0, AOP, 0x63, "com"}, +{0, NOARG, 0x43, "coma"}, +{0, NOARG, 0x53, "comb"}, +{0, AOP, 0x64, "lsr"}, +{0, NOARG, 0x44, "lsra"}, +{0, NOARG, 0x54, "lsrb"}, +{0, AOP, 0x66, "ror"}, +{0, NOARG, 0x46, "rora"}, +{0, NOARG, 0x56, "rorb"}, +{0, AOP, 0x67, "asr"}, +{0, NOARG, 0x47, "asra"}, +{0, NOARG, 0x57, "asrb"}, +{0, AOP, 0x68, "asl"}, +{0, NOARG, 0x48, "asla"}, +{0, NOARG, 0x58, "aslb"}, +{0, AOP, 0x68, "lsl"}, +{0, NOARG, 0x48, "lsla"}, +{0, NOARG, 0x58, "lslb"}, +{0, AOP, 0x69, "rol"}, +{0, NOARG, 0x49, "rola"}, +{0, NOARG, 0x59, "rolb"}, +{0, AOP, 0x6A, "dec"}, +{0, NOARG, 0x4A, "deca"}, +{0, NOARG, 0x5A, "decb"}, +{0, AOP, 0x6C, "inc"}, +{0, NOARG, 0x4C, "inca"}, +{0, NOARG, 0x5C, "incb"}, +{0, AOP, 0x6D, "tst"}, +{0, NOARG, 0x4D, "tsta"}, +{0, NOARG, 0x5D, "tstb"}, +{0, AOP, 0x6F, "clr"}, +{0, NOARG, 0x4F, "clra"}, +{0, NOARG, 0x5F, "clrb"}, +{0, XOP, 0x6E, "jmp"}, +{0, XOP, 0xAD, "jsr"}, +{0, XOP, 0xAC, "cpx"}, +{0, XOP, 0xAE, "ldx"}, +{0, XOP, 0xEE, "lds"}, +{0, XOP, 0xA7, "sta"}, +{0, XOP, 0xE7, "stb"}, +{0, XOP, 0xAF, "stx"}, +{0, XOP, 0xEF, "sts"}, +{0, NOARG, 0x19, "daa"}, +{0, NOARG, 0x01, "nop"}, +{0, NOARG, 0x3B, "rti"}, +{0, NOARG, 0x39, "rts"}, +{0, NOARG, 0x3F, "swi"}, +{0, NOARG, 0x0C, "clc"}, +{0, NOARG, 0x0D, "sec"}, +{0, NOARG, 0x0E, "cli"}, +{0, NOARG, 0x0F, "sei"}, +{0, NOARG, 0x0A, "clv"}, +{0, NOARG, 0x0B, "sev"}, +{0, NOARG, 0x3E, "wai"}, +{0, NOARG, 0x06, "tap"}, +{0, NOARG, 0x07, "tpa"}, +{0, NOARG, 0x1B, "aba"}, +{0, NOARG, 0x11, "cba"}, +{0, NOARG, 0x10, "sba"}, +{0, NOARG, 0x16, "tab"}, +{0, NOARG, 0x17, "tba"}, +{0, NOARG, 0x09, "dex"}, +{0, NOARG, 0x08, "inx"}, +{0, NOARG, 0x34, "des"}, +{0, NOARG, 0x31, "ins"}, +{0, NOARG, 0x35, "txs"}, +{0, NOARG, 0x30, "tsx"}, diff --git a/mach/6805/as/mach3.c b/mach/6805/as/mach3.c index 2d9d57cf8..d254105e8 100644 --- a/mach/6805/as/mach3.c +++ b/mach/6805/as/mach3.c @@ -10,118 +10,118 @@ /* * The X register */ -0, X, 0, "x", +{0, X, 0, "x"}, /* * Bit test and branch */ -0, BBRANCH, 0x00, "brset", -0, BBRANCH, 0x01, "brclr", +{0, BBRANCH, 0x00, "brset"}, +{0, BBRANCH, 0x01, "brclr"}, /* * Bit manipulation */ -0, BIT, 0x10, "bset", -0, BIT, 0x11, "bclr", +{0, BIT, 0x10, "bset"}, +{0, BIT, 0x11, "bclr"}, /* * Branches */ -0, BRANCH, 0x20, "bra", -0, BRANCH, 0x21, "brn", -0, BRANCH, 0x22, "bhi", -0, BRANCH, 0x23, "bls", -0, BRANCH, 0x24, "bcc", -0, BRANCH, 0x25, "bcs", -0, BRANCH, 0x26, "bne", -0, BRANCH, 0x27, "beq", -0, BRANCH, 0x28, "bhcc", -0, BRANCH, 0x29, "bhcs", -0, BRANCH, 0x2a, "bpl", -0, BRANCH, 0x2b, "bmi", -0, BRANCH, 0x2c, "bmc", -0, BRANCH, 0x2d, "bms", -0, BRANCH, 0x2e, "bil", -0, BRANCH, 0x2f, "bih", +{0, BRANCH, 0x20, "bra"}, +{0, BRANCH, 0x21, "brn"}, +{0, BRANCH, 0x22, "bhi"}, +{0, BRANCH, 0x23, "bls"}, +{0, BRANCH, 0x24, "bcc"}, +{0, BRANCH, 0x25, "bcs"}, +{0, BRANCH, 0x26, "bne"}, +{0, BRANCH, 0x27, "beq"}, +{0, BRANCH, 0x28, "bhcc"}, +{0, BRANCH, 0x29, "bhcs"}, +{0, BRANCH, 0x2a, "bpl"}, +{0, BRANCH, 0x2b, "bmi"}, +{0, BRANCH, 0x2c, "bmc"}, +{0, BRANCH, 0x2d, "bms"}, +{0, BRANCH, 0x2e, "bil"}, +{0, BRANCH, 0x2f, "bih"}, /* * Read modify write on anything but registers */ -0, RMR, 0x30, "neg", -0, RMR, 0x33, "com", -0, RMR, 0x34, "lsr", -0, RMR, 0x36, "ror", -0, RMR, 0x36, "asr", -0, RMR, 0x38, "lsl", -0, RMR, 0x39, "rol", -0, RMR, 0x3a, "dec", -0, RMR, 0x3c, "inc", -0, RMR, 0x3d, "tst", -0, RMR, 0x3f, "clr", +{0, RMR, 0x30, "neg"}, +{0, RMR, 0x33, "com"}, +{0, RMR, 0x34, "lsr"}, +{0, RMR, 0x36, "ror"}, +{0, RMR, 0x36, "asr"}, +{0, RMR, 0x38, "lsl"}, +{0, RMR, 0x39, "rol"}, +{0, RMR, 0x3a, "dec"}, +{0, RMR, 0x3c, "inc"}, +{0, RMR, 0x3d, "tst"}, +{0, RMR, 0x3f, "clr"}, /* * Implied stuff */ -0, NOARG, 0x80, "rti", -0, NOARG, 0x81, "rts", -0, NOARG, 0x83, "swi", -0, NOARG, 0x97, "tax", -0, NOARG, 0x98, "clc", -0, NOARG, 0x99, "sec", -0, NOARG, 0x9a, "cli", -0, NOARG, 0x9b, "sei", -0, NOARG, 0x9c, "rsp", -0, NOARG, 0x9d, "nop", -0, NOARG, 0x9f, "txa", +{0, NOARG, 0x80, "rti"}, +{0, NOARG, 0x81, "rts"}, +{0, NOARG, 0x83, "swi"}, +{0, NOARG, 0x97, "tax"}, +{0, NOARG, 0x98, "clc"}, +{0, NOARG, 0x99, "sec"}, +{0, NOARG, 0x9a, "cli"}, +{0, NOARG, 0x9b, "sei"}, +{0, NOARG, 0x9c, "rsp"}, +{0, NOARG, 0x9d, "nop"}, +{0, NOARG, 0x9f, "txa"}, /* * Register memory. * Warning. Some imediate opcodes excluded in parser actions. */ -0, RM, 0xa0, "sub", -0, RM, 0xa1, "cmp", -0, RM, 0xa2, "sbc", -0, RM, 0xa3, "cpx", -0, RM, 0xa4, "and", -0, RM, 0xa5, "bit", -0, RM, 0xa6, "lda", -0, RM, 0xa7, "sta", -0, RM, 0xa8, "eor", -0, RM, 0xa9, "adc", -0, RM, 0xaa, "ora", -0, RM, 0xab, "add", -0, RM, 0xac, "jmp", -0, BRANCH, 0xad, "bsr", -0, RM, 0xad, "jsr", -0, RM, 0xae, "ldx", -0, RM, 0xaf, "stx", +{0, RM, 0xa0, "sub"}, +{0, RM, 0xa1, "cmp"}, +{0, RM, 0xa2, "sbc"}, +{0, RM, 0xa3, "cpx"}, +{0, RM, 0xa4, "and"}, +{0, RM, 0xa5, "bit"}, +{0, RM, 0xa6, "lda"}, +{0, RM, 0xa7, "sta"}, +{0, RM, 0xa8, "eor"}, +{0, RM, 0xa9, "adc"}, +{0, RM, 0xaa, "ora"}, +{0, RM, 0xab, "add"}, +{0, RM, 0xac, "jmp"}, +{0, BRANCH, 0xad, "bsr"}, +{0, RM, 0xad, "jsr"}, +{0, RM, 0xae, "ldx"}, +{0, RM, 0xaf, "stx"}, /* * Branch synonyms */ -0, BRANCH, 0x24, "bhs", /* bcc */ -0, BRANCH, 0x25, "blo", /* bcs */ +{0, BRANCH, 0x24, "bhs"}, /* bcc */ +{0, BRANCH, 0x25, "blo"}, /* bcs */ /* * Brain damaged concatenated opcodes for RMR on registers */ -0, NOARG, 0x40, "nega", -0, NOARG, 0x43, "coma", -0, NOARG, 0x44, "lsra", -0, NOARG, 0x46, "rora", -0, NOARG, 0x47, "asra", -0, NOARG, 0x48, "lsla", -0, NOARG, 0x49, "rola", -0, NOARG, 0x4a, "deca", -0, NOARG, 0x4c, "inca", -0, NOARG, 0x4d, "tsta", -0, NOARG, 0x4f, "clra", -0, NOARG, 0x50, "negx", -0, NOARG, 0x53, "comx", -0, NOARG, 0x54, "lsrx", -0, NOARG, 0x56, "rorx", -0, NOARG, 0x57, "asrx", -0, NOARG, 0x58, "lslx", -0, NOARG, 0x59, "rolx", -0, NOARG, 0x5a, "decx", -0, NOARG, 0x5c, "incx", -0, NOARG, 0x5d, "tstx", -0, NOARG, 0x5f, "clrx", +{0, NOARG, 0x40, "nega"}, +{0, NOARG, 0x43, "coma"}, +{0, NOARG, 0x44, "lsra"}, +{0, NOARG, 0x46, "rora"}, +{0, NOARG, 0x47, "asra"}, +{0, NOARG, 0x48, "lsla"}, +{0, NOARG, 0x49, "rola"}, +{0, NOARG, 0x4a, "deca"}, +{0, NOARG, 0x4c, "inca"}, +{0, NOARG, 0x4d, "tsta"}, +{0, NOARG, 0x4f, "clra"}, +{0, NOARG, 0x50, "negx"}, +{0, NOARG, 0x53, "comx"}, +{0, NOARG, 0x54, "lsrx"}, +{0, NOARG, 0x56, "rorx"}, +{0, NOARG, 0x57, "asrx"}, +{0, NOARG, 0x58, "lslx"}, +{0, NOARG, 0x59, "rolx"}, +{0, NOARG, 0x5a, "decx"}, +{0, NOARG, 0x5c, "incx"}, +{0, NOARG, 0x5d, "tstx"}, +{0, NOARG, 0x5f, "clrx"}, /* * CMOS support */ -0, CMOS, 0, ".cmos", -0, CMOS, 0x8e, "stop", -0, CMOS, 0x8f, "wait", +{0, CMOS, 0, ".cmos"}, +{0, CMOS, 0x8e, "stop"}, +{0, CMOS, 0x8f, "wait"}, diff --git a/mach/6809/as/mach3.c b/mach/6809/as/mach3.c index f7a8fb922..a349f9f68 100644 --- a/mach/6809/as/mach3.c +++ b/mach/6809/as/mach3.c @@ -8,163 +8,163 @@ * Motorola 6809 keywords */ -0, REG, A, "a", -0, REG, B, "b", -0, REG, CC, "cc", -0, REG, DP, "dp", -0, REG, D, "d", -0, REG, X, "x", -0, REG, Y, "y", -0, REG, U, "u", -0, REG, S, "s", -0, REG, PC, "pc", -0, ALL, 0xFF, "all", -0, SETDP, 0, "setdp", -0, NOARG, 0x3A, "abx", -0, NOARG, 0x19, "daa", -0, NOARG, 0x3D, "mul", -0, NOARG, 0x12, "nop", -0, NOARG, 0x10, "page2", -0, NOARG, 0x11, "page3", -0, NOARG, 0x3B, "rti", -0, NOARG, 0x4F, "clra", -0, NOARG, 0x5F, "clrb", -0, NOARG, 0x4A, "deca", -0, NOARG, 0x5A, "decb", -0, NOARG, 0x43, "coma", -0, NOARG, 0x53, "comb", -0, NOARG, 0x44, "lsra", -0, NOARG, 0x54, "lsrb", -0, NOARG, 0x40, "nega", -0, NOARG, 0x50, "negb", -0, NOARG, 0x46, "rora", -0, NOARG, 0x56, "rorb", -0, NOARG, 0x47, "asra", -0, NOARG, 0x57, "asrb", -0, NOARG, 0x49, "rola", -0, NOARG, 0x59, "rolb", -0, NOARG, 0x48, "asla", -0, NOARG, 0x58, "aslb", -0, NOARG, 0x48, "lsla", -0, NOARG, 0x58, "lslb", -0, NOARG, 0x4C, "inca", -0, NOARG, 0x5C, "incb", -0, NOARG, 0x4D, "tsta", -0, NOARG, 0x5D, "tstb", -0, NOARG, 0x39, "rts", -0, NOARG, 0x1D, "sex", -0, NOARG, 0x3F, "swi", -0, NOARG, 0x103F, "swi2", -0, NOARG, 0x113F, "swi3", -0, NOARG, 0x13, "sync", -0, BRANCH, 0x20, "bra", -0, BRANCH, 0x21, "brn", -0, BRANCH, 0x22, "bhi", -0, BRANCH, 0x23, "bls", -0, BRANCH, 0x24, "bhs", -0, BRANCH, 0x24, "bcc", -0, BRANCH, 0x25, "blo", -0, BRANCH, 0x25, "bcs", -0, BRANCH, 0x26, "bne", -0, BRANCH, 0x27, "beq", -0, BRANCH, 0x28, "bvc", -0, BRANCH, 0x29, "bvs", -0, BRANCH, 0x2A, "bpl", -0, BRANCH, 0x2B, "bmi", -0, BRANCH, 0x2C, "bge", -0, BRANCH, 0x2D, "blt", -0, BRANCH, 0x2E, "bgt", -0, BRANCH, 0x2F, "ble", -0, BRANCH, 0x8D, "bsr", -0, STACK, 0x34, "pshs", -0, STACK, 0x35, "puls", -0, STACK, 0x36, "pshu", -0, STACK, 0x37, "pulu", -0, IMMED, 0x1A, "orcc", -0, IMMED, 0x1C, "andcc", -0, IMMED, 0x3C, "cwai", -0, TWOREG, 0x1E, "exg", -0, TWOREG, 0x1F, "tfr", -0, XOP, 0xA0, "suba", -0, XOP, 0xA1, "cmpa", -0, XOP, 0xA2, "sbca", -0, XOP, 0xA4, "anda", -0, XOP, 0xA5, "bita", -0, XOP, 0xA6, "lda", -0, XOP, 0xA8, "eora", -0, XOP, 0xA9, "adca", -0, XOP, 0xAA, "ora", -0, XOP, 0xAB, "adda", -0, XOP, 0xE0, "subb", -0, XOP, 0xE1, "cmpb", -0, XOP, 0xE2, "sbcb", -0, XOP, 0xE4, "andb", -0, XOP, 0xE5, "bitb", -0, XOP, 0xE6, "ldb", -0, XOP, 0xE8, "eorb", -0, XOP, 0xE9, "adcb", -0, XOP, 0xEA, "orb", -0, XOP, 0xEB, "addb", -0, XOP, 0x30, "leax", -0, XOP, 0x31, "leay", -0, XOP, 0x32, "leas", -0, XOP, 0x33, "leau", -0, XOP, 0x60, "neg", -0, XOP, 0x63, "com", -0, XOP, 0x64, "lsr", -0, XOP, 0x66, "ror", -0, XOP, 0x67, "asr", -0, XOP, 0x68, "asl", -0, XOP, 0x68, "lsl", -0, XOP, 0x69, "rol", -0, XOP, 0x6A, "dec", -0, XOP, 0x6C, "inc", -0, XOP, 0x6D, "tst", -0, XOP, 0x6F, "clr", -0, XOP, 0x6E, "jmp", -0, XOP, 0xA3, "subd", -0, XOP, 0x10A3, "cmpd", -0, XOP, 0x11A3, "cmpu", -0, XOP, 0xAC, "cmpx", -0, XOP, 0x10AC, "cmpy", -0, XOP, 0x11AC, "cmps", -0, XOP, 0xAE, "ldx", -0, XOP, 0x10AE, "ldy", -0, XOP, 0xE3, "addd", -0, XOP, 0xEC, "ldd", -0, XOP, 0xEE, "ldu", -0, XOP, 0x10EE, "lds", -0, XOP, 0xA7, "sta", -0, XOP, 0xAD, "jsr", -0, XOP, 0xAF, "stx", -0, XOP, 0x10AF, "sty", -0, XOP, 0xE7, "stb", -0, XOP, 0xED, "std", -0, XOP, 0xEF, "stu", -0, XOP, 0x10EF, "sts", -0, LBRNCH, 0x21, "lbrn", -0, LBRNCH, 0x22, "lbhi", -0, LBRNCH, 0x23, "lbls", -0, LBRNCH, 0x24, "lbhs", -0, LBRNCH, 0x24, "lbcc", -0, LBRNCH, 0x25, "lblo", -0, LBRNCH, 0x25, "lbcs", -0, LBRNCH, 0x26, "lbne", -0, LBRNCH, 0x27, "lbeq", -0, LBRNCH, 0x28, "lbvc", -0, LBRNCH, 0x29, "lbvs", -0, LBRNCH, 0x2A, "lbpl", -0, LBRNCH, 0x2B, "lbmi", -0, LBRNCH, 0x2C, "lbge", -0, LBRNCH, 0x2D, "lblt", -0, LBRNCH, 0x2E, "lbgt", -0, LBRNCH, 0x2F, "lble", -0, SBRNCH, 0x16, "lbra", -0, SBRNCH, 0x17, "lbsr", -0, NOARG, 0x1CFE, "clc", -0, NOARG, 0x1A01, "sec", -0, NOARG, 0x1CEF, "cli", -0, NOARG, 0x1A10, "sei", -0, NOARG, 0x1CFD, "clv", -0, NOARG, 0x1A02, "sev", -0, NOARG, 0x3CFF, "wai", +{0, REG, A, "a"}, +{0, REG, B, "b"}, +{0, REG, CC, "cc"}, +{0, REG, DP, "dp"}, +{0, REG, D, "d"}, +{0, REG, X, "x"}, +{0, REG, Y, "y"}, +{0, REG, U, "u"}, +{0, REG, S, "s"}, +{0, REG, PC, "pc"}, +{0, ALL, 0xFF, "all"}, +{0, SETDP, 0, "setdp"}, +{0, NOARG, 0x3A, "abx"}, +{0, NOARG, 0x19, "daa"}, +{0, NOARG, 0x3D, "mul"}, +{0, NOARG, 0x12, "nop"}, +{0, NOARG, 0x10, "page2"}, +{0, NOARG, 0x11, "page3"}, +{0, NOARG, 0x3B, "rti"}, +{0, NOARG, 0x4F, "clra"}, +{0, NOARG, 0x5F, "clrb"}, +{0, NOARG, 0x4A, "deca"}, +{0, NOARG, 0x5A, "decb"}, +{0, NOARG, 0x43, "coma"}, +{0, NOARG, 0x53, "comb"}, +{0, NOARG, 0x44, "lsra"}, +{0, NOARG, 0x54, "lsrb"}, +{0, NOARG, 0x40, "nega"}, +{0, NOARG, 0x50, "negb"}, +{0, NOARG, 0x46, "rora"}, +{0, NOARG, 0x56, "rorb"}, +{0, NOARG, 0x47, "asra"}, +{0, NOARG, 0x57, "asrb"}, +{0, NOARG, 0x49, "rola"}, +{0, NOARG, 0x59, "rolb"}, +{0, NOARG, 0x48, "asla"}, +{0, NOARG, 0x58, "aslb"}, +{0, NOARG, 0x48, "lsla"}, +{0, NOARG, 0x58, "lslb"}, +{0, NOARG, 0x4C, "inca"}, +{0, NOARG, 0x5C, "incb"}, +{0, NOARG, 0x4D, "tsta"}, +{0, NOARG, 0x5D, "tstb"}, +{0, NOARG, 0x39, "rts"}, +{0, NOARG, 0x1D, "sex"}, +{0, NOARG, 0x3F, "swi"}, +{0, NOARG, 0x103F, "swi2"}, +{0, NOARG, 0x113F, "swi3"}, +{0, NOARG, 0x13, "sync"}, +{0, BRANCH, 0x20, "bra"}, +{0, BRANCH, 0x21, "brn"}, +{0, BRANCH, 0x22, "bhi"}, +{0, BRANCH, 0x23, "bls"}, +{0, BRANCH, 0x24, "bhs"}, +{0, BRANCH, 0x24, "bcc"}, +{0, BRANCH, 0x25, "blo"}, +{0, BRANCH, 0x25, "bcs"}, +{0, BRANCH, 0x26, "bne"}, +{0, BRANCH, 0x27, "beq"}, +{0, BRANCH, 0x28, "bvc"}, +{0, BRANCH, 0x29, "bvs"}, +{0, BRANCH, 0x2A, "bpl"}, +{0, BRANCH, 0x2B, "bmi"}, +{0, BRANCH, 0x2C, "bge"}, +{0, BRANCH, 0x2D, "blt"}, +{0, BRANCH, 0x2E, "bgt"}, +{0, BRANCH, 0x2F, "ble"}, +{0, BRANCH, 0x8D, "bsr"}, +{0, STACK, 0x34, "pshs"}, +{0, STACK, 0x35, "puls"}, +{0, STACK, 0x36, "pshu"}, +{0, STACK, 0x37, "pulu"}, +{0, IMMED, 0x1A, "orcc"}, +{0, IMMED, 0x1C, "andcc"}, +{0, IMMED, 0x3C, "cwai"}, +{0, TWOREG, 0x1E, "exg"}, +{0, TWOREG, 0x1F, "tfr"}, +{0, XOP, 0xA0, "suba"}, +{0, XOP, 0xA1, "cmpa"}, +{0, XOP, 0xA2, "sbca"}, +{0, XOP, 0xA4, "anda"}, +{0, XOP, 0xA5, "bita"}, +{0, XOP, 0xA6, "lda"}, +{0, XOP, 0xA8, "eora"}, +{0, XOP, 0xA9, "adca"}, +{0, XOP, 0xAA, "ora"}, +{0, XOP, 0xAB, "adda"}, +{0, XOP, 0xE0, "subb"}, +{0, XOP, 0xE1, "cmpb"}, +{0, XOP, 0xE2, "sbcb"}, +{0, XOP, 0xE4, "andb"}, +{0, XOP, 0xE5, "bitb"}, +{0, XOP, 0xE6, "ldb"}, +{0, XOP, 0xE8, "eorb"}, +{0, XOP, 0xE9, "adcb"}, +{0, XOP, 0xEA, "orb"}, +{0, XOP, 0xEB, "addb"}, +{0, XOP, 0x30, "leax"}, +{0, XOP, 0x31, "leay"}, +{0, XOP, 0x32, "leas"}, +{0, XOP, 0x33, "leau"}, +{0, XOP, 0x60, "neg"}, +{0, XOP, 0x63, "com"}, +{0, XOP, 0x64, "lsr"}, +{0, XOP, 0x66, "ror"}, +{0, XOP, 0x67, "asr"}, +{0, XOP, 0x68, "asl"}, +{0, XOP, 0x68, "lsl"}, +{0, XOP, 0x69, "rol"}, +{0, XOP, 0x6A, "dec"}, +{0, XOP, 0x6C, "inc"}, +{0, XOP, 0x6D, "tst"}, +{0, XOP, 0x6F, "clr"}, +{0, XOP, 0x6E, "jmp"}, +{0, XOP, 0xA3, "subd"}, +{0, XOP, 0x10A3, "cmpd"}, +{0, XOP, 0x11A3, "cmpu"}, +{0, XOP, 0xAC, "cmpx"}, +{0, XOP, 0x10AC, "cmpy"}, +{0, XOP, 0x11AC, "cmps"}, +{0, XOP, 0xAE, "ldx"}, +{0, XOP, 0x10AE, "ldy"}, +{0, XOP, 0xE3, "addd"}, +{0, XOP, 0xEC, "ldd"}, +{0, XOP, 0xEE, "ldu"}, +{0, XOP, 0x10EE, "lds"}, +{0, XOP, 0xA7, "sta"}, +{0, XOP, 0xAD, "jsr"}, +{0, XOP, 0xAF, "stx"}, +{0, XOP, 0x10AF, "sty"}, +{0, XOP, 0xE7, "stb"}, +{0, XOP, 0xED, "std"}, +{0, XOP, 0xEF, "stu"}, +{0, XOP, 0x10EF, "sts"}, +{0, LBRNCH, 0x21, "lbrn"}, +{0, LBRNCH, 0x22, "lbhi"}, +{0, LBRNCH, 0x23, "lbls"}, +{0, LBRNCH, 0x24, "lbhs"}, +{0, LBRNCH, 0x24, "lbcc"}, +{0, LBRNCH, 0x25, "lblo"}, +{0, LBRNCH, 0x25, "lbcs"}, +{0, LBRNCH, 0x26, "lbne"}, +{0, LBRNCH, 0x27, "lbeq"}, +{0, LBRNCH, 0x28, "lbvc"}, +{0, LBRNCH, 0x29, "lbvs"}, +{0, LBRNCH, 0x2A, "lbpl"}, +{0, LBRNCH, 0x2B, "lbmi"}, +{0, LBRNCH, 0x2C, "lbge"}, +{0, LBRNCH, 0x2D, "lblt"}, +{0, LBRNCH, 0x2E, "lbgt"}, +{0, LBRNCH, 0x2F, "lble"}, +{0, SBRNCH, 0x16, "lbra"}, +{0, SBRNCH, 0x17, "lbsr"}, +{0, NOARG, 0x1CFE, "clc"}, +{0, NOARG, 0x1A01, "sec"}, +{0, NOARG, 0x1CEF, "cli"}, +{0, NOARG, 0x1A10, "sei"}, +{0, NOARG, 0x1CFD, "clv"}, +{0, NOARG, 0x1A02, "sev"}, +{0, NOARG, 0x3CFF, "wai"}, diff --git a/mach/arm/as/mach3.c b/mach/arm/as/mach3.c index a35feb540..9ea286650 100644 --- a/mach/arm/as/mach3.c +++ b/mach/arm/as/mach3.c @@ -1,121 +1,121 @@ /* $Id: mach3.c, v2.0 23-Feb-89 AJM */ -0, COND, 0x00000000, ".EQ", -0, COND, 0x10000000, ".NE", -0, COND, 0x20000000, ".CS", -0, COND, 0x20000000, ".HS", -0, COND, 0x30000000, ".CC", -0, COND, 0x30000000, ".LO", -0, COND, 0x40000000, ".MI", -0, COND, 0x50000000, ".PL", -0, COND, 0x60000000, ".VS", -0, COND, 0x70000000, ".VC", -0, COND, 0x80000000, ".HI", -0, COND, 0x90000000, ".LS", -0, COND, 0xA0000000, ".GE", -0, COND, 0xB0000000, ".LT", -0, COND, 0xC0000000, ".GT", -0, COND, 0xD0000000, ".LE", -0, COND, 0xE0000000, ".AL", -0, COND, 0xF0000000, ".NV", +{0, COND, 0x00000000, ".EQ"}, +{0, COND, 0x10000000, ".NE"}, +{0, COND, 0x20000000, ".CS"}, +{0, COND, 0x20000000, ".HS"}, +{0, COND, 0x30000000, ".CC"}, +{0, COND, 0x30000000, ".LO"}, +{0, COND, 0x40000000, ".MI"}, +{0, COND, 0x50000000, ".PL"}, +{0, COND, 0x60000000, ".VS"}, +{0, COND, 0x70000000, ".VC"}, +{0, COND, 0x80000000, ".HI"}, +{0, COND, 0x90000000, ".LS"}, +{0, COND, 0xA0000000, ".GE"}, +{0, COND, 0xB0000000, ".LT"}, +{0, COND, 0xC0000000, ".GT"}, +{0, COND, 0xD0000000, ".LE"}, +{0, COND, 0xE0000000, ".AL"}, +{0, COND, 0xF0000000, ".NV"}, -0, LINK, 0x01000000, ".L", +{0, LINK, 0x01000000, ".L"}, -0, BRANCH, 0x0A000000, "BEQ", -0, BRANCH, 0x1A000000, "BNE", -0, BRANCH, 0x2A000000, "BCS", -0, BRANCH, 0x2A000000, "BHS", -0, BRANCH, 0x3A000000, "BCC", -0, BRANCH, 0x3A000000, "BLO", -0, BRANCH, 0x4A000000, "BMI", -0, BRANCH, 0x5A000000, "BPL", -0, BRANCH, 0x6A000000, "BVS", -0, BRANCH, 0x7A000000, "BVC", -0, BRANCH, 0x8A000000, "BHI", -0, BRANCH, 0x9A000000, "BLS", -0, BRANCH, 0xAA000000, "BGE", -0, BRANCH, 0xBA000000, "BLT", -0, BRANCH, 0xCA000000, "BGT", -0, BRANCH, 0xDA000000, "BLE", -0, BRANCH, 0xEA000000, "BAL", -0, BRANCH, 0xFA000000, "BNV", +{0, BRANCH, 0x0A000000, "BEQ"}, +{0, BRANCH, 0x1A000000, "BNE"}, +{0, BRANCH, 0x2A000000, "BCS"}, +{0, BRANCH, 0x2A000000, "BHS"}, +{0, BRANCH, 0x3A000000, "BCC"}, +{0, BRANCH, 0x3A000000, "BLO"}, +{0, BRANCH, 0x4A000000, "BMI"}, +{0, BRANCH, 0x5A000000, "BPL"}, +{0, BRANCH, 0x6A000000, "BVS"}, +{0, BRANCH, 0x7A000000, "BVC"}, +{0, BRANCH, 0x8A000000, "BHI"}, +{0, BRANCH, 0x9A000000, "BLS"}, +{0, BRANCH, 0xAA000000, "BGE"}, +{0, BRANCH, 0xBA000000, "BLT"}, +{0, BRANCH, 0xCA000000, "BGT"}, +{0, BRANCH, 0xDA000000, "BLE"}, +{0, BRANCH, 0xEA000000, "BAL"}, +{0, BRANCH, 0xFA000000, "BNV"}, -0, DATA1, ADC, "ADC", -0, DATA1, ADD, "ADD", -0, DATA1, AND, "AND", -0, DATA1, BIC, "BIC", -0, DATA1, EOR, "EOR", -0, DATA1, ORR, "ORR", -0, DATA1, RSB, "RSB", -0, DATA1, RSC, "RSC", -0, DATA1, SBC, "SBC", -0, DATA1, SUB, "SUB", -0, DATA2, MOV, "MOV", -0, DATA2, MVN, "MVN", -0, DATA3, CMN, "CMN", -0, DATA3, CMP, "CMP", -0, DATA3, TEQ, "TEQ", -0, DATA3, TST, "TST", +{0, DATA1, ADC, "ADC"}, +{0, DATA1, ADD, "ADD"}, +{0, DATA1, AND, "AND"}, +{0, DATA1, BIC, "BIC"}, +{0, DATA1, EOR, "EOR"}, +{0, DATA1, ORR, "ORR"}, +{0, DATA1, RSB, "RSB"}, +{0, DATA1, RSC, "RSC"}, +{0, DATA1, SBC, "SBC"}, +{0, DATA1, SUB, "SUB"}, +{0, DATA2, MOV, "MOV"}, +{0, DATA2, MVN, "MVN"}, +{0, DATA3, CMN, "CMN"}, +{0, DATA3, CMP, "CMP"}, +{0, DATA3, TEQ, "TEQ"}, +{0, DATA3, TST, "TST"}, -0, SET, 0x00100000, ".S", +{0, SET, 0x00100000, ".S"}, -0, PEE, 0x0010F000, ".P", +{0, PEE, 0x0010F000, ".P"}, -0, REG, 0, "R0", -0, REG, 1, "R1", -0, REG, 2, "R2", -0, REG, 3, "R3", -0, REG, 4, "R4", -0, REG, 5, "R5", -0, REG, 6, "R6", -0, REG, 7, "R7", -0, REG, 8, "R8", -0, REG, 9, "R9", -0, REG, 10, "R10", -0, REG, 11, "R11", -0, REG, 12, "R12", -0, REG, 13, "R13", -0, REG, 14, "R14", -0, REG, 15, "R15", -0, REG, 15, "PC", +{0, REG, 0, "R0"}, +{0, REG, 1, "R1"}, +{0, REG, 2, "R2"}, +{0, REG, 3, "R3"}, +{0, REG, 4, "R4"}, +{0, REG, 5, "R5"}, +{0, REG, 6, "R6"}, +{0, REG, 7, "R7"}, +{0, REG, 8, "R8"}, +{0, REG, 9, "R9"}, +{0, REG, 10, "R10"}, +{0, REG, 11, "R11"}, +{0, REG, 12, "R12"}, +{0, REG, 13, "R13"}, +{0, REG, 14, "R14"}, +{0, REG, 15, "R15"}, +{0, REG, 15, "PC"}, -0, SHIFT, 0x00000000, "LSL", -0, SHIFT, 0x00000000, "ASL", -0, SHIFT, 0x00000020, "LSR", -0, SHIFT, 0x00000040, "ASR", -0, SHIFT, 0x00000060, "ROR", +{0, SHIFT, 0x00000000, "LSL"}, +{0, SHIFT, 0x00000000, "ASL"}, +{0, SHIFT, 0x00000020, "LSR"}, +{0, SHIFT, 0x00000040, "ASR"}, +{0, SHIFT, 0x00000060, "ROR"}, -0, RRX, 0x00000060, "RRX", +{0, RRX, 0x00000060, "RRX"}, -0, SDT, 0x04100000, "LDR", -0, SDT, 0x04000000, "STR", +{0, SDT, 0x04100000, "LDR"}, +{0, SDT, 0x04000000, "STR"}, -0, BYTE, 0x00400000, ".B", +{0, BYTE, 0x00400000, ".B"}, -0, TRANS, 0x00200000, ".T", +{0, TRANS, 0x00200000, ".T"}, -0, BDT, 0x09100000, "LDMDB", -0, BDT, 0x08100000, "LDMDA", -0, BDT, 0x09900000, "LDMIB", -0, BDT, 0x08900000, "LDMIA", -0, BDT, 0x08900000, "LDMFD", -0, BDT, 0x08100000, "LDMFA", -0, BDT, 0x09900000, "LDMED", -0, BDT, 0x09100000, "LDMEA", -0, BDT, 0x09000000, "STMDB", -0, BDT, 0x08000000, "STMDA", -0, BDT, 0x09800000, "STMIB", -0, BDT, 0x08800000, "STMIA", -0, BDT, 0x09000000, "STMFD", -0, BDT, 0x09800000, "STMFA", -0, BDT, 0x08000000, "STMED", -0, BDT, 0x08800000, "STMEA", +{0, BDT, 0x09100000, "LDMDB"}, +{0, BDT, 0x08100000, "LDMDA"}, +{0, BDT, 0x09900000, "LDMIB"}, +{0, BDT, 0x08900000, "LDMIA"}, +{0, BDT, 0x08900000, "LDMFD"}, +{0, BDT, 0x08100000, "LDMFA"}, +{0, BDT, 0x09900000, "LDMED"}, +{0, BDT, 0x09100000, "LDMEA"}, +{0, BDT, 0x09000000, "STMDB"}, +{0, BDT, 0x08000000, "STMDA"}, +{0, BDT, 0x09800000, "STMIB"}, +{0, BDT, 0x08800000, "STMIA"}, +{0, BDT, 0x09000000, "STMFD"}, +{0, BDT, 0x09800000, "STMFA"}, +{0, BDT, 0x08000000, "STMED"}, +{0, BDT, 0x08800000, "STMEA"}, -0, SWI, 0x0F000000, "SWI", +{0, SWI, 0x0F000000, "SWI"}, -0, ADR, 0x00000000, "ADR", +{0, ADR, 0x00000000, "ADR"}, -0, MUL, 0x00000090, "MUL", -0, MLA, 0x00200090, "MLA", +{0, MUL, 0x00000090, "MUL"}, +{0, MLA, 0x00200090, "MLA"}, diff --git a/mach/i386/as/mach3.c b/mach/i386/as/mach3.c index 1a348b584..37f03566b 100644 --- a/mach/i386/as/mach3.c +++ b/mach/i386/as/mach3.c @@ -10,411 +10,411 @@ * No system registers for now ... */ -0, USE16, 0, ".use16", -0, USE32, 0, ".use32", -0, R32, 0, "ax", -0, R32, 1, "cx", -0, R32, 2, "dx", -0, R32, 3, "bx", -0, R32, 4, "sp", -0, R32, 5, "bp", -0, R32, 6, "si", -0, R32, 7, "di", -0, R32, 0, "eax", -0, R32, 1, "ecx", -0, R32, 2, "edx", -0, R32, 3, "ebx", -0, R32, 4, "esp", -0, R32, 5, "ebp", -0, R32, 6, "esi", -0, R32, 7, "edi", -0, R8, 0, "al", -0, R8, 1, "cl", -0, R8, 2, "dl", -0, R8, 3, "bl", -0, R8, 4, "ah", -0, R8, 5, "ch", -0, R8, 6, "dh", -0, R8, 7, "bh", -0, RSEG, 0, "es", -0, RSEG, 1, "cs", -0, RSEG, 2, "ss", -0, RSEG, 3, "ds", -0, RSEG, 4, "fs", -0, RSEG, 5, "gs", -0, RSYSCR, 0, "cr0", -0, RSYSCR, 2, "cr2", -0, RSYSCR, 3, "cr3", -0, RSYSDR, 0, "dr0", -0, RSYSDR, 1, "dr1", -0, RSYSDR, 2, "dr2", -0, RSYSDR, 3, "dr3", -0, RSYSDR, 6, "dr6", -0, RSYSDR, 7, "dr7", -0, RSYSTR, 3, "tr3", /* i486 */ -0, RSYSTR, 4, "tr4", /* i486 */ -0, RSYSTR, 5, "tr5", /* i486 */ -0, RSYSTR, 6, "tr6", -0, RSYSTR, 7, "tr7", -0, ADDOP, 000, "addb", -0, ADDOP, 001, "add", -0, ADDOP, 010, "orb", -0, ADDOP, 011, "or", -0, ADDOP, 020, "adcb", -0, ADDOP, 021, "adc", -0, ADDOP, 030, "sbbb", -0, ADDOP, 031, "sbb", -0, ADDOP, 040, "andb", -0, ADDOP, 041, "and", -0, ADDOP, 050, "subb", -0, ADDOP, 051, "sub", -0, ADDOP, 060, "xorb", -0, ADDOP, 061, "xor", -0, ADDOP, 070, "cmpb", -0, ADDOP, 071, "cmp", -0, BITTEST, 04, "bt", -0, BITTEST, 05, "bts", -0, BITTEST, 06, "btr", -0, BITTEST, 07, "btc", -0, CALFOP, 030+(0232<<8), "callf", -0, CALFOP, 050+(0352<<8), "jmpf", -0, CALLOP, 020+(0350<<8), "call", -0, CALLOP, 040+(0351<<8), "jmp", -0, ENTER, 0310, "enter", -0, EXTEND, 0267, "movzx", -0, EXTEND, 0266, "movzxb", -0, EXTEND, 0277, "movsx", -0, EXTEND, 0276, "movsxb", -0, EXTOP, 0002, "lar", -0, EXTOP, 0003, "lsl", -0, EXTOP, 0274, "bsf", -0, EXTOP, 0275, "bsr", -0, EXTOP1, 0000, "sldt", -0, EXTOP1, 0001, "sgdt", -0, EXTOP1, 0010, "str", -0, EXTOP1, 0011, "sidt", -0, EXTOP1, 0020, "lldt", -0, EXTOP1, 0021, "lgdt", -0, EXTOP1, 0030, "ltr", -0, EXTOP1, 0031, "lidt", -0, EXTOP1, 0040, "verr", -0, EXTOP1, 0041, "smsw", -0, EXTOP1, 0050, "verw", -0, EXTOP1, 0061, "lmsw", -0, IMUL, 00, "imul", -0, IMULB, 050, "imulb", -0, INCOP, 000, "incb", -0, INCOP, 001, "inc", -0, INCOP, 010, "decb", -0, INCOP, 011, "dec", -0, INT, 0, "int", -0, IOOP, 0344, "inb", -0, IOOP, 0345, "in", -0, IOOP, 0346, "outb", -0, IOOP, 0347, "out", -0, JOP, 0340, "loopne", -0, JOP, 0340, "loopnz", -0, JOP, 0341, "loope", -0, JOP, 0341, "loopz", -0, JOP, 0342, "loop", -0, JOP, 0343, "jcxz", -0, JOP, 0343, "jecxz", -0, JOP2, 0000, "jo", -0, JOP2, 0001, "jno", -0, JOP2, 0002, "jb", -0, JOP2, 0002, "jc", -0, JOP2, 0002, "jnae", -0, JOP2, 0003, "jae", -0, JOP2, 0003, "jnb", -0, JOP2, 0003, "jnc", -0, JOP2, 0004, "je", -0, JOP2, 0004, "jz", -0, JOP2, 0005, "jne", -0, JOP2, 0005, "jnz", -0, JOP2, 0006, "jbe", -0, JOP2, 0006, "jna", -0, JOP2, 0007, "ja", -0, JOP2, 0007, "jnbe", -0, JOP2, 0010, "js", -0, JOP2, 0011, "jns", -0, JOP2, 0012, "jp", -0, JOP2, 0012, "jpe", -0, JOP2, 0013, "jnp", -0, JOP2, 0013, "jpo", -0, JOP2, 0014, "jl", -0, JOP2, 0014, "jnge", -0, JOP2, 0015, "jge", -0, JOP2, 0015, "jnl", -0, JOP2, 0016, "jle", -0, JOP2, 0016, "jng", -0, JOP2, 0017, "jg", -0, JOP2, 0017, "jnle", -0, LEAOP, 0142, "bound", -0, LEAOP, 0215, "lea", -0, LEAOP, 0304, "les", -0, LEAOP, 0305, "lds", -0, LEAOP2, 0262, "lss", -0, LEAOP2, 0264, "lfs", -0, LEAOP2, 0265, "lgs", -0, LSHFT, 0244, "shld", -0, LSHFT, 0254, "shrd", -0, MOV, 0, "movb", -0, MOV, 1, "mov", -0, NOOP_1, 0140, "pusha", -0, NOOP_1, 0140, "pushad", -0, NOOP_1, 0141, "popa", -0, NOOP_1, 0141, "popad", -0, NOOP_1, 0156, "outsb", -0, NOOP_1, 0157, "outs", -0, NOOP_1, 0220, "nop", -0, NOOP_1, 0230, "cbw", -0, NOOP_1, 0230, "cwde", /* same opcode as cbw! */ -0, NOOP_1, 0231, "cdq", /* same opcode as cwd! */ -0, NOOP_1, 0231, "cwd", -0, NOOP_1, 0233, "wait", -0, NOOP_1, 0234, "pushf", -0, NOOP_1, 0235, "popf", -0, NOOP_1, 0236, "sahf", -0, NOOP_1, 0237, "lahf", -0, NOOP_1, 0244, "movsb", -0, NOOP_1, 0245, "movs", -0, NOOP_1, 0246, "cmpsb", -0, NOOP_1, 0154, "insb", -0, NOOP_1, 0247, "cmps", -0, NOOP_1, 0155, "ins", -0, NOOP_1, 0252, "stosb", -0, NOOP_1, 0253, "stos", -0, NOOP_1, 0254, "lodsb", -0, NOOP_1, 0255, "lods", -0, NOOP_1, 0256, "scasb", -0, NOOP_1, 0257, "scas", -0, NOOP_1, 0311, "leave", -0, NOOP_1, 0316, "into", -0, NOOP_1, 0317, "iret", -0, NOOP_1, 0317, "iretd", -0, NOOP_1, 0327, "xlat", -0, NOOP_1, 0364, "hlt", -0, NOOP_1, 0365, "cmc", -0, NOOP_1, 0370, "clc", -0, NOOP_1, 0371, "stc", -0, NOOP_1, 0372, "cli", -0, NOOP_1, 0373, "sti", -0, NOOP_1, 0374, "cld", -0, NOOP_1, 0375, "std", -0, NOOP_1, 047, "daa", -0, NOOP_1, 057, "das", -0, NOOP_1, 067, "aaa", -0, NOOP_1, 077, "aas", -0, NOOP_2, 017+(06<<8), "clts", -0, NOOP_2, 0324+(012<<8), "aam", -0, NOOP_2, 0325+(012<<8), "aad", -0, NOTOP, 020, "notb", -0, NOTOP, 021, "not", -0, NOTOP, 030, "negb", -0, NOTOP, 031, "neg", -0, NOTOP, 040, "mulb", -0, NOTOP, 041, "mul", -0, NOTOP, 060, "divb", -0, NOTOP, 061, "div", -0, NOTOP, 070, "idivb", -0, NOTOP, 071, "idiv", -0, PREFIX, 0144, "fseg", -0, PREFIX, 0145, "gseg", -0, OTOGGLE, 0146, "o16", /* operand size toggle */ -0, OTOGGLE, 0346, "o32", /* operand size toggle */ -0, ATOGGLE, 0147, "a16", /* address size toggle */ -0, ATOGGLE, 0347, "a32", /* address size toggle */ -0, PREFIX, 0360, "lock", -0, PREFIX, 0362, "repne", -0, PREFIX, 0362, "repnz", -0, PREFIX, 0363, "rep", -0, PREFIX, 0363, "repe", -0, PREFIX, 0363, "repz", -0, PREFIX, 046, "eseg", -0, PREFIX, 056, "cseg", -0, PREFIX, 066, "sseg", -0, PREFIX, 076, "dseg", -0, PUSHOP, 0, "push", -0, PUSHOP, 1, "pop", -0, RET, 0303, "ret", -0, RET, 0313, "retf", -0, ROLOP, 000, "rolb", -0, ROLOP, 001, "rol", -0, ROLOP, 010, "rorb", -0, ROLOP, 011, "ror", -0, ROLOP, 020, "rclb", -0, ROLOP, 021, "rcl", -0, ROLOP, 030, "rcrb", -0, ROLOP, 031, "rcr", -0, ROLOP, 040, "salb", -0, ROLOP, 040, "shlb", -0, ROLOP, 041, "sal", -0, ROLOP, 041, "shl", -0, ROLOP, 050, "shrb", -0, ROLOP, 051, "shr", -0, ROLOP, 070, "sarb", -0, ROLOP, 071, "sar", -0, SETCC, 0000, "seto", -0, SETCC, 0001, "setno", -0, SETCC, 0002, "setb", -0, SETCC, 0002, "setnae", -0, SETCC, 0003, "setae", -0, SETCC, 0003, "setnb", -0, SETCC, 0004, "sete", -0, SETCC, 0004, "setz", -0, SETCC, 0005, "setne", -0, SETCC, 0005, "setnz", -0, SETCC, 0006, "setbe", -0, SETCC, 0006, "setna", -0, SETCC, 0007, "seta", -0, SETCC, 0007, "setnbe", -0, SETCC, 0010, "sets", -0, SETCC, 0011, "setns", -0, SETCC, 0012, "setp", -0, SETCC, 0012, "setpe", -0, SETCC, 0013, "setnp", -0, SETCC, 0013, "setpo", -0, SETCC, 0014, "setl", -0, SETCC, 0014, "setnge", -0, SETCC, 0015, "setge", -0, SETCC, 0015, "setnl", -0, SETCC, 0016, "setle", -0, SETCC, 0016, "setng", -0, SETCC, 0017, "setg", -0, SETCC, 0017, "setnle", -0, TEST, 0, "testb", -0, TEST, 1, "test", -0, XCHG, 0, "xchgb", -0, XCHG, 1, "xchg", -0, ARPLOP, 0143, "arpl", +{0, USE16, 0, ".use16"}, +{0, USE32, 0, ".use32"}, +{0, R32, 0, "ax"}, +{0, R32, 1, "cx"}, +{0, R32, 2, "dx"}, +{0, R32, 3, "bx"}, +{0, R32, 4, "sp"}, +{0, R32, 5, "bp"}, +{0, R32, 6, "si"}, +{0, R32, 7, "di"}, +{0, R32, 0, "eax"}, +{0, R32, 1, "ecx"}, +{0, R32, 2, "edx"}, +{0, R32, 3, "ebx"}, +{0, R32, 4, "esp"}, +{0, R32, 5, "ebp"}, +{0, R32, 6, "esi"}, +{0, R32, 7, "edi"}, +{0, R8, 0, "al"}, +{0, R8, 1, "cl"}, +{0, R8, 2, "dl"}, +{0, R8, 3, "bl"}, +{0, R8, 4, "ah"}, +{0, R8, 5, "ch"}, +{0, R8, 6, "dh"}, +{0, R8, 7, "bh"}, +{0, RSEG, 0, "es"}, +{0, RSEG, 1, "cs"}, +{0, RSEG, 2, "ss"}, +{0, RSEG, 3, "ds"}, +{0, RSEG, 4, "fs"}, +{0, RSEG, 5, "gs"}, +{0, RSYSCR, 0, "cr0"}, +{0, RSYSCR, 2, "cr2"}, +{0, RSYSCR, 3, "cr3"}, +{0, RSYSDR, 0, "dr0"}, +{0, RSYSDR, 1, "dr1"}, +{0, RSYSDR, 2, "dr2"}, +{0, RSYSDR, 3, "dr3"}, +{0, RSYSDR, 6, "dr6"}, +{0, RSYSDR, 7, "dr7"}, +{0, RSYSTR, 3, "tr3"}, /* i486 */ +{0, RSYSTR, 4, "tr4"}, /* i486 */ +{0, RSYSTR, 5, "tr5"}, /* i486 */ +{0, RSYSTR, 6, "tr6"}, +{0, RSYSTR, 7, "tr7"}, +{0, ADDOP, 000, "addb"}, +{0, ADDOP, 001, "add"}, +{0, ADDOP, 010, "orb"}, +{0, ADDOP, 011, "or"}, +{0, ADDOP, 020, "adcb"}, +{0, ADDOP, 021, "adc"}, +{0, ADDOP, 030, "sbbb"}, +{0, ADDOP, 031, "sbb"}, +{0, ADDOP, 040, "andb"}, +{0, ADDOP, 041, "and"}, +{0, ADDOP, 050, "subb"}, +{0, ADDOP, 051, "sub"}, +{0, ADDOP, 060, "xorb"}, +{0, ADDOP, 061, "xor"}, +{0, ADDOP, 070, "cmpb"}, +{0, ADDOP, 071, "cmp"}, +{0, BITTEST, 04, "bt"}, +{0, BITTEST, 05, "bts"}, +{0, BITTEST, 06, "btr"}, +{0, BITTEST, 07, "btc"}, +{0, CALFOP, 030+(0232<<8), "callf"}, +{0, CALFOP, 050+(0352<<8), "jmpf"}, +{0, CALLOP, 020+(0350<<8), "call"}, +{0, CALLOP, 040+(0351<<8), "jmp"}, +{0, ENTER, 0310, "enter"}, +{0, EXTEND, 0267, "movzx"}, +{0, EXTEND, 0266, "movzxb"}, +{0, EXTEND, 0277, "movsx"}, +{0, EXTEND, 0276, "movsxb"}, +{0, EXTOP, 0002, "lar"}, +{0, EXTOP, 0003, "lsl"}, +{0, EXTOP, 0274, "bsf"}, +{0, EXTOP, 0275, "bsr"}, +{0, EXTOP1, 0000, "sldt"}, +{0, EXTOP1, 0001, "sgdt"}, +{0, EXTOP1, 0010, "str"}, +{0, EXTOP1, 0011, "sidt"}, +{0, EXTOP1, 0020, "lldt"}, +{0, EXTOP1, 0021, "lgdt"}, +{0, EXTOP1, 0030, "ltr"}, +{0, EXTOP1, 0031, "lidt"}, +{0, EXTOP1, 0040, "verr"}, +{0, EXTOP1, 0041, "smsw"}, +{0, EXTOP1, 0050, "verw"}, +{0, EXTOP1, 0061, "lmsw"}, +{0, IMUL, 00, "imul"}, +{0, IMULB, 050, "imulb"}, +{0, INCOP, 000, "incb"}, +{0, INCOP, 001, "inc"}, +{0, INCOP, 010, "decb"}, +{0, INCOP, 011, "dec"}, +{0, INT, 0, "int"}, +{0, IOOP, 0344, "inb"}, +{0, IOOP, 0345, "in"}, +{0, IOOP, 0346, "outb"}, +{0, IOOP, 0347, "out"}, +{0, JOP, 0340, "loopne"}, +{0, JOP, 0340, "loopnz"}, +{0, JOP, 0341, "loope"}, +{0, JOP, 0341, "loopz"}, +{0, JOP, 0342, "loop"}, +{0, JOP, 0343, "jcxz"}, +{0, JOP, 0343, "jecxz"}, +{0, JOP2, 0000, "jo"}, +{0, JOP2, 0001, "jno"}, +{0, JOP2, 0002, "jb"}, +{0, JOP2, 0002, "jc"}, +{0, JOP2, 0002, "jnae"}, +{0, JOP2, 0003, "jae"}, +{0, JOP2, 0003, "jnb"}, +{0, JOP2, 0003, "jnc"}, +{0, JOP2, 0004, "je"}, +{0, JOP2, 0004, "jz"}, +{0, JOP2, 0005, "jne"}, +{0, JOP2, 0005, "jnz"}, +{0, JOP2, 0006, "jbe"}, +{0, JOP2, 0006, "jna"}, +{0, JOP2, 0007, "ja"}, +{0, JOP2, 0007, "jnbe"}, +{0, JOP2, 0010, "js"}, +{0, JOP2, 0011, "jns"}, +{0, JOP2, 0012, "jp"}, +{0, JOP2, 0012, "jpe"}, +{0, JOP2, 0013, "jnp"}, +{0, JOP2, 0013, "jpo"}, +{0, JOP2, 0014, "jl"}, +{0, JOP2, 0014, "jnge"}, +{0, JOP2, 0015, "jge"}, +{0, JOP2, 0015, "jnl"}, +{0, JOP2, 0016, "jle"}, +{0, JOP2, 0016, "jng"}, +{0, JOP2, 0017, "jg"}, +{0, JOP2, 0017, "jnle"}, +{0, LEAOP, 0142, "bound"}, +{0, LEAOP, 0215, "lea"}, +{0, LEAOP, 0304, "les"}, +{0, LEAOP, 0305, "lds"}, +{0, LEAOP2, 0262, "lss"}, +{0, LEAOP2, 0264, "lfs"}, +{0, LEAOP2, 0265, "lgs"}, +{0, LSHFT, 0244, "shld"}, +{0, LSHFT, 0254, "shrd"}, +{0, MOV, 0, "movb"}, +{0, MOV, 1, "mov"}, +{0, NOOP_1, 0140, "pusha"}, +{0, NOOP_1, 0140, "pushad"}, +{0, NOOP_1, 0141, "popa"}, +{0, NOOP_1, 0141, "popad"}, +{0, NOOP_1, 0156, "outsb"}, +{0, NOOP_1, 0157, "outs"}, +{0, NOOP_1, 0220, "nop"}, +{0, NOOP_1, 0230, "cbw"}, +{0, NOOP_1, 0230, "cwde"}, /* same opcode as cbw! */ +{0, NOOP_1, 0231, "cdq"}, /* same opcode as cwd! */ +{0, NOOP_1, 0231, "cwd"}, +{0, NOOP_1, 0233, "wait"}, +{0, NOOP_1, 0234, "pushf"}, +{0, NOOP_1, 0235, "popf"}, +{0, NOOP_1, 0236, "sahf"}, +{0, NOOP_1, 0237, "lahf"}, +{0, NOOP_1, 0244, "movsb"}, +{0, NOOP_1, 0245, "movs"}, +{0, NOOP_1, 0246, "cmpsb"}, +{0, NOOP_1, 0154, "insb"}, +{0, NOOP_1, 0247, "cmps"}, +{0, NOOP_1, 0155, "ins"}, +{0, NOOP_1, 0252, "stosb"}, +{0, NOOP_1, 0253, "stos"}, +{0, NOOP_1, 0254, "lodsb"}, +{0, NOOP_1, 0255, "lods"}, +{0, NOOP_1, 0256, "scasb"}, +{0, NOOP_1, 0257, "scas"}, +{0, NOOP_1, 0311, "leave"}, +{0, NOOP_1, 0316, "into"}, +{0, NOOP_1, 0317, "iret"}, +{0, NOOP_1, 0317, "iretd"}, +{0, NOOP_1, 0327, "xlat"}, +{0, NOOP_1, 0364, "hlt"}, +{0, NOOP_1, 0365, "cmc"}, +{0, NOOP_1, 0370, "clc"}, +{0, NOOP_1, 0371, "stc"}, +{0, NOOP_1, 0372, "cli"}, +{0, NOOP_1, 0373, "sti"}, +{0, NOOP_1, 0374, "cld"}, +{0, NOOP_1, 0375, "std"}, +{0, NOOP_1, 047, "daa"}, +{0, NOOP_1, 057, "das"}, +{0, NOOP_1, 067, "aaa"}, +{0, NOOP_1, 077, "aas"}, +{0, NOOP_2, 017+(06<<8), "clts"}, +{0, NOOP_2, 0324+(012<<8), "aam"}, +{0, NOOP_2, 0325+(012<<8), "aad"}, +{0, NOTOP, 020, "notb"}, +{0, NOTOP, 021, "not"}, +{0, NOTOP, 030, "negb"}, +{0, NOTOP, 031, "neg"}, +{0, NOTOP, 040, "mulb"}, +{0, NOTOP, 041, "mul"}, +{0, NOTOP, 060, "divb"}, +{0, NOTOP, 061, "div"}, +{0, NOTOP, 070, "idivb"}, +{0, NOTOP, 071, "idiv"}, +{0, PREFIX, 0144, "fseg"}, +{0, PREFIX, 0145, "gseg"}, +{0, OTOGGLE, 0146, "o16"}, /* operand size toggle */ +{0, OTOGGLE, 0346, "o32"}, /* operand size toggle */ +{0, ATOGGLE, 0147, "a16"}, /* address size toggle */ +{0, ATOGGLE, 0347, "a32"}, /* address size toggle */ +{0, PREFIX, 0360, "lock"}, +{0, PREFIX, 0362, "repne"}, +{0, PREFIX, 0362, "repnz"}, +{0, PREFIX, 0363, "rep"}, +{0, PREFIX, 0363, "repe"}, +{0, PREFIX, 0363, "repz"}, +{0, PREFIX, 046, "eseg"}, +{0, PREFIX, 056, "cseg"}, +{0, PREFIX, 066, "sseg"}, +{0, PREFIX, 076, "dseg"}, +{0, PUSHOP, 0, "push"}, +{0, PUSHOP, 1, "pop"}, +{0, RET, 0303, "ret"}, +{0, RET, 0313, "retf"}, +{0, ROLOP, 000, "rolb"}, +{0, ROLOP, 001, "rol"}, +{0, ROLOP, 010, "rorb"}, +{0, ROLOP, 011, "ror"}, +{0, ROLOP, 020, "rclb"}, +{0, ROLOP, 021, "rcl"}, +{0, ROLOP, 030, "rcrb"}, +{0, ROLOP, 031, "rcr"}, +{0, ROLOP, 040, "salb"}, +{0, ROLOP, 040, "shlb"}, +{0, ROLOP, 041, "sal"}, +{0, ROLOP, 041, "shl"}, +{0, ROLOP, 050, "shrb"}, +{0, ROLOP, 051, "shr"}, +{0, ROLOP, 070, "sarb"}, +{0, ROLOP, 071, "sar"}, +{0, SETCC, 0000, "seto"}, +{0, SETCC, 0001, "setno"}, +{0, SETCC, 0002, "setb"}, +{0, SETCC, 0002, "setnae"}, +{0, SETCC, 0003, "setae"}, +{0, SETCC, 0003, "setnb"}, +{0, SETCC, 0004, "sete"}, +{0, SETCC, 0004, "setz"}, +{0, SETCC, 0005, "setne"}, +{0, SETCC, 0005, "setnz"}, +{0, SETCC, 0006, "setbe"}, +{0, SETCC, 0006, "setna"}, +{0, SETCC, 0007, "seta"}, +{0, SETCC, 0007, "setnbe"}, +{0, SETCC, 0010, "sets"}, +{0, SETCC, 0011, "setns"}, +{0, SETCC, 0012, "setp"}, +{0, SETCC, 0012, "setpe"}, +{0, SETCC, 0013, "setnp"}, +{0, SETCC, 0013, "setpo"}, +{0, SETCC, 0014, "setl"}, +{0, SETCC, 0014, "setnge"}, +{0, SETCC, 0015, "setge"}, +{0, SETCC, 0015, "setnl"}, +{0, SETCC, 0016, "setle"}, +{0, SETCC, 0016, "setng"}, +{0, SETCC, 0017, "setg"}, +{0, SETCC, 0017, "setnle"}, +{0, TEST, 0, "testb"}, +{0, TEST, 1, "test"}, +{0, XCHG, 0, "xchgb"}, +{0, XCHG, 1, "xchg"}, +{0, ARPLOP, 0143, "arpl"}, /* Intel 80[23]87 coprocessor keywords */ -0, ST, 0, "st", +{0, ST, 0, "st"}, -0, FNOOP, FESC+1+(0xF0<<8), "f2xm1", -0, FNOOP, FESC+1+(0xE1<<8), "fabs", -0, FNOOP, FESC+1+(0xE0<<8), "fchs", -0, FNOOP, FESC+3+(0xE2<<8), "fclex", -0, FNOOP, FESC+6+(0xD9<<8), "fcompp", -0, FNOOP, FESC+2+(0xE9<<8), "fucompp", -0, FNOOP, FESC+1+(0xF6<<8), "fdecstp", -0, FNOOP, FESC+3+(0xE1<<8), "fdisi", -0, FNOOP, FESC+3+(0xE0<<8), "feni", -0, FNOOP, FESC+1+(0xF7<<8), "fincstp", -0, FNOOP, FESC+3+(0xE3<<8), "finit", -0, FNOOP, FESC+1+(0xE8<<8), "fld1", -0, FNOOP, FESC+1+(0xEA<<8), "fldl2e", -0, FNOOP, FESC+1+(0xE9<<8), "fldl2t", -0, FNOOP, FESC+1+(0xEC<<8), "fldlg2", -0, FNOOP, FESC+1+(0xED<<8), "fldln2", -0, FNOOP, FESC+1+(0xEB<<8), "fldpi", -0, FNOOP, FESC+1+(0xEE<<8), "fldz", -0, FNOOP, FESC+1+(0xD0<<8), "fnop", -0, FNOOP, FESC+1+(0xF3<<8), "fpatan", -0, FNOOP, FESC+1+(0xFF<<8), "fcos", -0, FNOOP, FESC+1+(0xFE<<8), "fsin", -0, FNOOP, FESC+1+(0xFB<<8), "fsincos", -0, FNOOP, FESC+1+(0xF8<<8), "fprem", -0, FNOOP, FESC+1+(0xF5<<8), "fprem1", -0, FNOOP, FESC+1+(0xF2<<8), "fptan", -0, FNOOP, FESC+1+(0xFC<<8), "frndint", -0, FNOOP, FESC+1+(0xFD<<8), "fscale", -0, FNOOP, FESC+1+(0xFA<<8), "fsqrt", -0, FNOOP, FESC+1+(0xE4<<8), "ftst", -0, FNOOP, FESC+1+(0xE5<<8), "fxam", -0, FNOOP, FESC+1+(0xF4<<8), "fxtract", -0, FNOOP, FESC+1+(0xF1<<8), "fyl2x", -0, FNOOP, FESC+1+(0xF9<<8), "fyl2xp1", +{0, FNOOP, FESC+1+(0xF0<<8), "f2xm1"}, +{0, FNOOP, FESC+1+(0xE1<<8), "fabs"}, +{0, FNOOP, FESC+1+(0xE0<<8), "fchs"}, +{0, FNOOP, FESC+3+(0xE2<<8), "fclex"}, +{0, FNOOP, FESC+6+(0xD9<<8), "fcompp"}, +{0, FNOOP, FESC+2+(0xE9<<8), "fucompp"}, +{0, FNOOP, FESC+1+(0xF6<<8), "fdecstp"}, +{0, FNOOP, FESC+3+(0xE1<<8), "fdisi"}, +{0, FNOOP, FESC+3+(0xE0<<8), "feni"}, +{0, FNOOP, FESC+1+(0xF7<<8), "fincstp"}, +{0, FNOOP, FESC+3+(0xE3<<8), "finit"}, +{0, FNOOP, FESC+1+(0xE8<<8), "fld1"}, +{0, FNOOP, FESC+1+(0xEA<<8), "fldl2e"}, +{0, FNOOP, FESC+1+(0xE9<<8), "fldl2t"}, +{0, FNOOP, FESC+1+(0xEC<<8), "fldlg2"}, +{0, FNOOP, FESC+1+(0xED<<8), "fldln2"}, +{0, FNOOP, FESC+1+(0xEB<<8), "fldpi"}, +{0, FNOOP, FESC+1+(0xEE<<8), "fldz"}, +{0, FNOOP, FESC+1+(0xD0<<8), "fnop"}, +{0, FNOOP, FESC+1+(0xF3<<8), "fpatan"}, +{0, FNOOP, FESC+1+(0xFF<<8), "fcos"}, +{0, FNOOP, FESC+1+(0xFE<<8), "fsin"}, +{0, FNOOP, FESC+1+(0xFB<<8), "fsincos"}, +{0, FNOOP, FESC+1+(0xF8<<8), "fprem"}, +{0, FNOOP, FESC+1+(0xF5<<8), "fprem1"}, +{0, FNOOP, FESC+1+(0xF2<<8), "fptan"}, +{0, FNOOP, FESC+1+(0xFC<<8), "frndint"}, +{0, FNOOP, FESC+1+(0xFD<<8), "fscale"}, +{0, FNOOP, FESC+1+(0xFA<<8), "fsqrt"}, +{0, FNOOP, FESC+1+(0xE4<<8), "ftst"}, +{0, FNOOP, FESC+1+(0xE5<<8), "fxam"}, +{0, FNOOP, FESC+1+(0xF4<<8), "fxtract"}, +{0, FNOOP, FESC+1+(0xF1<<8), "fyl2x"}, +{0, FNOOP, FESC+1+(0xF9<<8), "fyl2xp1"}, -0, FMEM, FESC+6+(0<<11), "fiadds", -0, FMEM, FESC+2+(0<<11), "fiaddl", -0, FMEM, FESC+0+(0<<11), "fadds", -0, FMEM, FESC+4+(0<<11), "faddd", -0, FMEM, FESC+7+(4<<11), "fbld", -0, FMEM, FESC+7+(6<<11), "fbstp", -0, FMEM, FESC+6+(2<<11), "ficoms", -0, FMEM, FESC+2+(2<<11), "ficoml", -0, FMEM, FESC+0+(2<<11), "fcoms", -0, FMEM, FESC+4+(2<<11), "fcomd", -0, FMEM, FESC+6+(3<<11), "ficomps", -0, FMEM, FESC+2+(3<<11), "ficompl", -0, FMEM, FESC+0+(3<<11), "fcomps", -0, FMEM, FESC+4+(3<<11), "fcompd", -0, FMEM, FESC+6+(6<<11), "fidivs", -0, FMEM, FESC+2+(6<<11), "fidivl", -0, FMEM, FESC+0+(6<<11), "fdivs", -0, FMEM, FESC+4+(6<<11), "fdivd", -0, FMEM, FESC+6+(7<<11), "fidivrs", -0, FMEM, FESC+2+(7<<11), "fidivrl", -0, FMEM, FESC+0+(7<<11), "fdivrs", -0, FMEM, FESC+4+(7<<11), "fdivrd", -0, FMEM, FESC+7+(5<<11), "fildq", -0, FMEM, FESC+7+(0<<11), "filds", -0, FMEM, FESC+3+(0<<11), "fildl", -0, FMEM, FESC+1+(0<<11), "flds", -0, FMEM, FESC+5+(0<<11), "fldd", -0, FMEM, FESC+3+(5<<11), "fldx", -0, FMEM, FESC+1+(5<<11), "fldcw", -0, FMEM, FESC+1+(4<<11), "fldenv", -0, FMEM, FESC+6+(1<<11), "fimuls", -0, FMEM, FESC+2+(1<<11), "fimull", -0, FMEM, FESC+0+(1<<11), "fmuls", -0, FMEM, FESC+4+(1<<11), "fmuld", -0, FMEM, FESC+5+(4<<11), "frstor", -0, FMEM, FESC+5+(6<<11), "fsave", -0, FMEM, FESC+7+(2<<11), "fists", -0, FMEM, FESC+3+(2<<11), "fistl", -0, FMEM, FESC+1+(2<<11), "fsts", -0, FMEM, FESC+5+(2<<11), "fstd", -0, FMEM, FESC+7+(7<<11), "fistpq", -0, FMEM, FESC+7+(3<<11), "fistps", -0, FMEM, FESC+3+(3<<11), "fistpl", -0, FMEM, FESC+1+(3<<11), "fstps", -0, FMEM, FESC+5+(3<<11), "fstpd", -0, FMEM, FESC+3+(7<<11), "fstpx", -0, FMEM, FESC+1+(7<<11), "fstcw", -0, FMEM, FESC+1+(6<<11), "fstenv", -0, FMEM_AX, FESC+5+(7<<11), "fstsw", -0, FMEM, FESC+6+(4<<11), "fisubs", -0, FMEM, FESC+2+(4<<11), "fisubl", -0, FMEM, FESC+0+(4<<11), "fsubs", -0, FMEM, FESC+4+(4<<11), "fsubd", -0, FMEM, FESC+6+(5<<11), "fisubrs", -0, FMEM, FESC+2+(5<<11), "fisubrl", -0, FMEM, FESC+0+(5<<11), "fsubrs", -0, FMEM, FESC+4+(5<<11), "fsubrd", +{0, FMEM, FESC+6+(0<<11), "fiadds"}, +{0, FMEM, FESC+2+(0<<11), "fiaddl"}, +{0, FMEM, FESC+0+(0<<11), "fadds"}, +{0, FMEM, FESC+4+(0<<11), "faddd"}, +{0, FMEM, FESC+7+(4<<11), "fbld"}, +{0, FMEM, FESC+7+(6<<11), "fbstp"}, +{0, FMEM, FESC+6+(2<<11), "ficoms"}, +{0, FMEM, FESC+2+(2<<11), "ficoml"}, +{0, FMEM, FESC+0+(2<<11), "fcoms"}, +{0, FMEM, FESC+4+(2<<11), "fcomd"}, +{0, FMEM, FESC+6+(3<<11), "ficomps"}, +{0, FMEM, FESC+2+(3<<11), "ficompl"}, +{0, FMEM, FESC+0+(3<<11), "fcomps"}, +{0, FMEM, FESC+4+(3<<11), "fcompd"}, +{0, FMEM, FESC+6+(6<<11), "fidivs"}, +{0, FMEM, FESC+2+(6<<11), "fidivl"}, +{0, FMEM, FESC+0+(6<<11), "fdivs"}, +{0, FMEM, FESC+4+(6<<11), "fdivd"}, +{0, FMEM, FESC+6+(7<<11), "fidivrs"}, +{0, FMEM, FESC+2+(7<<11), "fidivrl"}, +{0, FMEM, FESC+0+(7<<11), "fdivrs"}, +{0, FMEM, FESC+4+(7<<11), "fdivrd"}, +{0, FMEM, FESC+7+(5<<11), "fildq"}, +{0, FMEM, FESC+7+(0<<11), "filds"}, +{0, FMEM, FESC+3+(0<<11), "fildl"}, +{0, FMEM, FESC+1+(0<<11), "flds"}, +{0, FMEM, FESC+5+(0<<11), "fldd"}, +{0, FMEM, FESC+3+(5<<11), "fldx"}, +{0, FMEM, FESC+1+(5<<11), "fldcw"}, +{0, FMEM, FESC+1+(4<<11), "fldenv"}, +{0, FMEM, FESC+6+(1<<11), "fimuls"}, +{0, FMEM, FESC+2+(1<<11), "fimull"}, +{0, FMEM, FESC+0+(1<<11), "fmuls"}, +{0, FMEM, FESC+4+(1<<11), "fmuld"}, +{0, FMEM, FESC+5+(4<<11), "frstor"}, +{0, FMEM, FESC+5+(6<<11), "fsave"}, +{0, FMEM, FESC+7+(2<<11), "fists"}, +{0, FMEM, FESC+3+(2<<11), "fistl"}, +{0, FMEM, FESC+1+(2<<11), "fsts"}, +{0, FMEM, FESC+5+(2<<11), "fstd"}, +{0, FMEM, FESC+7+(7<<11), "fistpq"}, +{0, FMEM, FESC+7+(3<<11), "fistps"}, +{0, FMEM, FESC+3+(3<<11), "fistpl"}, +{0, FMEM, FESC+1+(3<<11), "fstps"}, +{0, FMEM, FESC+5+(3<<11), "fstpd"}, +{0, FMEM, FESC+3+(7<<11), "fstpx"}, +{0, FMEM, FESC+1+(7<<11), "fstcw"}, +{0, FMEM, FESC+1+(6<<11), "fstenv"}, +{0, FMEM_AX, FESC+5+(7<<11), "fstsw"}, +{0, FMEM, FESC+6+(4<<11), "fisubs"}, +{0, FMEM, FESC+2+(4<<11), "fisubl"}, +{0, FMEM, FESC+0+(4<<11), "fsubs"}, +{0, FMEM, FESC+4+(4<<11), "fsubd"}, +{0, FMEM, FESC+6+(5<<11), "fisubrs"}, +{0, FMEM, FESC+2+(5<<11), "fisubrl"}, +{0, FMEM, FESC+0+(5<<11), "fsubrs"}, +{0, FMEM, FESC+4+(5<<11), "fsubrd"}, -0, FST_I, FESC+1+(0xC0<<8), "fld", -0, FST_I, FESC+5+(0xD0<<8), "fst", -0, FST_I, FESC+5+(0xD8<<8), "fstp", -0, FST_I, FESC+1+(0xC8<<8), "fxch", -0, FST_I, FESC+0+(0xD0<<8), "fcom", -0, FST_I, FESC+5+(0xE0<<8), "fucom", -0, FST_I, FESC+0+(0xD8<<8), "fcomp", -0, FST_I, FESC+5+(0xE8<<8), "fucomp", -0, FST_I, FESC+5+(0xC0<<8), "ffree", +{0, FST_I, FESC+1+(0xC0<<8), "fld"}, +{0, FST_I, FESC+5+(0xD0<<8), "fst"}, +{0, FST_I, FESC+5+(0xD8<<8), "fstp"}, +{0, FST_I, FESC+1+(0xC8<<8), "fxch"}, +{0, FST_I, FESC+0+(0xD0<<8), "fcom"}, +{0, FST_I, FESC+5+(0xE0<<8), "fucom"}, +{0, FST_I, FESC+0+(0xD8<<8), "fcomp"}, +{0, FST_I, FESC+5+(0xE8<<8), "fucomp"}, +{0, FST_I, FESC+5+(0xC0<<8), "ffree"}, -0, FST_ST, FESC+0+(0xC0<<8), "fadd", -0, FST_ST, FESC+2+(0xC0<<8), "faddp", -0, FST_ST2, FESC+0+(0xF0<<8), "fdiv", -0, FST_ST2, FESC+2+(0xF0<<8), "fdivp", -0, FST_ST2, FESC+0+(0xF8<<8), "fdivr", -0, FST_ST2, FESC+2+(0xF8<<8), "fdivrp", -0, FST_ST, FESC+0+(0xC8<<8), "fmul", -0, FST_ST, FESC+2+(0xC8<<8), "fmulp", -0, FST_ST2, FESC+0+(0xE0<<8), "fsub", -0, FST_ST2, FESC+2+(0xE0<<8), "fsubp", -0, FST_ST2, FESC+0+(0xE8<<8), "fsubr", -0, FST_ST2, FESC+2+(0xE8<<8), "fsubrp", +{0, FST_ST, FESC+0+(0xC0<<8), "fadd"}, +{0, FST_ST, FESC+2+(0xC0<<8), "faddp"}, +{0, FST_ST2, FESC+0+(0xF0<<8), "fdiv"}, +{0, FST_ST2, FESC+2+(0xF0<<8), "fdivp"}, +{0, FST_ST2, FESC+0+(0xF8<<8), "fdivr"}, +{0, FST_ST2, FESC+2+(0xF8<<8), "fdivrp"}, +{0, FST_ST, FESC+0+(0xC8<<8), "fmul"}, +{0, FST_ST, FESC+2+(0xC8<<8), "fmulp"}, +{0, FST_ST2, FESC+0+(0xE0<<8), "fsub"}, +{0, FST_ST2, FESC+2+(0xE0<<8), "fsubp"}, +{0, FST_ST2, FESC+0+(0xE8<<8), "fsubr"}, +{0, FST_ST2, FESC+2+(0xE8<<8), "fsubrp"}, /* Intel 486 instructions */ -0, EXTOPBW, 0xC0, "xaddb", -0, EXTOPBW, 0xC1, "xadd", -0, EXTOPBW, 0xB0, "cmpxchgb", -0, EXTOPBW, 0xB1, "cmpxchg", -0, BSWAP, 0xC8, "bswap", -0, NOOP_2, 017+(010<<8), "invd", -0, EXTOP1, 071, "invlpg", -0, NOOP_2, 017+(011<<8), "wbinvd", +{0, EXTOPBW, 0xC0, "xaddb"}, +{0, EXTOPBW, 0xC1, "xadd"}, +{0, EXTOPBW, 0xB0, "cmpxchgb"}, +{0, EXTOPBW, 0xB1, "cmpxchg"}, +{0, BSWAP, 0xC8, "bswap"}, +{0, NOOP_2, 017+(010<<8), "invd"}, +{0, EXTOP1, 071, "invlpg"}, +{0, NOOP_2, 017+(011<<8), "wbinvd"}, diff --git a/mach/i80/as/mach3.c b/mach/i80/as/mach3.c index 94b531d2e..3dd2a689f 100644 --- a/mach/i80/as/mach3.c +++ b/mach/i80/as/mach3.c @@ -8,101 +8,101 @@ * Specials */ -0, KILL, 0, "kill", +{0, KILL, 0, "kill"}, /* * Intel 8080 keywords */ -0, REG, B, "b", -0, REG, C, "c", -0, REG, D, "d", -0, REG, E, "e", -0, REG, H, "h", -0, REG, L, "l", -0, REG, M, "m", -0, REG, A, "a", -0, REG, SP, "sp", -0, REG, PSW, "psw", -0, D16OP, 0315, "call", -0, D16OP, 0334, "cc", -0, D16OP, 0324, "cnc", -0, D16OP, 0314, "cz", -0, D16OP, 0304, "cnz", -0, D16OP, 0364, "cp", -0, D16OP, 0374, "cm", -0, D16OP, 0354, "cpe", -0, D16OP, 0344, "cpo", -0, NOOPOP, 0311, "ret", -0, NOOPOP, 0330, "rc", -0, NOOPOP, 0320, "rnc", -0, NOOPOP, 0310, "rz", -0, NOOPOP, 0300, "rnz", -0, NOOPOP, 0360, "rp", -0, NOOPOP, 0370, "rm", -0, NOOPOP, 0350, "rpe", -0, NOOPOP, 0340, "rpo", -0, RST, 0307, "rst", -0, D8OP, 0333, "in", -0, D8OP, 0323, "out", -0, LXI, 0001, "lxi", -0, R16OP, 0305, "push", -0, R16OP, 0301, "pop", -0, D16OP, 0062, "sta", -0, D16OP, 0072, "lda", -0, NOOPOP, 0353, "xchg", -0, NOOPOP, 0343, "xthl", -0, NOOPOP, 0371, "sphl", -0, NOOPOP, 0351, "pchl", -0, R16OP, 0011, "dad", -0, STLDAX, 0002, "stax", -0, STLDAX, 0012, "ldax", -0, R16OP, 0003, "inx", -0, MOV, 0100, "mov", -0, NOOPOP, 0166, "hlt", -0, MVI, 0006, "mvi", -0, DSTOP, 0004, "inr", -0, DSTOP, 0005, "dcr", -0, SRCOP, 0200, "add", -0, SRCOP, 0210, "adc", -0, SRCOP, 0220, "sub", -0, SRCOP, 0230, "sbb", -0, SRCOP, 0240, "ana", -0, SRCOP, 0250, "xra", -0, SRCOP, 0260, "ora", -0, SRCOP, 0270, "cmp", -0, D8OP, 0306, "adi", -0, D8OP, 0316, "aci", -0, D8OP, 0326, "sui", -0, D8OP, 0336, "sbi", -0, D8OP, 0346, "ani", -0, D8OP, 0356, "xri", -0, D8OP, 0366, "ori", -0, D8OP, 0376, "cpi", -0, NOOPOP, 0007, "rlc", -0, NOOPOP, 0017, "rrc", -0, NOOPOP, 0027, "ral", -0, NOOPOP, 0037, "rar", -0, D16OP, 0303, "jmp", -0, D16OP, 0332, "jc", -0, D16OP, 0322, "jnc", -0, D16OP, 0312, "jz", -0, D16OP, 0302, "jnz", -0, D16OP, 0362, "jp", -0, D16OP, 0372, "jm", -0, D16OP, 0352, "jpe", -0, D16OP, 0342, "jpo", -0, R16OP, 0013, "dcx", -0, NOOPOP, 0057, "cma", -0, NOOPOP, 0067, "stc", -0, NOOPOP, 0077, "cmc", -0, NOOPOP, 0047, "daa", -0, D16OP, 0042, "shld", -0, D16OP, 0052, "lhld", -0, NOOPOP, 0373, "ei", -0, NOOPOP, 0363, "di", -0, NOOPOP, 0000, "nop", -0, NOOPOP, 0040, "rim", /* 8085 */ -0, NOOPOP, 0060, "sim", /* 8085 */ +{0, REG, B, "b"}, +{0, REG, C, "c"}, +{0, REG, D, "d"}, +{0, REG, E, "e"}, +{0, REG, H, "h"}, +{0, REG, L, "l"}, +{0, REG, M, "m"}, +{0, REG, A, "a"}, +{0, REG, SP, "sp"}, +{0, REG, PSW, "psw"}, +{0, D16OP, 0315, "call"}, +{0, D16OP, 0334, "cc"}, +{0, D16OP, 0324, "cnc"}, +{0, D16OP, 0314, "cz"}, +{0, D16OP, 0304, "cnz"}, +{0, D16OP, 0364, "cp"}, +{0, D16OP, 0374, "cm"}, +{0, D16OP, 0354, "cpe"}, +{0, D16OP, 0344, "cpo"}, +{0, NOOPOP, 0311, "ret"}, +{0, NOOPOP, 0330, "rc"}, +{0, NOOPOP, 0320, "rnc"}, +{0, NOOPOP, 0310, "rz"}, +{0, NOOPOP, 0300, "rnz"}, +{0, NOOPOP, 0360, "rp"}, +{0, NOOPOP, 0370, "rm"}, +{0, NOOPOP, 0350, "rpe"}, +{0, NOOPOP, 0340, "rpo"}, +{0, RST, 0307, "rst"}, +{0, D8OP, 0333, "in"}, +{0, D8OP, 0323, "out"}, +{0, LXI, 0001, "lxi"}, +{0, R16OP, 0305, "push"}, +{0, R16OP, 0301, "pop"}, +{0, D16OP, 0062, "sta"}, +{0, D16OP, 0072, "lda"}, +{0, NOOPOP, 0353, "xchg"}, +{0, NOOPOP, 0343, "xthl"}, +{0, NOOPOP, 0371, "sphl"}, +{0, NOOPOP, 0351, "pchl"}, +{0, R16OP, 0011, "dad"}, +{0, STLDAX, 0002, "stax"}, +{0, STLDAX, 0012, "ldax"}, +{0, R16OP, 0003, "inx"}, +{0, MOV, 0100, "mov"}, +{0, NOOPOP, 0166, "hlt"}, +{0, MVI, 0006, "mvi"}, +{0, DSTOP, 0004, "inr"}, +{0, DSTOP, 0005, "dcr"}, +{0, SRCOP, 0200, "add"}, +{0, SRCOP, 0210, "adc"}, +{0, SRCOP, 0220, "sub"}, +{0, SRCOP, 0230, "sbb"}, +{0, SRCOP, 0240, "ana"}, +{0, SRCOP, 0250, "xra"}, +{0, SRCOP, 0260, "ora"}, +{0, SRCOP, 0270, "cmp"}, +{0, D8OP, 0306, "adi"}, +{0, D8OP, 0316, "aci"}, +{0, D8OP, 0326, "sui"}, +{0, D8OP, 0336, "sbi"}, +{0, D8OP, 0346, "ani"}, +{0, D8OP, 0356, "xri"}, +{0, D8OP, 0366, "ori"}, +{0, D8OP, 0376, "cpi"}, +{0, NOOPOP, 0007, "rlc"}, +{0, NOOPOP, 0017, "rrc"}, +{0, NOOPOP, 0027, "ral"}, +{0, NOOPOP, 0037, "rar"}, +{0, D16OP, 0303, "jmp"}, +{0, D16OP, 0332, "jc"}, +{0, D16OP, 0322, "jnc"}, +{0, D16OP, 0312, "jz"}, +{0, D16OP, 0302, "jnz"}, +{0, D16OP, 0362, "jp"}, +{0, D16OP, 0372, "jm"}, +{0, D16OP, 0352, "jpe"}, +{0, D16OP, 0342, "jpo"}, +{0, R16OP, 0013, "dcx"}, +{0, NOOPOP, 0057, "cma"}, +{0, NOOPOP, 0067, "stc"}, +{0, NOOPOP, 0077, "cmc"}, +{0, NOOPOP, 0047, "daa"}, +{0, D16OP, 0042, "shld"}, +{0, D16OP, 0052, "lhld"}, +{0, NOOPOP, 0373, "ei"}, +{0, NOOPOP, 0363, "di"}, +{0, NOOPOP, 0000, "nop"}, +{0, NOOPOP, 0040, "rim"}, /* 8085 */ +{0, NOOPOP, 0060, "sim"}, /* 8085 */ /* * The Intel 8085 has a set of instructions for high level language * support that were not originally documented. @@ -114,14 +114,14 @@ * check via A. RSTV is useful for runtimes where signed overflow is a * fault. */ -0, NOOPOP, 0010, "dsub", /* 8085 undoc HL = HL - BC */ -0, NOOPOP, 0020, "arhl", /* 8085 undoc HL arith right shift */ -0, NOOPOP, 0030, "rld", /* 8085 undoc rotate DE left thru carry */ +{0, NOOPOP, 0010, "dsub"}, /* 8085 undoc HL = HL - BC */ +{0, NOOPOP, 0020, "arhl"}, /* 8085 undoc HL arith right shift */ +{0, NOOPOP, 0030, "rld"}, /* 8085 undoc rotate DE left thru carry */ /* in effect ADC DE,DE */ -0, D8OP, 0050, "ldhi", /* DE = HL + imm8 */ -0, D8OP, 0070, "ldsi", /* DE = SP + imm8 */ -0, NOOPOP, 0313, "rstv", /* RST8 if V set */ -0, NOOPOP, 0331, "shlx", /* (DE) = HL */ -0, NOOPOP, 0355, "lhlx", /* HL = (DE) */ -0, D16OP, 0335, "jnk", /* Jump K clear */ -0, D16OP, 0375, "jk", /* Jump K set */ +{0, D8OP, 0050, "ldhi"}, /* DE = HL + imm8 */ +{0, D8OP, 0070, "ldsi"}, /* DE = SP + imm8 */ +{0, NOOPOP, 0313, "rstv"}, /* RST8 if V set */ +{0, NOOPOP, 0331, "shlx"}, /* (DE) = HL */ +{0, NOOPOP, 0355, "lhlx"}, /* HL = (DE) */ +{0, D16OP, 0335, "jnk"}, /* Jump K clear */ +{0, D16OP, 0375, "jk"}, /* Jump K set */ diff --git a/mach/i86/as/mach3.c b/mach/i86/as/mach3.c index 46f0f4855..6c54daa8b 100644 --- a/mach/i86/as/mach3.c +++ b/mach/i86/as/mach3.c @@ -8,330 +8,330 @@ * INTEL 8086 keywords */ -0, R16, 0, "ax", -0, R16, 1, "cx", -0, R16, 2, "dx", -0, R16, 3, "bx", -0, R16, 4, "sp", -0, R16, 5, "bp", -0, R16, 6, "si", -0, R16, 7, "di", -0, R8, 0, "al", -0, R8, 1, "cl", -0, R8, 2, "dl", -0, R8, 3, "bl", -0, R8, 4, "ah", -0, R8, 5, "ch", -0, R8, 6, "dh", -0, R8, 7, "bh", -0, RSEG, 0, "es", -0, RSEG, 1, "cs", -0, RSEG, 2, "ss", -0, RSEG, 3, "ds", -0, PREFIX, 046, "eseg", -0, PREFIX, 056, "cseg", -0, PREFIX, 066, "sseg", -0, PREFIX, 076, "dseg", -0, PREFIX, 0360, "lock", -0, PREFIX, 0363, "rep", -0, PREFIX, 0362, "repne", -0, PREFIX, 0362, "repnz", -0, PREFIX, 0363, "repe", -0, PREFIX, 0363, "repz", -0, NOOP_1, 047, "daa", -0, NOOP_1, 057, "das", -0, NOOP_1, 067, "aaa", -0, NOOP_1, 077, "aas", -0, NOOP_1, 0220, "nop", -0, NOOP_1, 0230, "cbw", -0, NOOP_1, 0231, "cwd", -0, NOOP_1, 0233, "wait", -0, NOOP_1, 0234, "pushf", -0, NOOP_1, 0235, "popf", -0, NOOP_1, 0236, "sahf", -0, NOOP_1, 0237, "lahf", -0, NOOP_1, 0244, "movsb", -0, NOOP_1, 0245, "movs", -0, NOOP_1, 0245, "movsw", -0, NOOP_1, 0246, "cmpsb", -0, NOOP_1, 0247, "cmps", -0, NOOP_1, 0247, "cmpsw", -0, NOOP_1, 0252, "stosb", -0, NOOP_1, 0253, "stos", -0, NOOP_1, 0253, "stosw", -0, NOOP_1, 0254, "lodsb", -0, NOOP_1, 0255, "lods", -0, NOOP_1, 0255, "lodsw", -0, NOOP_1, 0256, "scasb", -0, NOOP_1, 0257, "scas", -0, NOOP_1, 0257, "scasw", -0, NOOP_1, 0316, "into", -0, NOOP_1, 0317, "iret", -0, NOOP_1, 0327, "xlat", -0, NOOP_1, 0364, "hlt", -0, NOOP_1, 0365, "cmc", -0, NOOP_1, 0370, "clc", -0, NOOP_1, 0371, "stc", -0, NOOP_1, 0372, "cli", -0, NOOP_1, 0373, "sti", -0, NOOP_1, 0374, "cld", -0, NOOP_1, 0375, "std", -0, NOOP_2, 0324+012<<8, "aam", -0, NOOP_2, 0325+012<<8, "aad", -0, JOP, 0340, "loopne", -0, JOP, 0340, "loopnz", -0, JOP, 0341, "loope", -0, JOP, 0341, "loopz", -0, JOP, 0342, "loop", -0, JOP, 0343, "jcxz", -0, JOP, 0160, "jo", -0, JOP, 0161, "jno", -0, JOP, 0162, "jb", -0, JOP, 0162, "jc", -0, JOP, 0162, "jnae", -0, JOP, 0163, "jae", -0, JOP, 0163, "jnb", -0, JOP, 0163, "jnc", -0, JOP, 0164, "je", -0, JOP, 0164, "jz", -0, JOP, 0165, "jne", -0, JOP, 0165, "jnz", -0, JOP, 0166, "jbe", -0, JOP, 0166, "jna", -0, JOP, 0167, "ja", -0, JOP, 0167, "jnbe", -0, JOP, 0170, "js", -0, JOP, 0171, "jns", -0, JOP, 0172, "jp", -0, JOP, 0172, "jpe", -0, JOP, 0173, "jnp", -0, JOP, 0173, "jpo", -0, JOP, 0174, "jl", -0, JOP, 0174, "jnge", -0, JOP, 0175, "jge", -0, JOP, 0175, "jnl", -0, JOP, 0176, "jle", -0, JOP, 0176, "jng", -0, JOP, 0177, "jg", -0, JOP, 0177, "jnle", -0, PUSHOP, 0, "push", -0, PUSHOP, 1, "pop", -0, IOOP, 0344, "inb", -0, IOOP, 0345, "in", -0, IOOP, 0345, "inw", -0, IOOP, 0346, "outb", -0, IOOP, 0347, "out", -0, IOOP, 0347, "outw", -0, ADDOP, 000, "addb", -0, ADDOP, 001, "add", -0, ADDOP, 010, "orb", -0, ADDOP, 011, "or", -0, ADDOP, 020, "adcb", -0, ADDOP, 021, "adc", -0, ADDOP, 030, "sbbb", -0, ADDOP, 031, "sbb", -0, ADDOP, 040, "andb", -0, ADDOP, 041, "and", -0, ADDOP, 050, "subb", -0, ADDOP, 051, "sub", -0, ADDOP, 060, "xorb", -0, ADDOP, 061, "xor", -0, ADDOP, 070, "cmpb", -0, ADDOP, 071, "cmp", -0, ROLOP, 000, "rolb", -0, ROLOP, 001, "rol", -0, ROLOP, 010, "rorb", -0, ROLOP, 011, "ror", -0, ROLOP, 020, "rclb", -0, ROLOP, 021, "rcl", -0, ROLOP, 030, "rcrb", -0, ROLOP, 031, "rcr", -0, ROLOP, 040, "salb", -0, ROLOP, 040, "shlb", -0, ROLOP, 041, "sal", -0, ROLOP, 041, "shl", -0, ROLOP, 050, "shrb", -0, ROLOP, 051, "shr", -0, ROLOP, 070, "sarb", -0, ROLOP, 071, "sar", -0, INCOP, 000, "incb", -0, INCOP, 001, "inc", -0, INCOP, 010, "decb", -0, INCOP, 011, "dec", -0, NOTOP, 020, "notb", -0, NOTOP, 021, "not", -0, NOTOP, 030, "negb", -0, NOTOP, 031, "neg", -0, NOTOP, 040, "mulb", -0, NOTOP, 041, "mul", -0, NOTOP, 050, "imulb", -0, IMUL, 051, "imul", /* for 80286 */ -0, NOTOP, 060, "divb", -0, NOTOP, 061, "div", -0, NOTOP, 070, "idivb", -0, NOTOP, 071, "idiv", -0, CALLOP, 020+(0350<<8), "call", -0, CALLOP, 040+(0351<<8), "jmp", -0, CALFOP, 030+(0232<<8), "callf", -0, CALFOP, 050+(0352<<8), "jmpf", -0, LEAOP, 0215, "lea", -0, LEAOP, 0304, "les", -0, LEAOP, 0305, "lds", -0, ESC, 0, "esc", -0, INT, 0, "int", -0, RET, 0303, "ret", -0, RET, 0313, "retf", -0, XCHG, 0, "xchgb", -0, XCHG, 1, "xchg", -0, TEST, 0, "testb", -0, TEST, 1, "test", -0, MOV, 0, "movb", -0, MOV, 1, "mov", -0, MOV, 1, "movw", +{0, R16, 0, "ax"}, +{0, R16, 1, "cx"}, +{0, R16, 2, "dx"}, +{0, R16, 3, "bx"}, +{0, R16, 4, "sp"}, +{0, R16, 5, "bp"}, +{0, R16, 6, "si"}, +{0, R16, 7, "di"}, +{0, R8, 0, "al"}, +{0, R8, 1, "cl"}, +{0, R8, 2, "dl"}, +{0, R8, 3, "bl"}, +{0, R8, 4, "ah"}, +{0, R8, 5, "ch"}, +{0, R8, 6, "dh"}, +{0, R8, 7, "bh"}, +{0, RSEG, 0, "es"}, +{0, RSEG, 1, "cs"}, +{0, RSEG, 2, "ss"}, +{0, RSEG, 3, "ds"}, +{0, PREFIX, 046, "eseg"}, +{0, PREFIX, 056, "cseg"}, +{0, PREFIX, 066, "sseg"}, +{0, PREFIX, 076, "dseg"}, +{0, PREFIX, 0360, "lock"}, +{0, PREFIX, 0363, "rep"}, +{0, PREFIX, 0362, "repne"}, +{0, PREFIX, 0362, "repnz"}, +{0, PREFIX, 0363, "repe"}, +{0, PREFIX, 0363, "repz"}, +{0, NOOP_1, 047, "daa"}, +{0, NOOP_1, 057, "das"}, +{0, NOOP_1, 067, "aaa"}, +{0, NOOP_1, 077, "aas"}, +{0, NOOP_1, 0220, "nop"}, +{0, NOOP_1, 0230, "cbw"}, +{0, NOOP_1, 0231, "cwd"}, +{0, NOOP_1, 0233, "wait"}, +{0, NOOP_1, 0234, "pushf"}, +{0, NOOP_1, 0235, "popf"}, +{0, NOOP_1, 0236, "sahf"}, +{0, NOOP_1, 0237, "lahf"}, +{0, NOOP_1, 0244, "movsb"}, +{0, NOOP_1, 0245, "movs"}, +{0, NOOP_1, 0245, "movsw"}, +{0, NOOP_1, 0246, "cmpsb"}, +{0, NOOP_1, 0247, "cmps"}, +{0, NOOP_1, 0247, "cmpsw"}, +{0, NOOP_1, 0252, "stosb"}, +{0, NOOP_1, 0253, "stos"}, +{0, NOOP_1, 0253, "stosw"}, +{0, NOOP_1, 0254, "lodsb"}, +{0, NOOP_1, 0255, "lods"}, +{0, NOOP_1, 0255, "lodsw"}, +{0, NOOP_1, 0256, "scasb"}, +{0, NOOP_1, 0257, "scas"}, +{0, NOOP_1, 0257, "scasw"}, +{0, NOOP_1, 0316, "into"}, +{0, NOOP_1, 0317, "iret"}, +{0, NOOP_1, 0327, "xlat"}, +{0, NOOP_1, 0364, "hlt"}, +{0, NOOP_1, 0365, "cmc"}, +{0, NOOP_1, 0370, "clc"}, +{0, NOOP_1, 0371, "stc"}, +{0, NOOP_1, 0372, "cli"}, +{0, NOOP_1, 0373, "sti"}, +{0, NOOP_1, 0374, "cld"}, +{0, NOOP_1, 0375, "std"}, +{0, NOOP_2, 0324+012<<8, "aam"}, +{0, NOOP_2, 0325+012<<8, "aad"}, +{0, JOP, 0340, "loopne"}, +{0, JOP, 0340, "loopnz"}, +{0, JOP, 0341, "loope"}, +{0, JOP, 0341, "loopz"}, +{0, JOP, 0342, "loop"}, +{0, JOP, 0343, "jcxz"}, +{0, JOP, 0160, "jo"}, +{0, JOP, 0161, "jno"}, +{0, JOP, 0162, "jb"}, +{0, JOP, 0162, "jc"}, +{0, JOP, 0162, "jnae"}, +{0, JOP, 0163, "jae"}, +{0, JOP, 0163, "jnb"}, +{0, JOP, 0163, "jnc"}, +{0, JOP, 0164, "je"}, +{0, JOP, 0164, "jz"}, +{0, JOP, 0165, "jne"}, +{0, JOP, 0165, "jnz"}, +{0, JOP, 0166, "jbe"}, +{0, JOP, 0166, "jna"}, +{0, JOP, 0167, "ja"}, +{0, JOP, 0167, "jnbe"}, +{0, JOP, 0170, "js"}, +{0, JOP, 0171, "jns"}, +{0, JOP, 0172, "jp"}, +{0, JOP, 0172, "jpe"}, +{0, JOP, 0173, "jnp"}, +{0, JOP, 0173, "jpo"}, +{0, JOP, 0174, "jl"}, +{0, JOP, 0174, "jnge"}, +{0, JOP, 0175, "jge"}, +{0, JOP, 0175, "jnl"}, +{0, JOP, 0176, "jle"}, +{0, JOP, 0176, "jng"}, +{0, JOP, 0177, "jg"}, +{0, JOP, 0177, "jnle"}, +{0, PUSHOP, 0, "push"}, +{0, PUSHOP, 1, "pop"}, +{0, IOOP, 0344, "inb"}, +{0, IOOP, 0345, "in"}, +{0, IOOP, 0345, "inw"}, +{0, IOOP, 0346, "outb"}, +{0, IOOP, 0347, "out"}, +{0, IOOP, 0347, "outw"}, +{0, ADDOP, 000, "addb"}, +{0, ADDOP, 001, "add"}, +{0, ADDOP, 010, "orb"}, +{0, ADDOP, 011, "or"}, +{0, ADDOP, 020, "adcb"}, +{0, ADDOP, 021, "adc"}, +{0, ADDOP, 030, "sbbb"}, +{0, ADDOP, 031, "sbb"}, +{0, ADDOP, 040, "andb"}, +{0, ADDOP, 041, "and"}, +{0, ADDOP, 050, "subb"}, +{0, ADDOP, 051, "sub"}, +{0, ADDOP, 060, "xorb"}, +{0, ADDOP, 061, "xor"}, +{0, ADDOP, 070, "cmpb"}, +{0, ADDOP, 071, "cmp"}, +{0, ROLOP, 000, "rolb"}, +{0, ROLOP, 001, "rol"}, +{0, ROLOP, 010, "rorb"}, +{0, ROLOP, 011, "ror"}, +{0, ROLOP, 020, "rclb"}, +{0, ROLOP, 021, "rcl"}, +{0, ROLOP, 030, "rcrb"}, +{0, ROLOP, 031, "rcr"}, +{0, ROLOP, 040, "salb"}, +{0, ROLOP, 040, "shlb"}, +{0, ROLOP, 041, "sal"}, +{0, ROLOP, 041, "shl"}, +{0, ROLOP, 050, "shrb"}, +{0, ROLOP, 051, "shr"}, +{0, ROLOP, 070, "sarb"}, +{0, ROLOP, 071, "sar"}, +{0, INCOP, 000, "incb"}, +{0, INCOP, 001, "inc"}, +{0, INCOP, 010, "decb"}, +{0, INCOP, 011, "dec"}, +{0, NOTOP, 020, "notb"}, +{0, NOTOP, 021, "not"}, +{0, NOTOP, 030, "negb"}, +{0, NOTOP, 031, "neg"}, +{0, NOTOP, 040, "mulb"}, +{0, NOTOP, 041, "mul"}, +{0, NOTOP, 050, "imulb"}, +{0, IMUL, 051, "imul"}, /* for 80286 */ +{0, NOTOP, 060, "divb"}, +{0, NOTOP, 061, "div"}, +{0, NOTOP, 070, "idivb"}, +{0, NOTOP, 071, "idiv"}, +{0, CALLOP, 020+(0350<<8), "call"}, +{0, CALLOP, 040+(0351<<8), "jmp"}, +{0, CALFOP, 030+(0232<<8), "callf"}, +{0, CALFOP, 050+(0352<<8), "jmpf"}, +{0, LEAOP, 0215, "lea"}, +{0, LEAOP, 0304, "les"}, +{0, LEAOP, 0305, "lds"}, +{0, ESC, 0, "esc"}, +{0, INT, 0, "int"}, +{0, RET, 0303, "ret"}, +{0, RET, 0313, "retf"}, +{0, XCHG, 0, "xchgb"}, +{0, XCHG, 1, "xchg"}, +{0, TEST, 0, "testb"}, +{0, TEST, 1, "test"}, +{0, MOV, 0, "movb"}, +{0, MOV, 1, "mov"}, +{0, MOV, 1, "movw"}, /* Intel 8087 coprocessor keywords */ -0, ST, 0, "st", +{0, ST, 0, "st"}, -0, FNOOP, FESC+1+(0xF0<<8), "f2xm1", -0, FNOOP, FESC+1+(0xE1<<8), "fabs", -0, FNOOP, FESC+1+(0xE0<<8), "fchs", -0, FNOOP, FESC+3+(0xE2<<8), "fclex", -0, FNOOP, FESC+6+(0xD9<<8), "fcompp", -0, FNOOP, FESC+1+(0xF6<<8), "fdecstp", -0, FNOOP, FESC+3+(0xE1<<8), "fdisi", -0, FNOOP, FESC+3+(0xE0<<8), "feni", -0, FNOOP, FESC+1+(0xF7<<8), "fincstp", -0, FNOOP, FESC+3+(0xE3<<8), "finit", -0, FNOOP, FESC+1+(0xE8<<8), "fld1", -0, FNOOP, FESC+1+(0xEA<<8), "fldl2e", -0, FNOOP, FESC+1+(0xE9<<8), "fldl2t", -0, FNOOP, FESC+1+(0xEC<<8), "fldlg2", -0, FNOOP, FESC+1+(0xED<<8), "fldln2", -0, FNOOP, FESC+1+(0xEB<<8), "fldpi", -0, FNOOP, FESC+1+(0xEE<<8), "fldz", -0, FNOOP, FESC+1+(0xD0<<8), "fnop", -0, FNOOP, FESC+1+(0xF3<<8), "fpatan", -0, FNOOP, FESC+1+(0xF8<<8), "fprem", -0, FNOOP, FESC+1+(0xF2<<8), "fptan", -0, FNOOP, FESC+1+(0xFC<<8), "frndint", -0, FNOOP, FESC+1+(0xFD<<8), "fscale", -0, FNOOP, FESC+1+(0xFA<<8), "fsqrt", -0, FNOOP, FESC+7+(0xE0<<8), "fstswax", /* 80287 */ -0, FNOOP, FESC+1+(0xE4<<8), "ftst", -0, FNOOP, FESC+1+(0xE5<<8), "fxam", -0, FNOOP, FESC+1+(0xF4<<8), "fxtract", -0, FNOOP, FESC+1+(0xF1<<8), "fyl2x", -0, FNOOP, FESC+1+(0xF9<<8), "fyl2pi", +{0, FNOOP, FESC+1+(0xF0<<8), "f2xm1"}, +{0, FNOOP, FESC+1+(0xE1<<8), "fabs"}, +{0, FNOOP, FESC+1+(0xE0<<8), "fchs"}, +{0, FNOOP, FESC+3+(0xE2<<8), "fclex"}, +{0, FNOOP, FESC+6+(0xD9<<8), "fcompp"}, +{0, FNOOP, FESC+1+(0xF6<<8), "fdecstp"}, +{0, FNOOP, FESC+3+(0xE1<<8), "fdisi"}, +{0, FNOOP, FESC+3+(0xE0<<8), "feni"}, +{0, FNOOP, FESC+1+(0xF7<<8), "fincstp"}, +{0, FNOOP, FESC+3+(0xE3<<8), "finit"}, +{0, FNOOP, FESC+1+(0xE8<<8), "fld1"}, +{0, FNOOP, FESC+1+(0xEA<<8), "fldl2e"}, +{0, FNOOP, FESC+1+(0xE9<<8), "fldl2t"}, +{0, FNOOP, FESC+1+(0xEC<<8), "fldlg2"}, +{0, FNOOP, FESC+1+(0xED<<8), "fldln2"}, +{0, FNOOP, FESC+1+(0xEB<<8), "fldpi"}, +{0, FNOOP, FESC+1+(0xEE<<8), "fldz"}, +{0, FNOOP, FESC+1+(0xD0<<8), "fnop"}, +{0, FNOOP, FESC+1+(0xF3<<8), "fpatan"}, +{0, FNOOP, FESC+1+(0xF8<<8), "fprem"}, +{0, FNOOP, FESC+1+(0xF2<<8), "fptan"}, +{0, FNOOP, FESC+1+(0xFC<<8), "frndint"}, +{0, FNOOP, FESC+1+(0xFD<<8), "fscale"}, +{0, FNOOP, FESC+1+(0xFA<<8), "fsqrt"}, +{0, FNOOP, FESC+7+(0xE0<<8), "fstswax"}, /* 80287 */ +{0, FNOOP, FESC+1+(0xE4<<8), "ftst"}, +{0, FNOOP, FESC+1+(0xE5<<8), "fxam"}, +{0, FNOOP, FESC+1+(0xF4<<8), "fxtract"}, +{0, FNOOP, FESC+1+(0xF1<<8), "fyl2x"}, +{0, FNOOP, FESC+1+(0xF9<<8), "fyl2pi"}, -0, FMEM, FESC+6+(0<<11), "fiadds", -0, FMEM, FESC+2+(0<<11), "fiaddl", -0, FMEM, FESC+0+(0<<11), "fadds", -0, FMEM, FESC+4+(0<<11), "faddd", -0, FMEM, FESC+7+(4<<11), "fbld", -0, FMEM, FESC+7+(6<<11), "fbstp", -0, FMEM, FESC+6+(2<<11), "ficoms", -0, FMEM, FESC+2+(2<<11), "ficoml", -0, FMEM, FESC+0+(2<<11), "fcoms", -0, FMEM, FESC+4+(2<<11), "fcomd", -0, FMEM, FESC+6+(3<<11), "ficomps", -0, FMEM, FESC+2+(3<<11), "ficompl", -0, FMEM, FESC+0+(3<<11), "fcomps", -0, FMEM, FESC+4+(3<<11), "fcompd", -0, FMEM, FESC+6+(6<<11), "fidivs", -0, FMEM, FESC+2+(6<<11), "fidivl", -0, FMEM, FESC+0+(6<<11), "fdivs", -0, FMEM, FESC+4+(6<<11), "fdivd", -0, FMEM, FESC+6+(7<<11), "fidivrs", -0, FMEM, FESC+2+(7<<11), "fidivrl", -0, FMEM, FESC+0+(7<<11), "fdivrs", -0, FMEM, FESC+4+(7<<11), "fdivrd", -0, FMEM, FESC+7+(5<<11), "fildq", -0, FMEM, FESC+7+(0<<11), "filds", -0, FMEM, FESC+3+(0<<11), "fildl", -0, FMEM, FESC+1+(0<<11), "flds", -0, FMEM, FESC+5+(0<<11), "fldd", -0, FMEM, FESC+3+(5<<11), "fldx", -0, FMEM, FESC+1+(5<<11), "fldcw", -0, FMEM, FESC+1+(4<<11), "fldenv", -0, FMEM, FESC+6+(1<<11), "fimuls", -0, FMEM, FESC+2+(1<<11), "fimull", -0, FMEM, FESC+0+(1<<11), "fmuls", -0, FMEM, FESC+4+(1<<11), "fmuld", -0, FMEM, FESC+5+(4<<11), "frstor", -0, FMEM, FESC+5+(6<<11), "fsave", -0, FMEM, FESC+7+(2<<11), "fists", -0, FMEM, FESC+3+(2<<11), "fistl", -0, FMEM, FESC+1+(2<<11), "fsts", -0, FMEM, FESC+5+(2<<11), "fstd", -0, FMEM, FESC+7+(7<<11), "fistpq", -0, FMEM, FESC+7+(3<<11), "fistps", -0, FMEM, FESC+3+(3<<11), "fistpl", -0, FMEM, FESC+1+(3<<11), "fstps", -0, FMEM, FESC+5+(3<<11), "fstpd", -0, FMEM, FESC+3+(7<<11), "fstpx", -0, FMEM, FESC+1+(7<<11), "fstcw", -0, FMEM, FESC+1+(6<<11), "fstenv", -0, FMEM, FESC+5+(7<<11), "fstsw", -0, FMEM, FESC+6+(4<<11), "fisubs", -0, FMEM, FESC+2+(4<<11), "fisubl", -0, FMEM, FESC+0+(4<<11), "fsubs", -0, FMEM, FESC+4+(4<<11), "fsubd", -0, FMEM, FESC+6+(5<<11), "fisubrs", -0, FMEM, FESC+2+(5<<11), "fisubrl", -0, FMEM, FESC+0+(5<<11), "fsubrs", -0, FMEM, FESC+4+(5<<11), "fsubrd", +{0, FMEM, FESC+6+(0<<11), "fiadds"}, +{0, FMEM, FESC+2+(0<<11), "fiaddl"}, +{0, FMEM, FESC+0+(0<<11), "fadds"}, +{0, FMEM, FESC+4+(0<<11), "faddd"}, +{0, FMEM, FESC+7+(4<<11), "fbld"}, +{0, FMEM, FESC+7+(6<<11), "fbstp"}, +{0, FMEM, FESC+6+(2<<11), "ficoms"}, +{0, FMEM, FESC+2+(2<<11), "ficoml"}, +{0, FMEM, FESC+0+(2<<11), "fcoms"}, +{0, FMEM, FESC+4+(2<<11), "fcomd"}, +{0, FMEM, FESC+6+(3<<11), "ficomps"}, +{0, FMEM, FESC+2+(3<<11), "ficompl"}, +{0, FMEM, FESC+0+(3<<11), "fcomps"}, +{0, FMEM, FESC+4+(3<<11), "fcompd"}, +{0, FMEM, FESC+6+(6<<11), "fidivs"}, +{0, FMEM, FESC+2+(6<<11), "fidivl"}, +{0, FMEM, FESC+0+(6<<11), "fdivs"}, +{0, FMEM, FESC+4+(6<<11), "fdivd"}, +{0, FMEM, FESC+6+(7<<11), "fidivrs"}, +{0, FMEM, FESC+2+(7<<11), "fidivrl"}, +{0, FMEM, FESC+0+(7<<11), "fdivrs"}, +{0, FMEM, FESC+4+(7<<11), "fdivrd"}, +{0, FMEM, FESC+7+(5<<11), "fildq"}, +{0, FMEM, FESC+7+(0<<11), "filds"}, +{0, FMEM, FESC+3+(0<<11), "fildl"}, +{0, FMEM, FESC+1+(0<<11), "flds"}, +{0, FMEM, FESC+5+(0<<11), "fldd"}, +{0, FMEM, FESC+3+(5<<11), "fldx"}, +{0, FMEM, FESC+1+(5<<11), "fldcw"}, +{0, FMEM, FESC+1+(4<<11), "fldenv"}, +{0, FMEM, FESC+6+(1<<11), "fimuls"}, +{0, FMEM, FESC+2+(1<<11), "fimull"}, +{0, FMEM, FESC+0+(1<<11), "fmuls"}, +{0, FMEM, FESC+4+(1<<11), "fmuld"}, +{0, FMEM, FESC+5+(4<<11), "frstor"}, +{0, FMEM, FESC+5+(6<<11), "fsave"}, +{0, FMEM, FESC+7+(2<<11), "fists"}, +{0, FMEM, FESC+3+(2<<11), "fistl"}, +{0, FMEM, FESC+1+(2<<11), "fsts"}, +{0, FMEM, FESC+5+(2<<11), "fstd"}, +{0, FMEM, FESC+7+(7<<11), "fistpq"}, +{0, FMEM, FESC+7+(3<<11), "fistps"}, +{0, FMEM, FESC+3+(3<<11), "fistpl"}, +{0, FMEM, FESC+1+(3<<11), "fstps"}, +{0, FMEM, FESC+5+(3<<11), "fstpd"}, +{0, FMEM, FESC+3+(7<<11), "fstpx"}, +{0, FMEM, FESC+1+(7<<11), "fstcw"}, +{0, FMEM, FESC+1+(6<<11), "fstenv"}, +{0, FMEM, FESC+5+(7<<11), "fstsw"}, +{0, FMEM, FESC+6+(4<<11), "fisubs"}, +{0, FMEM, FESC+2+(4<<11), "fisubl"}, +{0, FMEM, FESC+0+(4<<11), "fsubs"}, +{0, FMEM, FESC+4+(4<<11), "fsubd"}, +{0, FMEM, FESC+6+(5<<11), "fisubrs"}, +{0, FMEM, FESC+2+(5<<11), "fisubrl"}, +{0, FMEM, FESC+0+(5<<11), "fsubrs"}, +{0, FMEM, FESC+4+(5<<11), "fsubrd"}, -0, FST_I, FESC+1+(0xC0<<8), "fld", -0, FST_I, FESC+5+(0xD0<<8), "fst", -0, FST_I, FESC+5+(0xC8<<8), "fstp", -0, FST_I, FESC+1+(0xC8<<8), "fxch", -0, FST_I, FESC+0+(0xD0<<8), "fcom", -0, FST_I, FESC+0+(0xD8<<8), "fcomp", -0, FST_I, FESC+5+(0xC0<<8), "ffree", +{0, FST_I, FESC+1+(0xC0<<8), "fld"}, +{0, FST_I, FESC+5+(0xD0<<8), "fst"}, +{0, FST_I, FESC+5+(0xC8<<8), "fstp"}, +{0, FST_I, FESC+1+(0xC8<<8), "fxch"}, +{0, FST_I, FESC+0+(0xD0<<8), "fcom"}, +{0, FST_I, FESC+0+(0xD8<<8), "fcomp"}, +{0, FST_I, FESC+5+(0xC0<<8), "ffree"}, -0, FST_ST, FESC+0+(0xC0<<8), "fadd", -0, FST_ST, FESC+2+(0xC0<<8), "faddp", -0, FST_ST2, FESC+0+(0xF0<<8), "fdiv", -0, FST_ST2, FESC+2+(0xF0<<8), "fdivp", -0, FST_ST2, FESC+0+(0xF8<<8), "fdivr", -0, FST_ST2, FESC+2+(0xF8<<8), "fdivrp", -0, FST_ST, FESC+0+(0xC8<<8), "fmul", -0, FST_ST, FESC+2+(0xC8<<8), "fmulp", -0, FST_ST2, FESC+0+(0xE0<<8), "fsub", -0, FST_ST2, FESC+2+(0xE0<<8), "fsubp", -0, FST_ST2, FESC+0+(0xE8<<8), "fsubr", -0, FST_ST2, FESC+2+(0xE8<<8), "fsubrp", +{0, FST_ST, FESC+0+(0xC0<<8), "fadd"}, +{0, FST_ST, FESC+2+(0xC0<<8), "faddp"}, +{0, FST_ST2, FESC+0+(0xF0<<8), "fdiv"}, +{0, FST_ST2, FESC+2+(0xF0<<8), "fdivp"}, +{0, FST_ST2, FESC+0+(0xF8<<8), "fdivr"}, +{0, FST_ST2, FESC+2+(0xF8<<8), "fdivrp"}, +{0, FST_ST, FESC+0+(0xC8<<8), "fmul"}, +{0, FST_ST, FESC+2+(0xC8<<8), "fmulp"}, +{0, FST_ST2, FESC+0+(0xE0<<8), "fsub"}, +{0, FST_ST2, FESC+2+(0xE0<<8), "fsubp"}, +{0, FST_ST2, FESC+0+(0xE8<<8), "fsubr"}, +{0, FST_ST2, FESC+2+(0xE8<<8), "fsubrp"}, /* 80286 keywords */ -0, NOOP_1, 0140, "pusha", -0, NOOP_1, 0141, "popa", -0, NOOP_1, 0154, "insb", -0, NOOP_1, 0155, "ins", -0, NOOP_1, 0155, "insw", -0, NOOP_1, 0156, "outsb", -0, NOOP_1, 0157, "outs", -0, NOOP_1, 0157, "outsw", +{0, NOOP_1, 0140, "pusha"}, +{0, NOOP_1, 0141, "popa"}, +{0, NOOP_1, 0154, "insb"}, +{0, NOOP_1, 0155, "ins"}, +{0, NOOP_1, 0155, "insw"}, +{0, NOOP_1, 0156, "outsb"}, +{0, NOOP_1, 0157, "outs"}, +{0, NOOP_1, 0157, "outsw"}, -0, ARPLOP, 0143, "arpl", -0, ENTER, 0310, "enter", -0, NOOP_1, 0311, "leave", -0, LEAOP, 0142, "bound", +{0, ARPLOP, 0143, "arpl"}, +{0, ENTER, 0310, "enter"}, +{0, NOOP_1, 0311, "leave"}, +{0, LEAOP, 0142, "bound"}, -0, NOOP_2, 017+06<<8, "clts", +{0, NOOP_2, 017+06<<8, "clts"}, -0, EXTOP, 0002, "lar", -0, EXTOP, 0003, "lsl", +{0, EXTOP, 0002, "lar"}, +{0, EXTOP, 0003, "lsl"}, -0, EXTOP1, 0021, "lgdt", -0, EXTOP1, 0001, "sgdt", -0, EXTOP1, 0031, "lidt", -0, EXTOP1, 0011, "sidt", -0, EXTOP1, 0020, "lldt", -0, EXTOP1, 0000, "sldt", -0, EXTOP1, 0030, "ltr", -0, EXTOP1, 0010, "str", -0, EXTOP1, 0061, "lmsw", -0, EXTOP1, 0041, "smsw", -0, EXTOP1, 0050, "verw", -0, EXTOP1, 0040, "verr", +{0, EXTOP1, 0021, "lgdt"}, +{0, EXTOP1, 0001, "sgdt"}, +{0, EXTOP1, 0031, "lidt"}, +{0, EXTOP1, 0011, "sidt"}, +{0, EXTOP1, 0020, "lldt"}, +{0, EXTOP1, 0000, "sldt"}, +{0, EXTOP1, 0030, "ltr"}, +{0, EXTOP1, 0010, "str"}, +{0, EXTOP1, 0061, "lmsw"}, +{0, EXTOP1, 0041, "smsw"}, +{0, EXTOP1, 0050, "verw"}, +{0, EXTOP1, 0040, "verr"}, diff --git a/mach/m68020/as/mach3.c b/mach/m68020/as/mach3.c index 96f52d228..e77745707 100644 --- a/mach/m68020/as/mach3.c +++ b/mach/m68020/as/mach3.c @@ -7,460 +7,460 @@ * Motorola 68020 keywords */ -0, SIZE, SIZE_B, ".b", -0, SIZE, SIZE_W, ".w", -0, SIZE, SIZE_L, ".l", +{0, SIZE, SIZE_B, ".b"}, +{0, SIZE, SIZE_W, ".w"}, +{0, SIZE, SIZE_L, ".l"}, -0, DREG, 00, "d0", -0, DREG, 01, "d1", -0, DREG, 02, "d2", -0, DREG, 03, "d3", -0, DREG, 04, "d4", -0, DREG, 05, "d5", -0, DREG, 06, "d6", -0, DREG, 07, "d7", +{0, DREG, 00, "d0"}, +{0, DREG, 01, "d1"}, +{0, DREG, 02, "d2"}, +{0, DREG, 03, "d3"}, +{0, DREG, 04, "d4"}, +{0, DREG, 05, "d5"}, +{0, DREG, 06, "d6"}, +{0, DREG, 07, "d7"}, -0, AREG, 00, "a0", -0, AREG, 01, "a1", -0, AREG, 02, "a2", -0, AREG, 03, "a3", -0, AREG, 04, "a4", -0, AREG, 05, "a5", -0, AREG, 06, "a6", -0, AREG, 07, "a7", -0, AREG, 07, "sp", +{0, AREG, 00, "a0"}, +{0, AREG, 01, "a1"}, +{0, AREG, 02, "a2"}, +{0, AREG, 03, "a3"}, +{0, AREG, 04, "a4"}, +{0, AREG, 05, "a5"}, +{0, AREG, 06, "a6"}, +{0, AREG, 07, "a7"}, +{0, AREG, 07, "sp"}, -0, PC, 0, "pc", -0, PC, 0200, "zpc", +{0, PC, 0, "pc"}, +{0, PC, 0200, "zpc"}, -0, CREG, 04001, "vbr", -0, CREG, 0, "sfc", -0, CREG, 00001, "dfc", -0, CREG, 00002, "cacr", -0, CREG, 04002, "caar", -0, CREG, 04003, "msp", -0, CREG, 04004, "isp", +{0, CREG, 04001, "vbr"}, +{0, CREG, 0, "sfc"}, +{0, CREG, 00001, "dfc"}, +{0, CREG, 00002, "cacr"}, +{0, CREG, 04002, "caar"}, +{0, CREG, 04003, "msp"}, +{0, CREG, 04004, "isp"}, -0, SPEC, 075, "usp", -0, SPEC, 076, "ccr", -0, SPEC, 077, "sr", +{0, SPEC, 075, "usp"}, +{0, SPEC, 076, "ccr"}, +{0, SPEC, 077, "sr"}, -0, ABCD, 0140400, "abcd", -0, ABCD, 0100400, "sbcd", +{0, ABCD, 0140400, "abcd"}, +{0, ABCD, 0100400, "sbcd"}, -0, ADDX, 0150400, "addx", -0, ADDX, 0110400, "subx", +{0, ADDX, 0150400, "addx"}, +{0, ADDX, 0110400, "subx"}, -0, ADD, 0153300, "add", -0, ADD, 0112700, "sub", +{0, ADD, 0153300, "add"}, +{0, ADD, 0112700, "sub"}, -0, AND, 0141000, "and", -0, AND, 0135000, "eor", -0, AND, 0100000, "or", +{0, AND, 0141000, "and"}, +{0, AND, 0135000, "eor"}, +{0, AND, 0100000, "or"}, -0, BITOP, 0000, "btst", -0, BITOP, 0100, "bchg", -0, BITOP, 0200, "bclr", -0, BITOP, 0300, "bset", +{0, BITOP, 0000, "btst"}, +{0, BITOP, 0100, "bchg"}, +{0, BITOP, 0200, "bclr"}, +{0, BITOP, 0300, "bset"}, -0, BITFIELD, 0164300, "bftst", -0, BITFIELD, 0165300, "bfchg", -0, BITFIELD, 0166300, "bfclr", -0, BITFIELD, 0167300, "bfset", -0, BF_TO_D, 0164700, "bfextu", -0, BF_TO_D, 0164700, "bfexts", -0, BF_TO_D, 0164700, "bfffo", -0, BFINS, 0167700, "bfins", +{0, BITFIELD, 0164300, "bftst"}, +{0, BITFIELD, 0165300, "bfchg"}, +{0, BITFIELD, 0166300, "bfclr"}, +{0, BITFIELD, 0167300, "bfset"}, +{0, BF_TO_D, 0164700, "bfextu"}, +{0, BF_TO_D, 0164700, "bfexts"}, +{0, BF_TO_D, 0164700, "bfffo"}, +{0, BFINS, 0167700, "bfins"}, -0, SHIFT, 0160340, "asr", -0, SHIFT, 0160740, "asl", -0, SHIFT, 0161350, "lsr", -0, SHIFT, 0161750, "lsl", -0, SHIFT, 0162360, "roxr", -0, SHIFT, 0162760, "roxl", -0, SHIFT, 0163370, "ror", -0, SHIFT, 0163770, "rol", +{0, SHIFT, 0160340, "asr"}, +{0, SHIFT, 0160740, "asl"}, +{0, SHIFT, 0161350, "lsr"}, +{0, SHIFT, 0161750, "lsl"}, +{0, SHIFT, 0162360, "roxr"}, +{0, SHIFT, 0162760, "roxl"}, +{0, SHIFT, 0163370, "ror"}, +{0, SHIFT, 0163770, "rol"}, -0, SZ_EA, 041000|DTA|ALT, "clr", -0, SZ_EA, 042000|DTA|ALT, "neg", -0, SZ_EA, 040000|DTA|ALT, "negx", -0, SZ_EA, 043000|DTA|ALT, "not", -0, SZ_EA, 045000, "tst", +{0, SZ_EA, 041000|DTA|ALT, "clr"}, +{0, SZ_EA, 042000|DTA|ALT, "neg"}, +{0, SZ_EA, 040000|DTA|ALT, "negx"}, +{0, SZ_EA, 043000|DTA|ALT, "not"}, +{0, SZ_EA, 045000, "tst"}, -0, OP_EA, 044000|DTA|ALT, "nbcd", -0, OP_EA, 045300|DTA|ALT, "tas", -0, OP_EA, 047200|CTR, "jsr", -0, OP_EA, 047300|CTR, "jmp", -0, OP_EA, 044100|CTR, "pea", +{0, OP_EA, 044000|DTA|ALT, "nbcd"}, +{0, OP_EA, 045300|DTA|ALT, "tas"}, +{0, OP_EA, 047200|CTR, "jsr"}, +{0, OP_EA, 047300|CTR, "jmp"}, +{0, OP_EA, 044100|CTR, "pea"}, -0, OP_EA, 050300, "st", -0, OP_EA, 050700, "sf", -0, OP_EA, 051300, "shi", -0, OP_EA, 051700, "sls", -0, OP_EA, 052300, "scc", -0, OP_EA, 052700, "scs", -0, OP_EA, 053300, "sne", -0, OP_EA, 053700, "seq", -0, OP_EA, 054300, "svc", -0, OP_EA, 054700, "svs", -0, OP_EA, 055300, "spl", -0, OP_EA, 055700, "smi", -0, OP_EA, 056300, "sge", -0, OP_EA, 056700, "slt", -0, OP_EA, 057300, "sgt", -0, OP_EA, 057700, "sle", +{0, OP_EA, 050300, "st"}, +{0, OP_EA, 050700, "sf"}, +{0, OP_EA, 051300, "shi"}, +{0, OP_EA, 051700, "sls"}, +{0, OP_EA, 052300, "scc"}, +{0, OP_EA, 052700, "scs"}, +{0, OP_EA, 053300, "sne"}, +{0, OP_EA, 053700, "seq"}, +{0, OP_EA, 054300, "svc"}, +{0, OP_EA, 054700, "svs"}, +{0, OP_EA, 055300, "spl"}, +{0, OP_EA, 055700, "smi"}, +{0, OP_EA, 056300, "sge"}, +{0, OP_EA, 056700, "slt"}, +{0, OP_EA, 057300, "sgt"}, +{0, OP_EA, 057700, "sle"}, -0, OP_NOOP, 047160, "reset", -0, OP_NOOP, 047161, "nop", -0, OP_NOOP, 047163, "rte", -0, OP_NOOP, 047165, "rts", -0, OP_NOOP, 047166, "trapv", -0, OP_NOOP, 047167, "rtr", -0, OP_NOOP, 045374, "illegal", +{0, OP_NOOP, 047160, "reset"}, +{0, OP_NOOP, 047161, "nop"}, +{0, OP_NOOP, 047163, "rte"}, +{0, OP_NOOP, 047165, "rts"}, +{0, OP_NOOP, 047166, "trapv"}, +{0, OP_NOOP, 047167, "rtr"}, +{0, OP_NOOP, 045374, "illegal"}, -0, PACK, 0100500, "pack", -0, PACK, 0100600, "unpk", +{0, PACK, 0100500, "pack"}, +{0, PACK, 0100600, "unpk"}, -0, DIVMUL, 0100, "divu", -0, DIVMUL, 0101, "divs", -0, DIVMUL, 0000, "mulu", -0, DIVMUL, 0001, "muls", +{0, DIVMUL, 0100, "divu"}, +{0, DIVMUL, 0101, "divs"}, +{0, DIVMUL, 0000, "mulu"}, +{0, DIVMUL, 0001, "muls"}, -0, DIVL, 046100, "divul", -0, DIVL, 046101, "divsl", +{0, DIVL, 046100, "divul"}, +{0, DIVL, 046101, "divsl"}, -0, BR, 060000, "bra", -0, BR, 060400, "bsr", -0, BR, 061000, "bhi", -0, BR, 061400, "bls", -0, BR, 062000, "bcc", -0, BR, 062400, "bcs", -0, BR, 063000, "bne", -0, BR, 063400, "beq", -0, BR, 064000, "bvc", -0, BR, 064400, "bvs", -0, BR, 065000, "bpl", -0, BR, 065400, "bmi", -0, BR, 066000, "bge", -0, BR, 066400, "blt", -0, BR, 067000, "bgt", -0, BR, 067400, "ble", +{0, BR, 060000, "bra"}, +{0, BR, 060400, "bsr"}, +{0, BR, 061000, "bhi"}, +{0, BR, 061400, "bls"}, +{0, BR, 062000, "bcc"}, +{0, BR, 062400, "bcs"}, +{0, BR, 063000, "bne"}, +{0, BR, 063400, "beq"}, +{0, BR, 064000, "bvc"}, +{0, BR, 064400, "bvs"}, +{0, BR, 065000, "bpl"}, +{0, BR, 065400, "bmi"}, +{0, BR, 066000, "bge"}, +{0, BR, 066400, "blt"}, +{0, BR, 067000, "bgt"}, +{0, BR, 067400, "ble"}, -0, DBR, 050310, "dbt", -0, DBR, 050710, "dbf", -0, DBR, 050710, "dbra", -0, DBR, 051310, "dbhi", -0, DBR, 051710, "dbls", -0, DBR, 052310, "dbcc", -0, DBR, 052710, "dbcs", -0, DBR, 053310, "dbne", -0, DBR, 053710, "dbeq", -0, DBR, 054310, "dbvc", -0, DBR, 054710, "dbvs", -0, DBR, 055310, "dbpl", -0, DBR, 055710, "dbmi", -0, DBR, 056310, "dbge", -0, DBR, 056710, "dblt", -0, DBR, 057310, "dbgt", -0, DBR, 057710, "dble", +{0, DBR, 050310, "dbt"}, +{0, DBR, 050710, "dbf"}, +{0, DBR, 050710, "dbra"}, +{0, DBR, 051310, "dbhi"}, +{0, DBR, 051710, "dbls"}, +{0, DBR, 052310, "dbcc"}, +{0, DBR, 052710, "dbcs"}, +{0, DBR, 053310, "dbne"}, +{0, DBR, 053710, "dbeq"}, +{0, DBR, 054310, "dbvc"}, +{0, DBR, 054710, "dbvs"}, +{0, DBR, 055310, "dbpl"}, +{0, DBR, 055710, "dbmi"}, +{0, DBR, 056310, "dbge"}, +{0, DBR, 056710, "dblt"}, +{0, DBR, 057310, "dbgt"}, +{0, DBR, 057710, "dble"}, -0, OP_EXT, 044000, "ext", -0, OP_EXT, 044400, "extb", +{0, OP_EXT, 044000, "ext"}, +{0, OP_EXT, 044400, "extb"}, -0, OP_RANGE, 04000, "chk2", -0, OP_RANGE, 0, "cmp2", +{0, OP_RANGE, 04000, "chk2"}, +{0, OP_RANGE, 0, "cmp2"}, -0, TRAPCC, 050370, "trapt", -0, TRAPCC, 050770, "trapf", -0, TRAPCC, 051370, "traphi", -0, TRAPCC, 051770, "trapls", -0, TRAPCC, 052370, "trapcc", -0, TRAPCC, 052770, "trapcs", -0, TRAPCC, 053370, "trapeq", -0, TRAPCC, 053770, "trapvc", -0, TRAPCC, 054370, "trapvs", -0, TRAPCC, 054770, "trappl", -0, TRAPCC, 055370, "trapmi", -0, TRAPCC, 055770, "trapge", -0, TRAPCC, 056370, "traplt", -0, TRAPCC, 056770, "trapgt", -0, TRAPCC, 057370, "traple", -0, TRAPCC, 057770, "trapne", +{0, TRAPCC, 050370, "trapt"}, +{0, TRAPCC, 050770, "trapf"}, +{0, TRAPCC, 051370, "traphi"}, +{0, TRAPCC, 051770, "trapls"}, +{0, TRAPCC, 052370, "trapcc"}, +{0, TRAPCC, 052770, "trapcs"}, +{0, TRAPCC, 053370, "trapeq"}, +{0, TRAPCC, 053770, "trapvc"}, +{0, TRAPCC, 054370, "trapvs"}, +{0, TRAPCC, 054770, "trappl"}, +{0, TRAPCC, 055370, "trapmi"}, +{0, TRAPCC, 055770, "trapge"}, +{0, TRAPCC, 056370, "traplt"}, +{0, TRAPCC, 056770, "trapgt"}, +{0, TRAPCC, 057370, "traple"}, +{0, TRAPCC, 057770, "trapne"}, -0, CMP, 0, "cmp", +{0, CMP, 0, "cmp"}, -0, MOVE, 0, "move", -0, MOVESP, 0, "movep", -0, MOVEM, 0, "movem", -0, MOVESP, 1, "moves", -0, MOVEC, 0, "movec", +{0, MOVE, 0, "move"}, +{0, MOVESP, 0, "movep"}, +{0, MOVEM, 0, "movem"}, +{0, MOVESP, 1, "moves"}, +{0, MOVEC, 0, "movec"}, -0, SWAP, 0, "swap", +{0, SWAP, 0, "swap"}, -0, LINK, 0, "link", +{0, LINK, 0, "link"}, -0, UNLK, 0, "unlk", +{0, UNLK, 0, "unlk"}, -0, TRAP, 0, "trap", +{0, TRAP, 0, "trap"}, -0, OP_IMM, 047162, "stop", +{0, OP_IMM, 047162, "stop"}, -0, CHK, 0, "chk", +{0, CHK, 0, "chk"}, -0, RTM, 0, "rtm", +{0, RTM, 0, "rtm"}, -0, EXG, 0, "exg", +{0, EXG, 0, "exg"}, -0, LEA, 0, "lea", +{0, LEA, 0, "lea"}, -0, OP_IMM, 047164, "rtd", +{0, OP_IMM, 047164, "rtd"}, -0, BKPT, 0, "bkpt", +{0, BKPT, 0, "bkpt"}, -0, CALLM, 0, "callm", +{0, CALLM, 0, "callm"}, -0, CAS, 0, "cas", +{0, CAS, 0, "cas"}, -0, CAS2, 0, "cas2", +{0, CAS2, 0, "cas2"}, -0, CP, 00000, "c0", -0, CP, 01000, "c1", -0, CP, 02000, "c2", -0, CP, 03000, "c3", -0, CP, 04000, "c4", -0, CP, 05000, "c5", -0, CP, 06000, "c6", -0, CP, 07000, "c7", +{0, CP, 00000, "c0"}, +{0, CP, 01000, "c1"}, +{0, CP, 02000, "c2"}, +{0, CP, 03000, "c3"}, +{0, CP, 04000, "c4"}, +{0, CP, 05000, "c5"}, +{0, CP, 06000, "c6"}, +{0, CP, 07000, "c7"}, /* ???? what is this ???? */ -0, CPGEN, 0170000, ".gen", -0, CPSCC, 0170100, ".s", -0, CPDBCC, 0170110, ".db", -0, CPTRAPCC, 0170170, ".trap", -0, CPBCC, 0170200, ".br", /* 'r' to distinguish from SIZE_B +{0, CPGEN, 0170000, ".gen"}, +{0, CPSCC, 0170100, ".s"}, +{0, CPDBCC, 0170110, ".db"}, +{0, CPTRAPCC, 0170170, ".trap"}, +{0, CPBCC, 0170200, ".br"}, /* 'r' to distinguish from SIZE_B */ -0, CPSAVREST, 0170400, ".save", -0, CPSAVREST, 0170500, ".restore", +{0, CPSAVREST, 0170400, ".save"}, +{0, CPSAVREST, 0170500, ".restore"}, /* ???? end of what is this ???? */ /* M68030 MMU registers */ -0, MREG, 0040000, "tc", -0, MREG, 0044000, "srp", -0, MREG, 0046000, "crp", -0, MREG, 0060000, "mmusr", -0, MREG, 0060000, "psr", -0, MREG, 0004000, "tt0", -0, MREG, 0006000, "tt1", +{0, MREG, 0040000, "tc"}, +{0, MREG, 0044000, "srp"}, +{0, MREG, 0046000, "crp"}, +{0, MREG, 0060000, "mmusr"}, +{0, MREG, 0060000, "psr"}, +{0, MREG, 0004000, "tt0"}, +{0, MREG, 0006000, "tt1"}, /* M68030 MMU instructions */ -0, PFLUSHA, 0022000, "pflusha", -0, PFLUSH, 0020000, "pflush", -0, PLOAD, 0021000, "ploadr", -0, PLOAD, 0020000, "ploadw", -0, PTEST, 0101000, "ptestr", -0, PTEST, 0100000, "ptestw", -0, PMOVE, 0000000, "pmove", -0, PMOVE, 0000400, "pmovefd", +{0, PFLUSHA, 0022000, "pflusha"}, +{0, PFLUSH, 0020000, "pflush"}, +{0, PLOAD, 0021000, "ploadr"}, +{0, PLOAD, 0020000, "ploadw"}, +{0, PTEST, 0101000, "ptestr"}, +{0, PTEST, 0100000, "ptestw"}, +{0, PMOVE, 0000000, "pmove"}, +{0, PMOVE, 0000400, "pmovefd"}, /* floating point coprocessor ... */ -0, FSIZE, FSIZE_S, ".s", -0, FSIZE, FSIZE_X, ".x", -0, FSIZE, FSIZE_P, ".p", -0, FSIZE, FSIZE_D, ".d", +{0, FSIZE, FSIZE_S, ".s"}, +{0, FSIZE, FSIZE_X, ".x"}, +{0, FSIZE, FSIZE_P, ".p"}, +{0, FSIZE, FSIZE_D, ".d"}, -0, FPREG, 0, "fp0", -0, FPREG, 1, "fp1", -0, FPREG, 2, "fp2", -0, FPREG, 3, "fp3", -0, FPREG, 4, "fp4", -0, FPREG, 5, "fp5", -0, FPREG, 6, "fp6", -0, FPREG, 7, "fp7", +{0, FPREG, 0, "fp0"}, +{0, FPREG, 1, "fp1"}, +{0, FPREG, 2, "fp2"}, +{0, FPREG, 3, "fp3"}, +{0, FPREG, 4, "fp4"}, +{0, FPREG, 5, "fp5"}, +{0, FPREG, 6, "fp6"}, +{0, FPREG, 7, "fp7"}, -0, FPCR, 1, "fpiar", -0, FPCR, 2, "fpsr", -0, FPCR, 4, "fpcr", +{0, FPCR, 1, "fpiar"}, +{0, FPCR, 2, "fpsr"}, +{0, FPCR, 4, "fpcr"}, -0, FMOVE, 0, "fmove", -0, FMOVECR, 0, "fmovecr", -0, FMOVEM, 0, "fmovem", +{0, FMOVE, 0, "fmove"}, +{0, FMOVECR, 0, "fmovecr"}, +{0, FMOVEM, 0, "fmovem"}, -0, FDYADIC, 042, "fadd", -0, FDYADIC, 070, "fcmp", -0, FDYADIC, 040, "fdiv", -0, FDYADIC, 041, "fmod", -0, FDYADIC, 043, "fmul", -0, FDYADIC, 045, "frem", -0, FDYADIC, 046, "fscale", -0, FDYADIC, 044, "fsgldiv", -0, FDYADIC, 047, "fsglmul", -0, FDYADIC, 050, "fsub", +{0, FDYADIC, 042, "fadd"}, +{0, FDYADIC, 070, "fcmp"}, +{0, FDYADIC, 040, "fdiv"}, +{0, FDYADIC, 041, "fmod"}, +{0, FDYADIC, 043, "fmul"}, +{0, FDYADIC, 045, "frem"}, +{0, FDYADIC, 046, "fscale"}, +{0, FDYADIC, 044, "fsgldiv"}, +{0, FDYADIC, 047, "fsglmul"}, +{0, FDYADIC, 050, "fsub"}, -0, FMONADIC, 030, "fabs", -0, FMONADIC, 034, "facos", -0, FMONADIC, 014, "fasin", -0, FMONADIC, 012, "fatan", -0, FMONADIC, 015, "fatanh", -0, FMONADIC, 035, "fcos", -0, FMONADIC, 031, "fcosh", -0, FMONADIC, 020, "fetox", -0, FMONADIC, 010, "fetoxm1", -0, FMONADIC, 036, "fgetexp", -0, FMONADIC, 037, "fgetman", -0, FMONADIC, 001, "fint", -0, FMONADIC, 003, "fintrz", -0, FMONADIC, 024, "flogn", -0, FMONADIC, 006, "flognp1", -0, FMONADIC, 025, "flog10", -0, FMONADIC, 026, "flog2", -0, FMONADIC, 032, "fneg", -0, FMONADIC, 016, "fsin", -0, FMONADIC, 002, "fsinh", -0, FMONADIC, 004, "fsqrt", -0, FMONADIC, 017, "ftan", -0, FMONADIC, 011, "ftanh", -0, FMONADIC, 022, "ftentox", -0, FMONADIC, 021, "ftwotox", +{0, FMONADIC, 030, "fabs"}, +{0, FMONADIC, 034, "facos"}, +{0, FMONADIC, 014, "fasin"}, +{0, FMONADIC, 012, "fatan"}, +{0, FMONADIC, 015, "fatanh"}, +{0, FMONADIC, 035, "fcos"}, +{0, FMONADIC, 031, "fcosh"}, +{0, FMONADIC, 020, "fetox"}, +{0, FMONADIC, 010, "fetoxm1"}, +{0, FMONADIC, 036, "fgetexp"}, +{0, FMONADIC, 037, "fgetman"}, +{0, FMONADIC, 001, "fint"}, +{0, FMONADIC, 003, "fintrz"}, +{0, FMONADIC, 024, "flogn"}, +{0, FMONADIC, 006, "flognp1"}, +{0, FMONADIC, 025, "flog10"}, +{0, FMONADIC, 026, "flog2"}, +{0, FMONADIC, 032, "fneg"}, +{0, FMONADIC, 016, "fsin"}, +{0, FMONADIC, 002, "fsinh"}, +{0, FMONADIC, 004, "fsqrt"}, +{0, FMONADIC, 017, "ftan"}, +{0, FMONADIC, 011, "ftanh"}, +{0, FMONADIC, 022, "ftentox"}, +{0, FMONADIC, 021, "ftwotox"}, -0, FSINCOS, 060, "fsincos", +{0, FSINCOS, 060, "fsincos"}, -0, FBCC, 001, "fbeq", -0, FBCC, 016, "fbne", -0, FBCC, 022, "fbgt", -0, FBCC, 035, "fbngt", -0, FBCC, 023, "fbge", -0, FBCC, 034, "fbnge", -0, FBCC, 024, "fblt", -0, FBCC, 033, "fbnlt", -0, FBCC, 025, "fble", -0, FBCC, 032, "fbnle", -0, FBCC, 026, "fbgl", -0, FBCC, 031, "fbngl", -0, FBCC, 027, "fbgle", -0, FBCC, 030, "fbngle", -0, FBCC, 002, "fbogt", -0, FBCC, 015, "fbule", -0, FBCC, 003, "fboge", -0, FBCC, 014, "fbult", -0, FBCC, 004, "fbolt", -0, FBCC, 013, "fbuge", -0, FBCC, 005, "fbole", -0, FBCC, 012, "fbugt", -0, FBCC, 006, "fbogl", -0, FBCC, 011, "fbueq", -0, FBCC, 007, "fbor", -0, FBCC, 010, "fbun", -0, FBCC, 000, "fbf", -0, FBCC, 017, "fbt", -0, FBCC, 020, "fbsf", -0, FBCC, 037, "fbst", -0, FBCC, 021, "fbseq", -0, FBCC, 036, "fbsne", +{0, FBCC, 001, "fbeq"}, +{0, FBCC, 016, "fbne"}, +{0, FBCC, 022, "fbgt"}, +{0, FBCC, 035, "fbngt"}, +{0, FBCC, 023, "fbge"}, +{0, FBCC, 034, "fbnge"}, +{0, FBCC, 024, "fblt"}, +{0, FBCC, 033, "fbnlt"}, +{0, FBCC, 025, "fble"}, +{0, FBCC, 032, "fbnle"}, +{0, FBCC, 026, "fbgl"}, +{0, FBCC, 031, "fbngl"}, +{0, FBCC, 027, "fbgle"}, +{0, FBCC, 030, "fbngle"}, +{0, FBCC, 002, "fbogt"}, +{0, FBCC, 015, "fbule"}, +{0, FBCC, 003, "fboge"}, +{0, FBCC, 014, "fbult"}, +{0, FBCC, 004, "fbolt"}, +{0, FBCC, 013, "fbuge"}, +{0, FBCC, 005, "fbole"}, +{0, FBCC, 012, "fbugt"}, +{0, FBCC, 006, "fbogl"}, +{0, FBCC, 011, "fbueq"}, +{0, FBCC, 007, "fbor"}, +{0, FBCC, 010, "fbun"}, +{0, FBCC, 000, "fbf"}, +{0, FBCC, 017, "fbt"}, +{0, FBCC, 020, "fbsf"}, +{0, FBCC, 037, "fbst"}, +{0, FBCC, 021, "fbseq"}, +{0, FBCC, 036, "fbsne"}, -0, FDBCC, 001, "fdbeq", -0, FDBCC, 016, "fdbne", -0, FDBCC, 022, "fdbgt", -0, FDBCC, 035, "fdbngt", -0, FDBCC, 023, "fdbge", -0, FDBCC, 034, "fdbnge", -0, FDBCC, 024, "fdblt", -0, FDBCC, 033, "fdbnlt", -0, FDBCC, 025, "fdble", -0, FDBCC, 032, "fdbnle", -0, FDBCC, 026, "fdbgl", -0, FDBCC, 031, "fdbngl", -0, FDBCC, 027, "fdbgle", -0, FDBCC, 030, "fdbngle", -0, FDBCC, 002, "fdbogt", -0, FDBCC, 015, "fdbule", -0, FDBCC, 003, "fdboge", -0, FDBCC, 014, "fdbult", -0, FDBCC, 004, "fdbolt", -0, FDBCC, 013, "fdbuge", -0, FDBCC, 005, "fdbole", -0, FDBCC, 012, "fdbugt", -0, FDBCC, 006, "fdbogl", -0, FDBCC, 011, "fdbueq", -0, FDBCC, 007, "fdbor", -0, FDBCC, 010, "fdbun", -0, FDBCC, 000, "fdbf", -0, FDBCC, 017, "fdbt", -0, FDBCC, 020, "fdbsf", -0, FDBCC, 037, "fdbst", -0, FDBCC, 021, "fdbseq", -0, FDBCC, 036, "fdbsne", +{0, FDBCC, 001, "fdbeq"}, +{0, FDBCC, 016, "fdbne"}, +{0, FDBCC, 022, "fdbgt"}, +{0, FDBCC, 035, "fdbngt"}, +{0, FDBCC, 023, "fdbge"}, +{0, FDBCC, 034, "fdbnge"}, +{0, FDBCC, 024, "fdblt"}, +{0, FDBCC, 033, "fdbnlt"}, +{0, FDBCC, 025, "fdble"}, +{0, FDBCC, 032, "fdbnle"}, +{0, FDBCC, 026, "fdbgl"}, +{0, FDBCC, 031, "fdbngl"}, +{0, FDBCC, 027, "fdbgle"}, +{0, FDBCC, 030, "fdbngle"}, +{0, FDBCC, 002, "fdbogt"}, +{0, FDBCC, 015, "fdbule"}, +{0, FDBCC, 003, "fdboge"}, +{0, FDBCC, 014, "fdbult"}, +{0, FDBCC, 004, "fdbolt"}, +{0, FDBCC, 013, "fdbuge"}, +{0, FDBCC, 005, "fdbole"}, +{0, FDBCC, 012, "fdbugt"}, +{0, FDBCC, 006, "fdbogl"}, +{0, FDBCC, 011, "fdbueq"}, +{0, FDBCC, 007, "fdbor"}, +{0, FDBCC, 010, "fdbun"}, +{0, FDBCC, 000, "fdbf"}, +{0, FDBCC, 017, "fdbt"}, +{0, FDBCC, 020, "fdbsf"}, +{0, FDBCC, 037, "fdbst"}, +{0, FDBCC, 021, "fdbseq"}, +{0, FDBCC, 036, "fdbsne"}, -0, FNOP, 0, "fnop", +{0, FNOP, 0, "fnop"}, -0, FSCC, 001, "fseq", -0, FSCC, 016, "fsne", -0, FSCC, 022, "fsgt", -0, FSCC, 035, "fsngt", -0, FSCC, 023, "fsge", -0, FSCC, 034, "fsnge", -0, FSCC, 024, "fslt", -0, FSCC, 033, "fsnlt", -0, FSCC, 025, "fsle", -0, FSCC, 032, "fsnle", -0, FSCC, 026, "fsgl", -0, FSCC, 031, "fsngl", -0, FSCC, 027, "fsgle", -0, FSCC, 030, "fsngle", -0, FSCC, 002, "fsogt", -0, FSCC, 015, "fsule", -0, FSCC, 003, "fsoge", -0, FSCC, 014, "fsult", -0, FSCC, 004, "fsolt", -0, FSCC, 013, "fsuge", -0, FSCC, 005, "fsole", -0, FSCC, 012, "fsugt", -0, FSCC, 006, "fsogl", -0, FSCC, 011, "fsueq", -0, FSCC, 007, "fsor", -0, FSCC, 010, "fsun", -0, FSCC, 000, "fsf", -0, FSCC, 017, "fst", -0, FSCC, 020, "fssf", -0, FSCC, 037, "fsst", -0, FSCC, 021, "fsseq", -0, FSCC, 036, "fssne", +{0, FSCC, 001, "fseq"}, +{0, FSCC, 016, "fsne"}, +{0, FSCC, 022, "fsgt"}, +{0, FSCC, 035, "fsngt"}, +{0, FSCC, 023, "fsge"}, +{0, FSCC, 034, "fsnge"}, +{0, FSCC, 024, "fslt"}, +{0, FSCC, 033, "fsnlt"}, +{0, FSCC, 025, "fsle"}, +{0, FSCC, 032, "fsnle"}, +{0, FSCC, 026, "fsgl"}, +{0, FSCC, 031, "fsngl"}, +{0, FSCC, 027, "fsgle"}, +{0, FSCC, 030, "fsngle"}, +{0, FSCC, 002, "fsogt"}, +{0, FSCC, 015, "fsule"}, +{0, FSCC, 003, "fsoge"}, +{0, FSCC, 014, "fsult"}, +{0, FSCC, 004, "fsolt"}, +{0, FSCC, 013, "fsuge"}, +{0, FSCC, 005, "fsole"}, +{0, FSCC, 012, "fsugt"}, +{0, FSCC, 006, "fsogl"}, +{0, FSCC, 011, "fsueq"}, +{0, FSCC, 007, "fsor"}, +{0, FSCC, 010, "fsun"}, +{0, FSCC, 000, "fsf"}, +{0, FSCC, 017, "fst"}, +{0, FSCC, 020, "fssf"}, +{0, FSCC, 037, "fsst"}, +{0, FSCC, 021, "fsseq"}, +{0, FSCC, 036, "fssne"}, -0, FTST, 0, "ftst", +{0, FTST, 0, "ftst"}, -0, FSAVRES, MEM|ALT|0430, "fsave", -0, FSAVRES, MEM|0540, "frestore", +{0, FSAVRES, MEM|ALT|0430, "fsave"}, +{0, FSAVRES, MEM|0540, "frestore"}, -0, FTRAPCC, 001, "ftrapeq", -0, FTRAPCC, 016, "ftrapne", -0, FTRAPCC, 022, "ftrapgt", -0, FTRAPCC, 035, "ftrapngt", -0, FTRAPCC, 023, "ftrapge", -0, FTRAPCC, 034, "ftrapnge", -0, FTRAPCC, 024, "ftraplt", -0, FTRAPCC, 033, "ftrapnlt", -0, FTRAPCC, 025, "ftraple", -0, FTRAPCC, 032, "ftrapnle", -0, FTRAPCC, 026, "ftrapgl", -0, FTRAPCC, 031, "ftrapngl", -0, FTRAPCC, 027, "ftrapgle", -0, FTRAPCC, 030, "ftrapngle", -0, FTRAPCC, 002, "ftrapogt", -0, FTRAPCC, 015, "ftrapule", -0, FTRAPCC, 003, "ftrapoge", -0, FTRAPCC, 014, "ftrapult", -0, FTRAPCC, 004, "ftrapolt", -0, FTRAPCC, 013, "ftrapuge", -0, FTRAPCC, 005, "ftrapole", -0, FTRAPCC, 012, "ftrapugt", -0, FTRAPCC, 006, "ftrapogl", -0, FTRAPCC, 011, "ftrapueq", -0, FTRAPCC, 007, "ftrapor", -0, FTRAPCC, 010, "ftrapun", -0, FTRAPCC, 000, "ftrapf", -0, FTRAPCC, 017, "ftrapt", -0, FTRAPCC, 020, "ftrapsf", -0, FTRAPCC, 037, "ftrapst", -0, FTRAPCC, 021, "ftrapseq", -0, FTRAPCC, 036, "ftrapsne", +{0, FTRAPCC, 001, "ftrapeq"}, +{0, FTRAPCC, 016, "ftrapne"}, +{0, FTRAPCC, 022, "ftrapgt"}, +{0, FTRAPCC, 035, "ftrapngt"}, +{0, FTRAPCC, 023, "ftrapge"}, +{0, FTRAPCC, 034, "ftrapnge"}, +{0, FTRAPCC, 024, "ftraplt"}, +{0, FTRAPCC, 033, "ftrapnlt"}, +{0, FTRAPCC, 025, "ftraple"}, +{0, FTRAPCC, 032, "ftrapnle"}, +{0, FTRAPCC, 026, "ftrapgl"}, +{0, FTRAPCC, 031, "ftrapngl"}, +{0, FTRAPCC, 027, "ftrapgle"}, +{0, FTRAPCC, 030, "ftrapngle"}, +{0, FTRAPCC, 002, "ftrapogt"}, +{0, FTRAPCC, 015, "ftrapule"}, +{0, FTRAPCC, 003, "ftrapoge"}, +{0, FTRAPCC, 014, "ftrapult"}, +{0, FTRAPCC, 004, "ftrapolt"}, +{0, FTRAPCC, 013, "ftrapuge"}, +{0, FTRAPCC, 005, "ftrapole"}, +{0, FTRAPCC, 012, "ftrapugt"}, +{0, FTRAPCC, 006, "ftrapogl"}, +{0, FTRAPCC, 011, "ftrapueq"}, +{0, FTRAPCC, 007, "ftrapor"}, +{0, FTRAPCC, 010, "ftrapun"}, +{0, FTRAPCC, 000, "ftrapf"}, +{0, FTRAPCC, 017, "ftrapt"}, +{0, FTRAPCC, 020, "ftrapsf"}, +{0, FTRAPCC, 037, "ftrapst"}, +{0, FTRAPCC, 021, "ftrapseq"}, +{0, FTRAPCC, 036, "ftrapsne"}, diff --git a/mach/m68k2/as/mach3.c b/mach/m68k2/as/mach3.c index 81b4d270f..dc5bc503c 100644 --- a/mach/m68k2/as/mach3.c +++ b/mach/m68k2/as/mach3.c @@ -8,382 +8,382 @@ * Motorola 68000/68010 keywords */ -0, EXTERN, 0, ".globl", +{0, EXTERN, 0, ".globl"}, -0, SIZE, SIZE_B, ".b", -0, SIZE, SIZE_W, ".w", -0, SIZE, SIZE_L, ".l", +{0, SIZE, SIZE_B, ".b"}, +{0, SIZE, SIZE_W, ".w"}, +{0, SIZE, SIZE_L, ".l"}, -0, DREG, 00, "d0", -0, DREG, 01, "d1", -0, DREG, 02, "d2", -0, DREG, 03, "d3", -0, DREG, 04, "d4", -0, DREG, 05, "d5", -0, DREG, 06, "d6", -0, DREG, 07, "d7", +{0, DREG, 00, "d0"}, +{0, DREG, 01, "d1"}, +{0, DREG, 02, "d2"}, +{0, DREG, 03, "d3"}, +{0, DREG, 04, "d4"}, +{0, DREG, 05, "d5"}, +{0, DREG, 06, "d6"}, +{0, DREG, 07, "d7"}, -0, AREG, 00, "a0", -0, AREG, 01, "a1", -0, AREG, 02, "a2", -0, AREG, 03, "a3", -0, AREG, 04, "a4", -0, AREG, 05, "a5", -0, AREG, 06, "a6", -0, AREG, 07, "a7", -0, AREG, 07, "sp", +{0, AREG, 00, "a0"}, +{0, AREG, 01, "a1"}, +{0, AREG, 02, "a2"}, +{0, AREG, 03, "a3"}, +{0, AREG, 04, "a4"}, +{0, AREG, 05, "a5"}, +{0, AREG, 06, "a6"}, +{0, AREG, 07, "a7"}, +{0, AREG, 07, "sp"}, -0, PC, 8, "pc", +{0, PC, 8, "pc"}, -0, MODEL, 0, ".68000", -0, MODEL, 1, ".68010", +{0, MODEL, 0, ".68000"}, +{0, MODEL, 1, ".68010"}, -0, CREG, 04001, "vbr", -0, CREG, 0, "sfc", -0, CREG, 00001, "dfc", +{0, CREG, 04001, "vbr"}, +{0, CREG, 0, "sfc"}, +{0, CREG, 00001, "dfc"}, -0, SPEC, 075, "usp", -0, SPEC, 076, "ccr", -0, SPEC, 077, "sr", +{0, SPEC, 075, "usp"}, +{0, SPEC, 076, "ccr"}, +{0, SPEC, 077, "sr"}, -0, ABCD, 0140400, "abcd", -0, ABCD, 0100400, "sbcd", +{0, ABCD, 0140400, "abcd"}, +{0, ABCD, 0100400, "sbcd"}, -0, ADDX, 0150400, "addx", -0, ADDX, 0110400, "subx", +{0, ADDX, 0150400, "addx"}, +{0, ADDX, 0110400, "subx"}, -0, ADD, 0153300, "add", -0, ADD, 0112700, "sub", +{0, ADD, 0153300, "add"}, +{0, ADD, 0112700, "sub"}, -0, AND, 0141000, "and", -0, AND, 0135000, "eor", -0, AND, 0100000, "or", +{0, AND, 0141000, "and"}, +{0, AND, 0135000, "eor"}, +{0, AND, 0100000, "or"}, -0, BITOP, 0000, "btst", -0, BITOP, 0100, "bchg", -0, BITOP, 0200, "bclr", -0, BITOP, 0300, "bset", +{0, BITOP, 0000, "btst"}, +{0, BITOP, 0100, "bchg"}, +{0, BITOP, 0200, "bclr"}, +{0, BITOP, 0300, "bset"}, -0, SHIFT, 0160340, "asr", -0, SHIFT, 0160740, "asl", -0, SHIFT, 0161350, "lsr", -0, SHIFT, 0161750, "lsl", -0, SHIFT, 0162360, "roxr", -0, SHIFT, 0162760, "roxl", -0, SHIFT, 0163370, "ror", -0, SHIFT, 0163770, "rol", +{0, SHIFT, 0160340, "asr"}, +{0, SHIFT, 0160740, "asl"}, +{0, SHIFT, 0161350, "lsr"}, +{0, SHIFT, 0161750, "lsl"}, +{0, SHIFT, 0162360, "roxr"}, +{0, SHIFT, 0162760, "roxl"}, +{0, SHIFT, 0163370, "ror"}, +{0, SHIFT, 0163770, "rol"}, -0, SZ_EA, 041000|DTA|ALT, "clr", -0, SZ_EA, 042000|DTA|ALT, "neg", -0, SZ_EA, 040000|DTA|ALT, "negx", -0, SZ_EA, 043000|DTA|ALT, "not", -0, SZ_EA, 045000|DTA|ALT, "tst", +{0, SZ_EA, 041000|DTA|ALT, "clr"}, +{0, SZ_EA, 042000|DTA|ALT, "neg"}, +{0, SZ_EA, 040000|DTA|ALT, "negx"}, +{0, SZ_EA, 043000|DTA|ALT, "not"}, +{0, SZ_EA, 045000|DTA|ALT, "tst"}, -0, OP_EA, 044000|DTA|ALT, "nbcd", -0, OP_EA, 045300|DTA|ALT, "tas", -0, OP_EA, 047200|CTR, "jsr", -0, OP_EA, 047300|CTR, "jmp", -0, OP_EA, 044100|CTR, "pea", +{0, OP_EA, 044000|DTA|ALT, "nbcd"}, +{0, OP_EA, 045300|DTA|ALT, "tas"}, +{0, OP_EA, 047200|CTR, "jsr"}, +{0, OP_EA, 047300|CTR, "jmp"}, +{0, OP_EA, 044100|CTR, "pea"}, -0, OP_EA, 050300, "st", -0, OP_EA, 050700, "sf", -0, OP_EA, 051300, "shi", -0, OP_EA, 051700, "sls", -0, OP_EA, 052300, "scc", -0, OP_EA, 052700, "scs", -0, OP_EA, 053300, "sne", -0, OP_EA, 053700, "seq", -0, OP_EA, 054300, "svc", -0, OP_EA, 054700, "svs", -0, OP_EA, 055300, "spl", -0, OP_EA, 055700, "smi", -0, OP_EA, 056300, "sge", -0, OP_EA, 056700, "slt", -0, OP_EA, 057300, "sgt", -0, OP_EA, 057700, "sle", +{0, OP_EA, 050300, "st"}, +{0, OP_EA, 050700, "sf"}, +{0, OP_EA, 051300, "shi"}, +{0, OP_EA, 051700, "sls"}, +{0, OP_EA, 052300, "scc"}, +{0, OP_EA, 052700, "scs"}, +{0, OP_EA, 053300, "sne"}, +{0, OP_EA, 053700, "seq"}, +{0, OP_EA, 054300, "svc"}, +{0, OP_EA, 054700, "svs"}, +{0, OP_EA, 055300, "spl"}, +{0, OP_EA, 055700, "smi"}, +{0, OP_EA, 056300, "sge"}, +{0, OP_EA, 056700, "slt"}, +{0, OP_EA, 057300, "sgt"}, +{0, OP_EA, 057700, "sle"}, -0, OP_NOOP, 047160, "reset", -0, OP_NOOP, 047161, "nop", -0, OP_NOOP, 047163, "rte", -0, OP_NOOP, 047165, "rts", -0, OP_NOOP, 047166, "trapv", -0, OP_NOOP, 047167, "rtr", -0, OP_NOOP, 045374, "illegal", +{0, OP_NOOP, 047160, "reset"}, +{0, OP_NOOP, 047161, "nop"}, +{0, OP_NOOP, 047163, "rte"}, +{0, OP_NOOP, 047165, "rts"}, +{0, OP_NOOP, 047166, "trapv"}, +{0, OP_NOOP, 047167, "rtr"}, +{0, OP_NOOP, 045374, "illegal"}, -0, OP_EA_D, 040600, "chk", -0, OP_EA_D, 0100300, "divu", -0, OP_EA_D, 0100700, "divs", -0, OP_EA_D, 0140300, "mulu", -0, OP_EA_D, 0140700, "muls", +{0, OP_EA_D, 040600, "chk"}, +{0, OP_EA_D, 0100300, "divu"}, +{0, OP_EA_D, 0100700, "divs"}, +{0, OP_EA_D, 0140300, "mulu"}, +{0, OP_EA_D, 0140700, "muls"}, -0, BR, 060000, "bra", -0, BR, 060400, "bsr", -0, BR, 061000, "bhi", -0, BR, 061400, "bls", -0, BR, 062000, "bcc", -0, BR, 062400, "bcs", -0, BR, 063000, "bne", -0, BR, 063400, "beq", -0, BR, 064000, "bvc", -0, BR, 064400, "bvs", -0, BR, 065000, "bpl", -0, BR, 065400, "bmi", -0, BR, 066000, "bge", -0, BR, 066400, "blt", -0, BR, 067000, "bgt", -0, BR, 067400, "ble", +{0, BR, 060000, "bra"}, +{0, BR, 060400, "bsr"}, +{0, BR, 061000, "bhi"}, +{0, BR, 061400, "bls"}, +{0, BR, 062000, "bcc"}, +{0, BR, 062400, "bcs"}, +{0, BR, 063000, "bne"}, +{0, BR, 063400, "beq"}, +{0, BR, 064000, "bvc"}, +{0, BR, 064400, "bvs"}, +{0, BR, 065000, "bpl"}, +{0, BR, 065400, "bmi"}, +{0, BR, 066000, "bge"}, +{0, BR, 066400, "blt"}, +{0, BR, 067000, "bgt"}, +{0, BR, 067400, "ble"}, -0, DBR, 050310, "dbt", -0, DBR, 050710, "dbf", -0, DBR, 050710, "dbra", -0, DBR, 051310, "dbhi", -0, DBR, 051710, "dbls", -0, DBR, 052310, "dbcc", -0, DBR, 052710, "dbcs", -0, DBR, 053310, "dbne", -0, DBR, 053710, "dbeq", -0, DBR, 054310, "dbvc", -0, DBR, 054710, "dbvs", -0, DBR, 055310, "dbpl", -0, DBR, 055710, "dbmi", -0, DBR, 056310, "dbge", -0, DBR, 056710, "dblt", -0, DBR, 057310, "dbgt", -0, DBR, 057710, "dble", +{0, DBR, 050310, "dbt"}, +{0, DBR, 050710, "dbf"}, +{0, DBR, 050710, "dbra"}, +{0, DBR, 051310, "dbhi"}, +{0, DBR, 051710, "dbls"}, +{0, DBR, 052310, "dbcc"}, +{0, DBR, 052710, "dbcs"}, +{0, DBR, 053310, "dbne"}, +{0, DBR, 053710, "dbeq"}, +{0, DBR, 054310, "dbvc"}, +{0, DBR, 054710, "dbvs"}, +{0, DBR, 055310, "dbpl"}, +{0, DBR, 055710, "dbmi"}, +{0, DBR, 056310, "dbge"}, +{0, DBR, 056710, "dblt"}, +{0, DBR, 057310, "dbgt"}, +{0, DBR, 057710, "dble"}, -0, CMP, 0, "cmp", +{0, CMP, 0, "cmp"}, -0, MOVE, 0, "move", -0, MOVEP, 0, "movep", -0, MOVEM, 0, "movem", -0, MOVES, 0, "moves", -0, MOVEC, 0, "movec", +{0, MOVE, 0, "move"}, +{0, MOVEP, 0, "movep"}, +{0, MOVEM, 0, "movem"}, +{0, MOVES, 0, "moves"}, +{0, MOVEC, 0, "movec"}, -0, SWAP, 0, "swap", +{0, SWAP, 0, "swap"}, -0, LINK, 0, "link", +{0, LINK, 0, "link"}, -0, UNLK, 0, "unlk", +{0, UNLK, 0, "unlk"}, -0, TRAP, 0, "trap", +{0, TRAP, 0, "trap"}, -0, STOP, 047162, "stop", +{0, STOP, 047162, "stop"}, -0, EXG, 0, "exg", +{0, EXG, 0, "exg"}, -0, OP_EXT, 0, "ext", +{0, OP_EXT, 0, "ext"}, -0, LEA, 0, "lea", +{0, LEA, 0, "lea"}, -0, RTD, 0, "rtd", +{0, RTD, 0, "rtd"}, /* floating point coprocessor ... */ -0, FSIZE, FSIZE_S, ".s", -0, FSIZE, FSIZE_X, ".x", -0, FSIZE, FSIZE_P, ".p", -0, FSIZE, FSIZE_D, ".d", +{0, FSIZE, FSIZE_S, ".s"}, +{0, FSIZE, FSIZE_X, ".x"}, +{0, FSIZE, FSIZE_P, ".p"}, +{0, FSIZE, FSIZE_D, ".d"}, -0, FPREG, 0, "fp0", -0, FPREG, 1, "fp1", -0, FPREG, 2, "fp2", -0, FPREG, 3, "fp3", -0, FPREG, 4, "fp4", -0, FPREG, 5, "fp5", -0, FPREG, 6, "fp6", -0, FPREG, 7, "fp7", +{0, FPREG, 0, "fp0"}, +{0, FPREG, 1, "fp1"}, +{0, FPREG, 2, "fp2"}, +{0, FPREG, 3, "fp3"}, +{0, FPREG, 4, "fp4"}, +{0, FPREG, 5, "fp5"}, +{0, FPREG, 6, "fp6"}, +{0, FPREG, 7, "fp7"}, -0, FPCR, 1, "fpiar", -0, FPCR, 2, "fpsr", -0, FPCR, 4, "fpcr", +{0, FPCR, 1, "fpiar"}, +{0, FPCR, 2, "fpsr"}, +{0, FPCR, 4, "fpcr"}, -0, FMOVE, 0, "fmove", -0, FMOVECR, 0, "fmovecr", -0, FMOVEM, 0, "fmovem", +{0, FMOVE, 0, "fmove"}, +{0, FMOVECR, 0, "fmovecr"}, +{0, FMOVEM, 0, "fmovem"}, -0, FDYADIC, 042, "fadd", -0, FDYADIC, 070, "fcmp", -0, FDYADIC, 040, "fdiv", -0, FDYADIC, 041, "fmod", -0, FDYADIC, 043, "fmul", -0, FDYADIC, 045, "frem", -0, FDYADIC, 046, "fscale", -0, FDYADIC, 044, "fsgldiv", -0, FDYADIC, 047, "fsglmul", -0, FDYADIC, 050, "fsub", +{0, FDYADIC, 042, "fadd"}, +{0, FDYADIC, 070, "fcmp"}, +{0, FDYADIC, 040, "fdiv"}, +{0, FDYADIC, 041, "fmod"}, +{0, FDYADIC, 043, "fmul"}, +{0, FDYADIC, 045, "frem"}, +{0, FDYADIC, 046, "fscale"}, +{0, FDYADIC, 044, "fsgldiv"}, +{0, FDYADIC, 047, "fsglmul"}, +{0, FDYADIC, 050, "fsub"}, -0, FMONADIC, 030, "fabs", -0, FMONADIC, 034, "facos", -0, FMONADIC, 014, "fasin", -0, FMONADIC, 012, "fatan", -0, FMONADIC, 015, "fatanh", -0, FMONADIC, 035, "fcos", -0, FMONADIC, 031, "fcosh", -0, FMONADIC, 020, "fetox", -0, FMONADIC, 010, "fetoxm1", -0, FMONADIC, 036, "fgetexp", -0, FMONADIC, 037, "fgetman", -0, FMONADIC, 001, "fint", -0, FMONADIC, 003, "fintrz", -0, FMONADIC, 024, "flogn", -0, FMONADIC, 006, "flognp1", -0, FMONADIC, 025, "flog10", -0, FMONADIC, 026, "flog2", -0, FMONADIC, 032, "fneg", -0, FMONADIC, 016, "fsin", -0, FMONADIC, 002, "fsinh", -0, FMONADIC, 004, "fsqrt", -0, FMONADIC, 017, "ftan", -0, FMONADIC, 011, "ftanh", -0, FMONADIC, 022, "ftentox", -0, FMONADIC, 021, "ftwotox", +{0, FMONADIC, 030, "fabs"}, +{0, FMONADIC, 034, "facos"}, +{0, FMONADIC, 014, "fasin"}, +{0, FMONADIC, 012, "fatan"}, +{0, FMONADIC, 015, "fatanh"}, +{0, FMONADIC, 035, "fcos"}, +{0, FMONADIC, 031, "fcosh"}, +{0, FMONADIC, 020, "fetox"}, +{0, FMONADIC, 010, "fetoxm1"}, +{0, FMONADIC, 036, "fgetexp"}, +{0, FMONADIC, 037, "fgetman"}, +{0, FMONADIC, 001, "fint"}, +{0, FMONADIC, 003, "fintrz"}, +{0, FMONADIC, 024, "flogn"}, +{0, FMONADIC, 006, "flognp1"}, +{0, FMONADIC, 025, "flog10"}, +{0, FMONADIC, 026, "flog2"}, +{0, FMONADIC, 032, "fneg"}, +{0, FMONADIC, 016, "fsin"}, +{0, FMONADIC, 002, "fsinh"}, +{0, FMONADIC, 004, "fsqrt"}, +{0, FMONADIC, 017, "ftan"}, +{0, FMONADIC, 011, "ftanh"}, +{0, FMONADIC, 022, "ftentox"}, +{0, FMONADIC, 021, "ftwotox"}, -0, FSINCOS, 060, "fsincos", +{0, FSINCOS, 060, "fsincos"}, -0, FBCC, 001, "fbeq", -0, FBCC, 016, "fbne", -0, FBCC, 022, "fbgt", -0, FBCC, 035, "fbngt", -0, FBCC, 023, "fbge", -0, FBCC, 034, "fbnge", -0, FBCC, 024, "fblt", -0, FBCC, 033, "fbnlt", -0, FBCC, 025, "fble", -0, FBCC, 032, "fbnle", -0, FBCC, 026, "fbgl", -0, FBCC, 031, "fbngl", -0, FBCC, 027, "fbgle", -0, FBCC, 030, "fbngle", -0, FBCC, 002, "fbogt", -0, FBCC, 015, "fbule", -0, FBCC, 003, "fboge", -0, FBCC, 014, "fbult", -0, FBCC, 004, "fbolt", -0, FBCC, 013, "fbuge", -0, FBCC, 005, "fbole", -0, FBCC, 012, "fbugt", -0, FBCC, 006, "fbogl", -0, FBCC, 011, "fbueq", -0, FBCC, 007, "fbor", -0, FBCC, 010, "fbun", -0, FBCC, 000, "fbf", -0, FBCC, 017, "fbt", -0, FBCC, 020, "fbsf", -0, FBCC, 037, "fbst", -0, FBCC, 021, "fbseq", -0, FBCC, 036, "fbsne", +{0, FBCC, 001, "fbeq"}, +{0, FBCC, 016, "fbne"}, +{0, FBCC, 022, "fbgt"}, +{0, FBCC, 035, "fbngt"}, +{0, FBCC, 023, "fbge"}, +{0, FBCC, 034, "fbnge"}, +{0, FBCC, 024, "fblt"}, +{0, FBCC, 033, "fbnlt"}, +{0, FBCC, 025, "fble"}, +{0, FBCC, 032, "fbnle"}, +{0, FBCC, 026, "fbgl"}, +{0, FBCC, 031, "fbngl"}, +{0, FBCC, 027, "fbgle"}, +{0, FBCC, 030, "fbngle"}, +{0, FBCC, 002, "fbogt"}, +{0, FBCC, 015, "fbule"}, +{0, FBCC, 003, "fboge"}, +{0, FBCC, 014, "fbult"}, +{0, FBCC, 004, "fbolt"}, +{0, FBCC, 013, "fbuge"}, +{0, FBCC, 005, "fbole"}, +{0, FBCC, 012, "fbugt"}, +{0, FBCC, 006, "fbogl"}, +{0, FBCC, 011, "fbueq"}, +{0, FBCC, 007, "fbor"}, +{0, FBCC, 010, "fbun"}, +{0, FBCC, 000, "fbf"}, +{0, FBCC, 017, "fbt"}, +{0, FBCC, 020, "fbsf"}, +{0, FBCC, 037, "fbst"}, +{0, FBCC, 021, "fbseq"}, +{0, FBCC, 036, "fbsne"}, -0, FDBCC, 001, "fdbeq", -0, FDBCC, 016, "fdbne", -0, FDBCC, 022, "fdbgt", -0, FDBCC, 035, "fdbngt", -0, FDBCC, 023, "fdbge", -0, FDBCC, 034, "fdbnge", -0, FDBCC, 024, "fdblt", -0, FDBCC, 033, "fdbnlt", -0, FDBCC, 025, "fdble", -0, FDBCC, 032, "fdbnle", -0, FDBCC, 026, "fdbgl", -0, FDBCC, 031, "fdbngl", -0, FDBCC, 027, "fdbgle", -0, FDBCC, 030, "fdbngle", -0, FDBCC, 002, "fdbogt", -0, FDBCC, 015, "fdbule", -0, FDBCC, 003, "fdboge", -0, FDBCC, 014, "fdbult", -0, FDBCC, 004, "fdbolt", -0, FDBCC, 013, "fdbuge", -0, FDBCC, 005, "fdbole", -0, FDBCC, 012, "fdbugt", -0, FDBCC, 006, "fdbogl", -0, FDBCC, 011, "fdbueq", -0, FDBCC, 007, "fdbor", -0, FDBCC, 010, "fdbun", -0, FDBCC, 000, "fdbf", -0, FDBCC, 017, "fdbt", -0, FDBCC, 020, "fdbsf", -0, FDBCC, 037, "fdbst", -0, FDBCC, 021, "fdbseq", -0, FDBCC, 036, "fdbsne", +{0, FDBCC, 001, "fdbeq"}, +{0, FDBCC, 016, "fdbne"}, +{0, FDBCC, 022, "fdbgt"}, +{0, FDBCC, 035, "fdbngt"}, +{0, FDBCC, 023, "fdbge"}, +{0, FDBCC, 034, "fdbnge"}, +{0, FDBCC, 024, "fdblt"}, +{0, FDBCC, 033, "fdbnlt"}, +{0, FDBCC, 025, "fdble"}, +{0, FDBCC, 032, "fdbnle"}, +{0, FDBCC, 026, "fdbgl"}, +{0, FDBCC, 031, "fdbngl"}, +{0, FDBCC, 027, "fdbgle"}, +{0, FDBCC, 030, "fdbngle"}, +{0, FDBCC, 002, "fdbogt"}, +{0, FDBCC, 015, "fdbule"}, +{0, FDBCC, 003, "fdboge"}, +{0, FDBCC, 014, "fdbult"}, +{0, FDBCC, 004, "fdbolt"}, +{0, FDBCC, 013, "fdbuge"}, +{0, FDBCC, 005, "fdbole"}, +{0, FDBCC, 012, "fdbugt"}, +{0, FDBCC, 006, "fdbogl"}, +{0, FDBCC, 011, "fdbueq"}, +{0, FDBCC, 007, "fdbor"}, +{0, FDBCC, 010, "fdbun"}, +{0, FDBCC, 000, "fdbf"}, +{0, FDBCC, 017, "fdbt"}, +{0, FDBCC, 020, "fdbsf"}, +{0, FDBCC, 037, "fdbst"}, +{0, FDBCC, 021, "fdbseq"}, +{0, FDBCC, 036, "fdbsne"}, -0, FNOP, 0, "fnop", +{0, FNOP, 0, "fnop"}, -0, FSCC, 001, "fseq", -0, FSCC, 016, "fsne", -0, FSCC, 022, "fsgt", -0, FSCC, 035, "fsngt", -0, FSCC, 023, "fsge", -0, FSCC, 034, "fsnge", -0, FSCC, 024, "fslt", -0, FSCC, 033, "fsnlt", -0, FSCC, 025, "fsle", -0, FSCC, 032, "fsnle", -0, FSCC, 026, "fsgl", -0, FSCC, 031, "fsngl", -0, FSCC, 027, "fsgle", -0, FSCC, 030, "fsngle", -0, FSCC, 002, "fsogt", -0, FSCC, 015, "fsule", -0, FSCC, 003, "fsoge", -0, FSCC, 014, "fsult", -0, FSCC, 004, "fsolt", -0, FSCC, 013, "fsuge", -0, FSCC, 005, "fsole", -0, FSCC, 012, "fsugt", -0, FSCC, 006, "fsogl", -0, FSCC, 011, "fsueq", -0, FSCC, 007, "fsor", -0, FSCC, 010, "fsun", -0, FSCC, 000, "fsf", -0, FSCC, 017, "fst", -0, FSCC, 020, "fssf", -0, FSCC, 037, "fsst", -0, FSCC, 021, "fsseq", -0, FSCC, 036, "fssne", +{0, FSCC, 001, "fseq"}, +{0, FSCC, 016, "fsne"}, +{0, FSCC, 022, "fsgt"}, +{0, FSCC, 035, "fsngt"}, +{0, FSCC, 023, "fsge"}, +{0, FSCC, 034, "fsnge"}, +{0, FSCC, 024, "fslt"}, +{0, FSCC, 033, "fsnlt"}, +{0, FSCC, 025, "fsle"}, +{0, FSCC, 032, "fsnle"}, +{0, FSCC, 026, "fsgl"}, +{0, FSCC, 031, "fsngl"}, +{0, FSCC, 027, "fsgle"}, +{0, FSCC, 030, "fsngle"}, +{0, FSCC, 002, "fsogt"}, +{0, FSCC, 015, "fsule"}, +{0, FSCC, 003, "fsoge"}, +{0, FSCC, 014, "fsult"}, +{0, FSCC, 004, "fsolt"}, +{0, FSCC, 013, "fsuge"}, +{0, FSCC, 005, "fsole"}, +{0, FSCC, 012, "fsugt"}, +{0, FSCC, 006, "fsogl"}, +{0, FSCC, 011, "fsueq"}, +{0, FSCC, 007, "fsor"}, +{0, FSCC, 010, "fsun"}, +{0, FSCC, 000, "fsf"}, +{0, FSCC, 017, "fst"}, +{0, FSCC, 020, "fssf"}, +{0, FSCC, 037, "fsst"}, +{0, FSCC, 021, "fsseq"}, +{0, FSCC, 036, "fssne"}, -0, FTST, 0, "ftst", +{0, FTST, 0, "ftst"}, -0, FSAVRES, MEM|ALT|0430, "fsave", -0, FSAVRES, MEM|0540, "frestore", +{0, FSAVRES, MEM|ALT|0430, "fsave"}, +{0, FSAVRES, MEM|0540, "frestore"}, -0, FTRAPCC, 001, "ftrapeq", -0, FTRAPCC, 016, "ftrapne", -0, FTRAPCC, 022, "ftrapgt", -0, FTRAPCC, 035, "ftrapngt", -0, FTRAPCC, 023, "ftrapge", -0, FTRAPCC, 034, "ftrapnge", -0, FTRAPCC, 024, "ftraplt", -0, FTRAPCC, 033, "ftrapnlt", -0, FTRAPCC, 025, "ftraple", -0, FTRAPCC, 032, "ftrapnle", -0, FTRAPCC, 026, "ftrapgl", -0, FTRAPCC, 031, "ftrapngl", -0, FTRAPCC, 027, "ftrapgle", -0, FTRAPCC, 030, "ftrapngle", -0, FTRAPCC, 002, "ftrapogt", -0, FTRAPCC, 015, "ftrapule", -0, FTRAPCC, 003, "ftrapoge", -0, FTRAPCC, 014, "ftrapult", -0, FTRAPCC, 004, "ftrapolt", -0, FTRAPCC, 013, "ftrapuge", -0, FTRAPCC, 005, "ftrapole", -0, FTRAPCC, 012, "ftrapugt", -0, FTRAPCC, 006, "ftrapogl", -0, FTRAPCC, 011, "ftrapueq", -0, FTRAPCC, 007, "ftrapor", -0, FTRAPCC, 010, "ftrapun", -0, FTRAPCC, 000, "ftrapf", -0, FTRAPCC, 017, "ftrapt", -0, FTRAPCC, 020, "ftrapsf", -0, FTRAPCC, 037, "ftrapst", -0, FTRAPCC, 021, "ftrapseq", -0, FTRAPCC, 036, "ftrapsne", +{0, FTRAPCC, 001, "ftrapeq"}, +{0, FTRAPCC, 016, "ftrapne"}, +{0, FTRAPCC, 022, "ftrapgt"}, +{0, FTRAPCC, 035, "ftrapngt"}, +{0, FTRAPCC, 023, "ftrapge"}, +{0, FTRAPCC, 034, "ftrapnge"}, +{0, FTRAPCC, 024, "ftraplt"}, +{0, FTRAPCC, 033, "ftrapnlt"}, +{0, FTRAPCC, 025, "ftraple"}, +{0, FTRAPCC, 032, "ftrapnle"}, +{0, FTRAPCC, 026, "ftrapgl"}, +{0, FTRAPCC, 031, "ftrapngl"}, +{0, FTRAPCC, 027, "ftrapgle"}, +{0, FTRAPCC, 030, "ftrapngle"}, +{0, FTRAPCC, 002, "ftrapogt"}, +{0, FTRAPCC, 015, "ftrapule"}, +{0, FTRAPCC, 003, "ftrapoge"}, +{0, FTRAPCC, 014, "ftrapult"}, +{0, FTRAPCC, 004, "ftrapolt"}, +{0, FTRAPCC, 013, "ftrapuge"}, +{0, FTRAPCC, 005, "ftrapole"}, +{0, FTRAPCC, 012, "ftrapugt"}, +{0, FTRAPCC, 006, "ftrapogl"}, +{0, FTRAPCC, 011, "ftrapueq"}, +{0, FTRAPCC, 007, "ftrapor"}, +{0, FTRAPCC, 010, "ftrapun"}, +{0, FTRAPCC, 000, "ftrapf"}, +{0, FTRAPCC, 017, "ftrapt"}, +{0, FTRAPCC, 020, "ftrapsf"}, +{0, FTRAPCC, 037, "ftrapst"}, +{0, FTRAPCC, 021, "ftrapseq"}, +{0, FTRAPCC, 036, "ftrapsne"}, -0, CP, 00000, "c0", -0, CP, 01000, "c1", -0, CP, 02000, "c2", -0, CP, 03000, "c3", -0, CP, 04000, "c4", -0, CP, 05000, "c5", -0, CP, 06000, "c6", -0, CP, 07000, "c7", +{0, CP, 00000, "c0"}, +{0, CP, 01000, "c1"}, +{0, CP, 02000, "c2"}, +{0, CP, 03000, "c3"}, +{0, CP, 04000, "c4"}, +{0, CP, 05000, "c5"}, +{0, CP, 06000, "c6"}, +{0, CP, 07000, "c7"}, diff --git a/mach/ns/as/mach3.c b/mach/ns/as/mach3.c index 4b072ad8b..b4b5435f7 100644 --- a/mach/ns/as/mach3.c +++ b/mach/ns/as/mach3.c @@ -9,449 +9,449 @@ */ /* Registers */ -0, REG, 0, "r0", -0, REG, 1, "r1", -0, REG, 2, "r2", -0, REG, 3, "r3", -0, REG, 4, "r4", -0, REG, 5, "r5", -0, REG, 6, "r6", -0, REG, 7, "r7", -0, FREG, 0, "f0", -0, FREG, 1, "f1", -0, FREG, 2, "f2", -0, FREG, 3, "f3", -0, FREG, 4, "f4", -0, FREG, 5, "f5", -0, FREG, 6, "f6", -0, FREG, 7, "f7", +{0, REG, 0, "r0"}, +{0, REG, 1, "r1"}, +{0, REG, 2, "r2"}, +{0, REG, 3, "r3"}, +{0, REG, 4, "r4"}, +{0, REG, 5, "r5"}, +{0, REG, 6, "r6"}, +{0, REG, 7, "r7"}, +{0, FREG, 0, "f0"}, +{0, FREG, 1, "f1"}, +{0, FREG, 2, "f2"}, +{0, FREG, 3, "f3"}, +{0, FREG, 4, "f4"}, +{0, FREG, 5, "f5"}, +{0, FREG, 6, "f6"}, +{0, FREG, 7, "f7"}, /* CPU dedicated registers */ -0, AREG, 0x0, "us", -0, AREG, 0x8, "fp", -0, AREG, 0x9, "sp", -0, AREG, 0xA, "sb", -0, AREG, 0xD, "psr", -0, AREG, 0xE, "intbase", -0, AREG, 0xF, "mod", +{0, AREG, 0x0, "us"}, +{0, AREG, 0x8, "fp"}, +{0, AREG, 0x9, "sp"}, +{0, AREG, 0xA, "sb"}, +{0, AREG, 0xD, "psr"}, +{0, AREG, 0xE, "intbase"}, +{0, AREG, 0xF, "mod"}, /* Tokens dedicated to addressing modes */ -0, TOS, 0x17, "tos", -0, EXTERNAL, 0x16, "external", -0, PC, 0, "pc", -0, INDICATOR, 'b', "b", -0, INDICATOR, 'c', "c", -0, INDICATOR, 'd', "d", -0, INDICATOR, 'f', "f", -0, INDICATOR, 'i', "i", -0, INDICATOR, 'm', "m", -0, INDICATOR, 'q', "q", -0, INDICATOR, 'u', "u", -0, INDICATOR, 'w', "w", +{0, TOS, 0x17, "tos"}, +{0, EXTERNAL, 0x16, "external"}, +{0, PC, 0, "pc"}, +{0, INDICATOR, 'b', "b"}, +{0, INDICATOR, 'c', "c"}, +{0, INDICATOR, 'd', "d"}, +{0, INDICATOR, 'f', "f"}, +{0, INDICATOR, 'i', "i"}, +{0, INDICATOR, 'm', "m"}, +{0, INDICATOR, 'q', "q"}, +{0, INDICATOR, 'u', "u"}, +{0, INDICATOR, 'w', "w"}, /* Memory management registers */ -0, MREG, 0x0, "bpr0", -0, MREG, 0x1, "bpr1", -0, MREG, 0x4, "pf0", -0, MREG, 0x5, "pf1", -0, MREG, 0x8, "sc", -0, MREG, 0xA, "msr", -0, MREG, 0xB, "bcnt", -0, MREG, 0xC, "ptb0", -0, MREG, 0xD, "ptb1", -0, MREG, 0xF, "eia", +{0, MREG, 0x0, "bpr0"}, +{0, MREG, 0x1, "bpr1"}, +{0, MREG, 0x4, "pf0"}, +{0, MREG, 0x5, "pf1"}, +{0, MREG, 0x8, "sc"}, +{0, MREG, 0xA, "msr"}, +{0, MREG, 0xB, "bcnt"}, +{0, MREG, 0xC, "ptb0"}, +{0, MREG, 0xD, "ptb1"}, +{0, MREG, 0xF, "eia"}, /* Instruction types */ /* Integer instructions */ -0, ADD_I, mk_op2(0x5,I_BYTE,I_BYTE), "movb", -0, ADD_I, mk_op2(0x5,I_WORD,I_WORD), "movw", -0, ADD_I, mk_op2(0x5,I_DOUBLE,I_DOUBLE), "movd", -0, ADD_I, mk_op2(0x1,I_BYTE,I_BYTE), "cmpb", -0, ADD_I, mk_op2(0x1,I_WORD,I_WORD), "cmpw", -0, ADD_I, mk_op2(0x1,I_DOUBLE,I_DOUBLE), "cmpd", -0, ADD_I, mk_op2(0x0,I_BYTE,I_BYTE), "addb", -0, ADD_I, mk_op2(0x0,I_WORD,I_WORD), "addw", -0, ADD_I, mk_op2(0x0,I_DOUBLE,I_DOUBLE), "addd", -0, ADD_I, mk_op2(0x4,I_BYTE,I_BYTE), "addcb", -0, ADD_I, mk_op2(0x4,I_WORD,I_WORD), "addcw", -0, ADD_I, mk_op2(0x4,I_DOUBLE,I_DOUBLE), "addcd", -0, ADD_I, mk_op2(0x8,I_BYTE,I_BYTE), "subb", -0, ADD_I, mk_op2(0x8,I_WORD,I_WORD), "subw", -0, ADD_I, mk_op2(0x8,I_DOUBLE,I_DOUBLE), "subd", -0, ADD_I, mk_op2(0xC,I_BYTE,I_BYTE), "subcb", -0, ADD_I, mk_op2(0xC,I_WORD,I_WORD), "subcw", -0, ADD_I, mk_op2(0xC,I_DOUBLE,I_DOUBLE), "subcd", -0, COM, mk_op2(0x8,I_BYTE,I_BYTE), "negb", -0, COM, mk_op2(0x8,I_WORD,I_WORD), "negw", -0, COM, mk_op2(0x8,I_DOUBLE,I_DOUBLE), "negd", -0, COM, mk_op2(0xC,I_BYTE,I_BYTE), "absb", -0, COM, mk_op2(0xC,I_WORD,I_WORD), "absw", -0, COM, mk_op2(0xC,I_DOUBLE,I_DOUBLE), "absd", -0, MUL_I, mk_op2(0x8,I_BYTE,I_BYTE), "mulb", -0, MUL_I, mk_op2(0x8,I_WORD,I_WORD), "mulw", -0, MUL_I, mk_op2(0x8,I_DOUBLE,I_DOUBLE), "muld", -0, MUL_I, mk_op2(0xF,I_BYTE,I_BYTE), "divb", -0, MUL_I, mk_op2(0xF,I_WORD,I_WORD), "divw", -0, MUL_I, mk_op2(0xF,I_DOUBLE,I_DOUBLE), "divd", -0, MUL_I, mk_op2(0xE,I_BYTE,I_BYTE), "modb", -0, MUL_I, mk_op2(0xE,I_WORD,I_WORD), "modw", -0, MUL_I, mk_op2(0xE,I_DOUBLE,I_DOUBLE), "modd", -0, MUL_I, mk_op2(0xC,I_BYTE,I_BYTE), "quob", -0, MUL_I, mk_op2(0xC,I_WORD,I_WORD), "quow", -0, MUL_I, mk_op2(0xC,I_DOUBLE,I_DOUBLE), "quod", -0, MUL_I, mk_op2(0xD,I_BYTE,I_BYTE), "remb", -0, MUL_I, mk_op2(0xD,I_WORD,I_WORD), "remw", -0, MUL_I, mk_op2(0xD,I_DOUBLE,I_DOUBLE), "remd", -0, ADD_I, mk_op2(0xA,I_BYTE,I_BYTE), "andb", -0, ADD_I, mk_op2(0xA,I_WORD,I_WORD), "andw", -0, ADD_I, mk_op2(0xA,I_DOUBLE,I_DOUBLE), "andd", -0, ADD_I, mk_op2(0x6,I_BYTE,I_BYTE), "orb", -0, ADD_I, mk_op2(0x6,I_WORD,I_WORD), "orw", -0, ADD_I, mk_op2(0x6,I_DOUBLE,I_DOUBLE), "ord", -0, ADD_I, mk_op2(0x2,I_BYTE,I_BYTE), "bicb", -0, ADD_I, mk_op2(0x2,I_WORD,I_WORD), "bicw", -0, ADD_I, mk_op2(0x2,I_DOUBLE,I_DOUBLE), "bicd", -0, ADD_I, mk_op2(0xE,I_BYTE,I_BYTE), "xorb", -0, ADD_I, mk_op2(0xE,I_WORD,I_WORD), "xorw", -0, ADD_I, mk_op2(0xE,I_DOUBLE,I_DOUBLE), "xord", -0, COM, mk_op2(0xD,I_BYTE,I_BYTE), "comb", -0, COM, mk_op2(0xD,I_WORD,I_WORD), "comw", -0, COM, mk_op2(0xD,I_DOUBLE,I_DOUBLE), "comd", -0, COM, mk_op2(0x1,I_BYTE,I_BYTE), "ashb", -0, COM, mk_op2(0x1,I_BYTE,I_WORD), "ashw", -0, COM, mk_op2(0x1,I_BYTE,I_DOUBLE), "ashd", -0, COM, mk_op2(0x5,I_BYTE,I_BYTE), "lshb", -0, COM, mk_op2(0x5,I_BYTE,I_WORD), "lshw", -0, COM, mk_op2(0x5,I_BYTE,I_DOUBLE), "lshd", -0, COM, mk_op2(0x0,I_BYTE,I_BYTE), "rotb", -0, COM, mk_op2(0x0,I_BYTE,I_WORD), "rotw", -0, COM, mk_op2(0x0,I_BYTE,I_DOUBLE), "rotd", -0, MOVID, mk_op2(0x4,I_BYTE,I_WORD), "movxbw", -0, MOVID, mk_op2(0x7,I_BYTE,I_DOUBLE), "movxbd", -0, MOVID, mk_op2(0x7,I_WORD,I_DOUBLE), "movxwd", -0, MOVID, mk_op2(0x5,I_BYTE,I_WORD), "movzbw", -0, MOVID, mk_op2(0x6,I_BYTE,I_DOUBLE), "movzbd", -0, MOVID, mk_op2(0x6,I_WORD,I_DOUBLE), "movzwd", +{0, ADD_I, mk_op2(0x5,I_BYTE,I_BYTE), "movb"}, +{0, ADD_I, mk_op2(0x5,I_WORD,I_WORD), "movw"}, +{0, ADD_I, mk_op2(0x5,I_DOUBLE,I_DOUBLE), "movd"}, +{0, ADD_I, mk_op2(0x1,I_BYTE,I_BYTE), "cmpb"}, +{0, ADD_I, mk_op2(0x1,I_WORD,I_WORD), "cmpw"}, +{0, ADD_I, mk_op2(0x1,I_DOUBLE,I_DOUBLE), "cmpd"}, +{0, ADD_I, mk_op2(0x0,I_BYTE,I_BYTE), "addb"}, +{0, ADD_I, mk_op2(0x0,I_WORD,I_WORD), "addw"}, +{0, ADD_I, mk_op2(0x0,I_DOUBLE,I_DOUBLE), "addd"}, +{0, ADD_I, mk_op2(0x4,I_BYTE,I_BYTE), "addcb"}, +{0, ADD_I, mk_op2(0x4,I_WORD,I_WORD), "addcw"}, +{0, ADD_I, mk_op2(0x4,I_DOUBLE,I_DOUBLE), "addcd"}, +{0, ADD_I, mk_op2(0x8,I_BYTE,I_BYTE), "subb"}, +{0, ADD_I, mk_op2(0x8,I_WORD,I_WORD), "subw"}, +{0, ADD_I, mk_op2(0x8,I_DOUBLE,I_DOUBLE), "subd"}, +{0, ADD_I, mk_op2(0xC,I_BYTE,I_BYTE), "subcb"}, +{0, ADD_I, mk_op2(0xC,I_WORD,I_WORD), "subcw"}, +{0, ADD_I, mk_op2(0xC,I_DOUBLE,I_DOUBLE), "subcd"}, +{0, COM, mk_op2(0x8,I_BYTE,I_BYTE), "negb"}, +{0, COM, mk_op2(0x8,I_WORD,I_WORD), "negw"}, +{0, COM, mk_op2(0x8,I_DOUBLE,I_DOUBLE), "negd"}, +{0, COM, mk_op2(0xC,I_BYTE,I_BYTE), "absb"}, +{0, COM, mk_op2(0xC,I_WORD,I_WORD), "absw"}, +{0, COM, mk_op2(0xC,I_DOUBLE,I_DOUBLE), "absd"}, +{0, MUL_I, mk_op2(0x8,I_BYTE,I_BYTE), "mulb"}, +{0, MUL_I, mk_op2(0x8,I_WORD,I_WORD), "mulw"}, +{0, MUL_I, mk_op2(0x8,I_DOUBLE,I_DOUBLE), "muld"}, +{0, MUL_I, mk_op2(0xF,I_BYTE,I_BYTE), "divb"}, +{0, MUL_I, mk_op2(0xF,I_WORD,I_WORD), "divw"}, +{0, MUL_I, mk_op2(0xF,I_DOUBLE,I_DOUBLE), "divd"}, +{0, MUL_I, mk_op2(0xE,I_BYTE,I_BYTE), "modb"}, +{0, MUL_I, mk_op2(0xE,I_WORD,I_WORD), "modw"}, +{0, MUL_I, mk_op2(0xE,I_DOUBLE,I_DOUBLE), "modd"}, +{0, MUL_I, mk_op2(0xC,I_BYTE,I_BYTE), "quob"}, +{0, MUL_I, mk_op2(0xC,I_WORD,I_WORD), "quow"}, +{0, MUL_I, mk_op2(0xC,I_DOUBLE,I_DOUBLE), "quod"}, +{0, MUL_I, mk_op2(0xD,I_BYTE,I_BYTE), "remb"}, +{0, MUL_I, mk_op2(0xD,I_WORD,I_WORD), "remw"}, +{0, MUL_I, mk_op2(0xD,I_DOUBLE,I_DOUBLE), "remd"}, +{0, ADD_I, mk_op2(0xA,I_BYTE,I_BYTE), "andb"}, +{0, ADD_I, mk_op2(0xA,I_WORD,I_WORD), "andw"}, +{0, ADD_I, mk_op2(0xA,I_DOUBLE,I_DOUBLE), "andd"}, +{0, ADD_I, mk_op2(0x6,I_BYTE,I_BYTE), "orb"}, +{0, ADD_I, mk_op2(0x6,I_WORD,I_WORD), "orw"}, +{0, ADD_I, mk_op2(0x6,I_DOUBLE,I_DOUBLE), "ord"}, +{0, ADD_I, mk_op2(0x2,I_BYTE,I_BYTE), "bicb"}, +{0, ADD_I, mk_op2(0x2,I_WORD,I_WORD), "bicw"}, +{0, ADD_I, mk_op2(0x2,I_DOUBLE,I_DOUBLE), "bicd"}, +{0, ADD_I, mk_op2(0xE,I_BYTE,I_BYTE), "xorb"}, +{0, ADD_I, mk_op2(0xE,I_WORD,I_WORD), "xorw"}, +{0, ADD_I, mk_op2(0xE,I_DOUBLE,I_DOUBLE), "xord"}, +{0, COM, mk_op2(0xD,I_BYTE,I_BYTE), "comb"}, +{0, COM, mk_op2(0xD,I_WORD,I_WORD), "comw"}, +{0, COM, mk_op2(0xD,I_DOUBLE,I_DOUBLE), "comd"}, +{0, COM, mk_op2(0x1,I_BYTE,I_BYTE), "ashb"}, +{0, COM, mk_op2(0x1,I_BYTE,I_WORD), "ashw"}, +{0, COM, mk_op2(0x1,I_BYTE,I_DOUBLE), "ashd"}, +{0, COM, mk_op2(0x5,I_BYTE,I_BYTE), "lshb"}, +{0, COM, mk_op2(0x5,I_BYTE,I_WORD), "lshw"}, +{0, COM, mk_op2(0x5,I_BYTE,I_DOUBLE), "lshd"}, +{0, COM, mk_op2(0x0,I_BYTE,I_BYTE), "rotb"}, +{0, COM, mk_op2(0x0,I_BYTE,I_WORD), "rotw"}, +{0, COM, mk_op2(0x0,I_BYTE,I_DOUBLE), "rotd"}, +{0, MOVID, mk_op2(0x4,I_BYTE,I_WORD), "movxbw"}, +{0, MOVID, mk_op2(0x7,I_BYTE,I_DOUBLE), "movxbd"}, +{0, MOVID, mk_op2(0x7,I_WORD,I_DOUBLE), "movxwd"}, +{0, MOVID, mk_op2(0x5,I_BYTE,I_WORD), "movzbw"}, +{0, MOVID, mk_op2(0x6,I_BYTE,I_DOUBLE), "movzbd"}, +{0, MOVID, mk_op2(0x6,I_WORD,I_DOUBLE), "movzwd"}, #ifdef UNUSED -0, MOVID, mk_op2(0x7,I_DOUBLE,I_DOUBLE), "movxdd", -0, MOVID, mk_op2(0x6,I_DOUBLE,I_DOUBLE), "movzdd", +{0, MOVID, mk_op2(0x7,I_DOUBLE,I_DOUBLE), "movxdd"}, +{0, MOVID, mk_op2(0x6,I_DOUBLE,I_DOUBLE), "movzdd"}, #endif -0, ADD_I, mk_op2(0x9,I_DOUBLE,I_DOUBLE), "addr", +{0, ADD_I, mk_op2(0x9,I_DOUBLE,I_DOUBLE), "addr"}, /* Quick integer instructions */ -0, MOVQ, mk_op1(0x5,I_BYTE), "movqb", -0, MOVQ, mk_op1(0x5,I_WORD), "movqw", -0, MOVQ, mk_op1(0x5,I_DOUBLE), "movqd", -0, MOVQ, mk_op1(0x1,I_BYTE), "cmpqb", -0, MOVQ, mk_op1(0x1,I_WORD), "cmpqw", -0, MOVQ, mk_op1(0x1,I_DOUBLE), "cmpqd", -0, MOVQ, mk_op1(0x0,I_BYTE), "addqb", -0, MOVQ, mk_op1(0x0,I_WORD), "addqw", -0, MOVQ, mk_op1(0x0,I_DOUBLE), "addqd", +{0, MOVQ, mk_op1(0x5,I_BYTE), "movqb"}, +{0, MOVQ, mk_op1(0x5,I_WORD), "movqw"}, +{0, MOVQ, mk_op1(0x5,I_DOUBLE), "movqd"}, +{0, MOVQ, mk_op1(0x1,I_BYTE), "cmpqb"}, +{0, MOVQ, mk_op1(0x1,I_WORD), "cmpqw"}, +{0, MOVQ, mk_op1(0x1,I_DOUBLE), "cmpqd"}, +{0, MOVQ, mk_op1(0x0,I_BYTE), "addqb"}, +{0, MOVQ, mk_op1(0x0,I_WORD), "addqw"}, +{0, MOVQ, mk_op1(0x0,I_DOUBLE), "addqd"}, /* Extended integer instructions */ -0, MUL_I, mk_op2(0x9,I_BYTE,I_BYTE), "meib", -0, MUL_I, mk_op2(0x9,I_WORD,I_WORD), "meiw", -0, MUL_I, mk_op2(0x9,I_DOUBLE,I_DOUBLE), "meid", -0, MUL_I, mk_op2(0xB,I_BYTE,I_BYTE), "deib", -0, MUL_I, mk_op2(0xB,I_WORD,I_WORD), "deiw", -0, MUL_I, mk_op2(0xB,I_DOUBLE,I_DOUBLE), "deid", +{0, MUL_I, mk_op2(0x9,I_BYTE,I_BYTE), "meib"}, +{0, MUL_I, mk_op2(0x9,I_WORD,I_WORD), "meiw"}, +{0, MUL_I, mk_op2(0x9,I_DOUBLE,I_DOUBLE), "meid"}, +{0, MUL_I, mk_op2(0xB,I_BYTE,I_BYTE), "deib"}, +{0, MUL_I, mk_op2(0xB,I_WORD,I_WORD), "deiw"}, +{0, MUL_I, mk_op2(0xB,I_DOUBLE,I_DOUBLE), "deid"}, /* Boolean instructions */ -0, COM, mk_op2(0x9,I_BYTE,I_BYTE), "notb", -0, COM, mk_op2(0x9,I_WORD,I_WORD), "notw", -0, COM, mk_op2(0x9,I_DOUBLE,I_DOUBLE), "notd", -0, SEQ, mk_op1c(0x3,I_BYTE,B_EQ), "seqb", -0, SEQ, mk_op1c(0x3,I_WORD,B_EQ), "seqw", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_EQ), "seqd", -0, SEQ, mk_op1c(0x3,I_BYTE,B_NE), "sneb", -0, SEQ, mk_op1c(0x3,I_WORD,B_NE), "snew", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_NE), "sned", -0, SEQ, mk_op1c(0x3,I_BYTE,B_CS), "scsb", -0, SEQ, mk_op1c(0x3,I_WORD,B_CS), "scsw", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_CS), "scsd", -0, SEQ, mk_op1c(0x3,I_BYTE,B_CC), "sccb", -0, SEQ, mk_op1c(0x3,I_WORD,B_CC), "sccw", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_CC), "sccd", -0, SEQ, mk_op1c(0x3,I_BYTE,B_HI), "shib", -0, SEQ, mk_op1c(0x3,I_WORD,B_HI), "shiw", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_HI), "shid", -0, SEQ, mk_op1c(0x3,I_BYTE,B_LS), "slsb", -0, SEQ, mk_op1c(0x3,I_WORD,B_LS), "slsw", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_LS), "slsd", -0, SEQ, mk_op1c(0x3,I_BYTE,B_GT), "sgtb", -0, SEQ, mk_op1c(0x3,I_WORD,B_GT), "sgtw", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_GT), "sgtd", -0, SEQ, mk_op1c(0x3,I_BYTE,B_LE), "sleb", -0, SEQ, mk_op1c(0x3,I_WORD,B_LE), "slew", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_LE), "sled", -0, SEQ, mk_op1c(0x3,I_BYTE,B_FS), "sfsb", -0, SEQ, mk_op1c(0x3,I_WORD,B_FS), "sfsw", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_FS), "sfsd", -0, SEQ, mk_op1c(0x3,I_BYTE,B_FC), "sfcb", -0, SEQ, mk_op1c(0x3,I_WORD,B_FC), "sfcw", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_FC), "sfcd", -0, SEQ, mk_op1c(0x3,I_BYTE,B_LO), "slob", -0, SEQ, mk_op1c(0x3,I_WORD,B_LO), "slow", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_LO), "slod", -0, SEQ, mk_op1c(0x3,I_BYTE,B_HS), "shsb", -0, SEQ, mk_op1c(0x3,I_WORD,B_HS), "shsw", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_HS), "shsd", -0, SEQ, mk_op1c(0x3,I_BYTE,B_LT), "sltb", -0, SEQ, mk_op1c(0x3,I_WORD,B_LT), "sltw", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_LT), "sltd", -0, SEQ, mk_op1c(0x3,I_BYTE,B_GE), "sgeb", -0, SEQ, mk_op1c(0x3,I_WORD,B_GE), "sgew", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_GE), "sged", +{0, COM, mk_op2(0x9,I_BYTE,I_BYTE), "notb"}, +{0, COM, mk_op2(0x9,I_WORD,I_WORD), "notw"}, +{0, COM, mk_op2(0x9,I_DOUBLE,I_DOUBLE), "notd"}, +{0, SEQ, mk_op1c(0x3,I_BYTE,B_EQ), "seqb"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_EQ), "seqw"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_EQ), "seqd"}, +{0, SEQ, mk_op1c(0x3,I_BYTE,B_NE), "sneb"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_NE), "snew"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_NE), "sned"}, +{0, SEQ, mk_op1c(0x3,I_BYTE,B_CS), "scsb"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_CS), "scsw"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_CS), "scsd"}, +{0, SEQ, mk_op1c(0x3,I_BYTE,B_CC), "sccb"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_CC), "sccw"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_CC), "sccd"}, +{0, SEQ, mk_op1c(0x3,I_BYTE,B_HI), "shib"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_HI), "shiw"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_HI), "shid"}, +{0, SEQ, mk_op1c(0x3,I_BYTE,B_LS), "slsb"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_LS), "slsw"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_LS), "slsd"}, +{0, SEQ, mk_op1c(0x3,I_BYTE,B_GT), "sgtb"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_GT), "sgtw"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_GT), "sgtd"}, +{0, SEQ, mk_op1c(0x3,I_BYTE,B_LE), "sleb"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_LE), "slew"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_LE), "sled"}, +{0, SEQ, mk_op1c(0x3,I_BYTE,B_FS), "sfsb"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_FS), "sfsw"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_FS), "sfsd"}, +{0, SEQ, mk_op1c(0x3,I_BYTE,B_FC), "sfcb"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_FC), "sfcw"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_FC), "sfcd"}, +{0, SEQ, mk_op1c(0x3,I_BYTE,B_LO), "slob"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_LO), "slow"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_LO), "slod"}, +{0, SEQ, mk_op1c(0x3,I_BYTE,B_HS), "shsb"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_HS), "shsw"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_HS), "shsd"}, +{0, SEQ, mk_op1c(0x3,I_BYTE,B_LT), "sltb"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_LT), "sltw"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_LT), "sltd"}, +{0, SEQ, mk_op1c(0x3,I_BYTE,B_GE), "sgeb"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_GE), "sgew"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_GE), "sged"}, #ifdef UNUSED -0, SEQ, mk_op1c(0x3,I_BYTE,B_TRUE), "strueb", -0, SEQ, mk_op1c(0x3,I_WORD,B_TRUE), "struew", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_TRUE), "strued", -0, SEQ, mk_op1c(0x3,I_BYTE,B_FALSE), "sfalseb", -0, SEQ, mk_op1c(0x3,I_WORD,B_FALSE), "sfalsew", -0, SEQ, mk_op1c(0x3,I_DOUBLE,B_FALSE), "sfalsed", +{0, SEQ, mk_op1c(0x3,I_BYTE,B_TRUE), "strueb"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_TRUE), "struew"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_TRUE), "strued"}, +{0, SEQ, mk_op1c(0x3,I_BYTE,B_FALSE), "sfalseb"}, +{0, SEQ, mk_op1c(0x3,I_WORD,B_FALSE), "sfalsew"}, +{0, SEQ, mk_op1c(0x3,I_DOUBLE,B_FALSE), "sfalsed"}, #endif /* Bit instructions */ -0, ADD_I, mk_op2(0xD,I_BYTE,I_BYTE), "tbitb", -0, ADD_I, mk_op2(0xD,I_WORD,I_WORD), "tbitw", -0, ADD_I, mk_op2(0xD,I_DOUBLE,I_DOUBLE), "tbitd", -0, COM, mk_op2(0x6,I_BYTE,I_BYTE), "sbitb", -0, COM, mk_op2(0x6,I_WORD,I_WORD), "sbitw", -0, COM, mk_op2(0x6,I_DOUBLE,I_DOUBLE), "sbitd", -0, COM, mk_op2(0x7,I_BYTE,I_BYTE), "sbitib", -0, COM, mk_op2(0x7,I_WORD,I_WORD), "sbitiw", -0, COM, mk_op2(0x7,I_DOUBLE,I_DOUBLE), "sbitid", -0, COM, mk_op2(0x2,I_BYTE,I_BYTE), "cbitb", -0, COM, mk_op2(0x2,I_WORD,I_WORD), "cbitw", -0, COM, mk_op2(0x2,I_DOUBLE,I_DOUBLE), "cbitd", -0, COM, mk_op2(0x3,I_BYTE,I_BYTE), "cbitib", -0, COM, mk_op2(0x3,I_WORD,I_WORD), "cbitiw", -0, COM, mk_op2(0x3,I_DOUBLE,I_DOUBLE), "cbitid", -0, COM, mk_op2(0xE,I_BYTE,I_BYTE), "ibitb", -0, COM, mk_op2(0xE,I_WORD,I_WORD), "ibitw", -0, COM, mk_op2(0xE,I_DOUBLE,I_DOUBLE), "ibitd", -0, CHECK, mk_op1(0x1,I_DOUBLE), "cvtp", -0, FFS, mk_op2c(0x5,I_BYTE,I_BYTE,0), "ffsb", -0, FFS, mk_op2c(0x5,I_WORD,I_BYTE,0), "ffsw", -0, FFS, mk_op2c(0x5,I_DOUBLE,I_BYTE,0), "ffsd", +{0, ADD_I, mk_op2(0xD,I_BYTE,I_BYTE), "tbitb"}, +{0, ADD_I, mk_op2(0xD,I_WORD,I_WORD), "tbitw"}, +{0, ADD_I, mk_op2(0xD,I_DOUBLE,I_DOUBLE), "tbitd"}, +{0, COM, mk_op2(0x6,I_BYTE,I_BYTE), "sbitb"}, +{0, COM, mk_op2(0x6,I_WORD,I_WORD), "sbitw"}, +{0, COM, mk_op2(0x6,I_DOUBLE,I_DOUBLE), "sbitd"}, +{0, COM, mk_op2(0x7,I_BYTE,I_BYTE), "sbitib"}, +{0, COM, mk_op2(0x7,I_WORD,I_WORD), "sbitiw"}, +{0, COM, mk_op2(0x7,I_DOUBLE,I_DOUBLE), "sbitid"}, +{0, COM, mk_op2(0x2,I_BYTE,I_BYTE), "cbitb"}, +{0, COM, mk_op2(0x2,I_WORD,I_WORD), "cbitw"}, +{0, COM, mk_op2(0x2,I_DOUBLE,I_DOUBLE), "cbitd"}, +{0, COM, mk_op2(0x3,I_BYTE,I_BYTE), "cbitib"}, +{0, COM, mk_op2(0x3,I_WORD,I_WORD), "cbitiw"}, +{0, COM, mk_op2(0x3,I_DOUBLE,I_DOUBLE), "cbitid"}, +{0, COM, mk_op2(0xE,I_BYTE,I_BYTE), "ibitb"}, +{0, COM, mk_op2(0xE,I_WORD,I_WORD), "ibitw"}, +{0, COM, mk_op2(0xE,I_DOUBLE,I_DOUBLE), "ibitd"}, +{0, CHECK, mk_op1(0x1,I_DOUBLE), "cvtp"}, +{0, FFS, mk_op2c(0x5,I_BYTE,I_BYTE,0), "ffsb"}, +{0, FFS, mk_op2c(0x5,I_WORD,I_BYTE,0), "ffsw"}, +{0, FFS, mk_op2c(0x5,I_DOUBLE,I_BYTE,0), "ffsd"}, /* Field instructions */ -0, INS, mk_op2(0x0,I_BYTE,I_BYTE), "extb", -0, INS, mk_op2(0x0,I_WORD,I_WORD), "extw", -0, INS, mk_op2(0x0,I_DOUBLE,I_DOUBLE), "extd", -0, INSS, mk_op2(0x3,I_BYTE,I_BYTE), "extsb", -0, INSS, mk_op2(0x3,I_WORD,I_WORD), "extsw", -0, INSS, mk_op2(0x3,I_DOUBLE,I_DOUBLE), "extsd", -0, INS, mk_op2(0x2,I_BYTE,I_BYTE), "insb", -0, INS, mk_op2(0x2,I_WORD,I_WORD), "insw", -0, INS, mk_op2(0x2,I_DOUBLE,I_DOUBLE), "insd", -0, INSS, mk_op2(0x2,I_BYTE,I_BYTE), "inssb", -0, INSS, mk_op2(0x2,I_WORD,I_WORD), "inssw", -0, INSS, mk_op2(0x2,I_DOUBLE,I_DOUBLE), "inssd", +{0, INS, mk_op2(0x0,I_BYTE,I_BYTE), "extb"}, +{0, INS, mk_op2(0x0,I_WORD,I_WORD), "extw"}, +{0, INS, mk_op2(0x0,I_DOUBLE,I_DOUBLE), "extd"}, +{0, INSS, mk_op2(0x3,I_BYTE,I_BYTE), "extsb"}, +{0, INSS, mk_op2(0x3,I_WORD,I_WORD), "extsw"}, +{0, INSS, mk_op2(0x3,I_DOUBLE,I_DOUBLE), "extsd"}, +{0, INS, mk_op2(0x2,I_BYTE,I_BYTE), "insb"}, +{0, INS, mk_op2(0x2,I_WORD,I_WORD), "insw"}, +{0, INS, mk_op2(0x2,I_DOUBLE,I_DOUBLE), "insd"}, +{0, INSS, mk_op2(0x2,I_BYTE,I_BYTE), "inssb"}, +{0, INSS, mk_op2(0x2,I_WORD,I_WORD), "inssw"}, +{0, INSS, mk_op2(0x2,I_DOUBLE,I_DOUBLE), "inssd"}, /* String instructions */ -0, MOVS, mk_op1c(0x0,I_BYTE,0), "movsb", -0, MOVS, mk_op1c(0x0,I_WORD,0), "movsw", -0, MOVS, mk_op1c(0x0,I_DOUBLE,0), "movsd", -0, MOVS, mk_op1c(0x0,I_BYTE,SO_TRANS), "movst", -0, MOVS, mk_op1c(0x1,I_BYTE,0), "cmpsb", -0, MOVS, mk_op1c(0x1,I_WORD,0), "cmpsw", -0, MOVS, mk_op1c(0x1,I_DOUBLE,0), "cmpsd", -0, MOVS, mk_op1c(0x1,I_BYTE,SO_TRANS), "cmpst", -0, MOVS, mk_op1c(0x3,I_BYTE,0), "skpsb", -0, MOVS, mk_op1c(0x3,I_WORD,0), "skpsw", -0, MOVS, mk_op1c(0x3,I_DOUBLE,0), "skpsd", -0, MOVS, mk_op1c(0x3,I_BYTE,SO_TRANS), "skpst", +{0, MOVS, mk_op1c(0x0,I_BYTE,0), "movsb"}, +{0, MOVS, mk_op1c(0x0,I_WORD,0), "movsw"}, +{0, MOVS, mk_op1c(0x0,I_DOUBLE,0), "movsd"}, +{0, MOVS, mk_op1c(0x0,I_BYTE,SO_TRANS), "movst"}, +{0, MOVS, mk_op1c(0x1,I_BYTE,0), "cmpsb"}, +{0, MOVS, mk_op1c(0x1,I_WORD,0), "cmpsw"}, +{0, MOVS, mk_op1c(0x1,I_DOUBLE,0), "cmpsd"}, +{0, MOVS, mk_op1c(0x1,I_BYTE,SO_TRANS), "cmpst"}, +{0, MOVS, mk_op1c(0x3,I_BYTE,0), "skpsb"}, +{0, MOVS, mk_op1c(0x3,I_WORD,0), "skpsw"}, +{0, MOVS, mk_op1c(0x3,I_DOUBLE,0), "skpsd"}, +{0, MOVS, mk_op1c(0x3,I_BYTE,SO_TRANS), "skpst"}, /* Block instructions */ -0, MOVM, mk_op2(0x0,I_BYTE,I_BYTE), "movmb", -0, MOVM, mk_op2(0x0,I_WORD,I_WORD), "movmw", -0, MOVM, mk_op2(0x0,I_DOUBLE,I_DOUBLE), "movmd", -0, MOVM, mk_op2(0x1,I_BYTE,I_BYTE), "cmpmb", -0, MOVM, mk_op2(0x1,I_WORD,I_WORD), "cmpmw", -0, MOVM, mk_op2(0x1,I_DOUBLE,I_DOUBLE), "cmpmd", +{0, MOVM, mk_op2(0x0,I_BYTE,I_BYTE), "movmb"}, +{0, MOVM, mk_op2(0x0,I_WORD,I_WORD), "movmw"}, +{0, MOVM, mk_op2(0x0,I_DOUBLE,I_DOUBLE), "movmd"}, +{0, MOVM, mk_op2(0x1,I_BYTE,I_BYTE), "cmpmb"}, +{0, MOVM, mk_op2(0x1,I_WORD,I_WORD), "cmpmw"}, +{0, MOVM, mk_op2(0x1,I_DOUBLE,I_DOUBLE), "cmpmd"}, /* Packed decimal instructions */ -0, COM, mk_op2(0xF,I_BYTE,I_BYTE), "addpb", -0, COM, mk_op2(0xF,I_WORD,I_WORD), "addpw", -0, COM, mk_op2(0xF,I_DOUBLE,I_DOUBLE), "addpd", -0, COM, mk_op2(0xB,I_BYTE,I_BYTE), "subpb", -0, COM, mk_op2(0xB,I_WORD,I_WORD), "subpw", -0, COM, mk_op2(0xB,I_DOUBLE,I_DOUBLE), "subpd", +{0, COM, mk_op2(0xF,I_BYTE,I_BYTE), "addpb"}, +{0, COM, mk_op2(0xF,I_WORD,I_WORD), "addpw"}, +{0, COM, mk_op2(0xF,I_DOUBLE,I_DOUBLE), "addpd"}, +{0, COM, mk_op2(0xB,I_BYTE,I_BYTE), "subpb"}, +{0, COM, mk_op2(0xB,I_WORD,I_WORD), "subpw"}, +{0, COM, mk_op2(0xB,I_DOUBLE,I_DOUBLE), "subpd"}, /* Array instructions */ -0, CHECK, mk_op2(0x4,I_BYTE,I_BYTE), "indexb", -0, CHECK, mk_op2(0x4,I_WORD,I_WORD), "indexw", -0, CHECK, mk_op2(0x4,I_DOUBLE,I_DOUBLE), "indexd", -0, CHECK, mk_op2(0x3,I_BYTE,I_BYTE), "checkb", -0, CHECK, mk_op2(0x3,I_WORD,I_WORD), "checkw", -0, CHECK, mk_op2(0x3,I_DOUBLE,I_DOUBLE), "checkd", +{0, CHECK, mk_op2(0x4,I_BYTE,I_BYTE), "indexb"}, +{0, CHECK, mk_op2(0x4,I_WORD,I_WORD), "indexw"}, +{0, CHECK, mk_op2(0x4,I_DOUBLE,I_DOUBLE), "indexd"}, +{0, CHECK, mk_op2(0x3,I_BYTE,I_BYTE), "checkb"}, +{0, CHECK, mk_op2(0x3,I_WORD,I_WORD), "checkw"}, +{0, CHECK, mk_op2(0x3,I_DOUBLE,I_DOUBLE), "checkd"}, /* Processor control instructions */ -0, JUMP, mk_op1(0x4,I_DOUBLE), "jump", -0, BR, mk_c(B_EQ), "beq", -0, BR, mk_c(B_NE), "bne", -0, BR, mk_c(B_CS), "bcs", -0, BR, mk_c(B_CC), "bcc", -0, BR, mk_c(B_HI), "bhi", -0, BR, mk_c(B_LS), "bls", -0, BR, mk_c(B_GT), "bgt", -0, BR, mk_c(B_LE), "ble", -0, BR, mk_c(B_FS), "bfs", -0, BR, mk_c(B_FC), "bfc", -0, BR, mk_c(B_LO), "blo", -0, BR, mk_c(B_HS), "bhs", -0, BR, mk_c(B_LT), "blt", -0, BR, mk_c(B_GE), "bge", -0, BR, mk_c(B_TRUE), "br", +{0, JUMP, mk_op1(0x4,I_DOUBLE), "jump"}, +{0, BR, mk_c(B_EQ), "beq"}, +{0, BR, mk_c(B_NE), "bne"}, +{0, BR, mk_c(B_CS), "bcs"}, +{0, BR, mk_c(B_CC), "bcc"}, +{0, BR, mk_c(B_HI), "bhi"}, +{0, BR, mk_c(B_LS), "bls"}, +{0, BR, mk_c(B_GT), "bgt"}, +{0, BR, mk_c(B_LE), "ble"}, +{0, BR, mk_c(B_FS), "bfs"}, +{0, BR, mk_c(B_FC), "bfc"}, +{0, BR, mk_c(B_LO), "blo"}, +{0, BR, mk_c(B_HS), "bhs"}, +{0, BR, mk_c(B_LT), "blt"}, +{0, BR, mk_c(B_GE), "bge"}, +{0, BR, mk_c(B_TRUE), "br"}, #ifdef UNUSED -0, BR, mk_c(B_FALSE), "bfalse", +{0, BR, mk_c(B_FALSE), "bfalse"}, #endif -0, ADJSP, mk_op1(0xE,I_BYTE), "caseb", -0, ADJSP, mk_op1(0xE,I_WORD), "casew", -0, ADJSP, mk_op1(0xE,I_DOUBLE), "cased", -0, ACB, mk_op1(0x4,I_BYTE), "acbb", -0, ACB, mk_op1(0x4,I_WORD), "acbw", -0, ACB, mk_op1(0x4,I_DOUBLE), "acbd", -0, JSR, mk_op1(0xC,I_DOUBLE), "jsr", -0, BSR, mk_op(0x0), "bsr", -0, RET, mk_op(0x1), "ret", -0, RET, mk_op(0x2), "cxp", -0, ADJSP, mk_op1(0x0,I_DOUBLE), "cxpd", -0, RET, mk_op(0x3), "rxp", -0, RET, mk_op(0x4), "rett", -0, WAIT, mk_op(0x5), "reti", -0, WAIT, mk_op(0xC), "dia", +{0, ADJSP, mk_op1(0xE,I_BYTE), "caseb"}, +{0, ADJSP, mk_op1(0xE,I_WORD), "casew"}, +{0, ADJSP, mk_op1(0xE,I_DOUBLE), "cased"}, +{0, ACB, mk_op1(0x4,I_BYTE), "acbb"}, +{0, ACB, mk_op1(0x4,I_WORD), "acbw"}, +{0, ACB, mk_op1(0x4,I_DOUBLE), "acbd"}, +{0, JSR, mk_op1(0xC,I_DOUBLE), "jsr"}, +{0, BSR, mk_op(0x0), "bsr"}, +{0, RET, mk_op(0x1), "ret"}, +{0, RET, mk_op(0x2), "cxp"}, +{0, ADJSP, mk_op1(0x0,I_DOUBLE), "cxpd"}, +{0, RET, mk_op(0x3), "rxp"}, +{0, RET, mk_op(0x4), "rett"}, +{0, WAIT, mk_op(0x5), "reti"}, +{0, WAIT, mk_op(0xC), "dia"}, /* Processor service instructions */ -0, ADJSP, mk_op1(0xA,I_BYTE), "adjspb", -0, ADJSP, mk_op1(0xA,I_WORD), "adjspw", -0, ADJSP, mk_op1(0xA,I_DOUBLE), "adjspd", -0, ADJSP, mk_op1(0x2,I_BYTE), "bicpsrb", -0, ADJSP, mk_op1(0x2,I_WORD), "bicpsrw", -0, ADJSP, mk_op1(0x6,I_BYTE), "bispsrb", -0, ADJSP, mk_op1(0x6,I_WORD), "bispsrw", +{0, ADJSP, mk_op1(0xA,I_BYTE), "adjspb"}, +{0, ADJSP, mk_op1(0xA,I_WORD), "adjspw"}, +{0, ADJSP, mk_op1(0xA,I_DOUBLE), "adjspd"}, +{0, ADJSP, mk_op1(0x2,I_BYTE), "bicpsrb"}, +{0, ADJSP, mk_op1(0x2,I_WORD), "bicpsrw"}, +{0, ADJSP, mk_op1(0x6,I_BYTE), "bispsrb"}, +{0, ADJSP, mk_op1(0x6,I_WORD), "bispsrw"}, #ifdef UNUSED -0, ADJSP, mk_op1(0x2,I_DOUBLE), "bicpsrd", -0, ADJSP, mk_op1(0x6,I_DOUBLE), "bispsrd", +{0, ADJSP, mk_op1(0x2,I_DOUBLE), "bicpsrd"}, +{0, ADJSP, mk_op1(0x6,I_DOUBLE), "bispsrd"}, #endif -0, SAVE, mk_op(0x6), "save", -0, SAVE, mk_op(0x7), "restore", -0, ENTER, mk_op(0x8), "enter", -0, SAVE, mk_op(0x9), "exit", -0, LPR, mk_op1(0x6,I_BYTE), "lprb", -0, LPR, mk_op1(0x6,I_WORD), "lprw", -0, LPR, mk_op1(0x6,I_DOUBLE), "lprd", -0, LPR, mk_op1(0x2,I_BYTE), "sprb", -0, LPR, mk_op1(0x2,I_WORD), "sprw", -0, LPR, mk_op1(0x2,I_DOUBLE), "sprd", -0, SETCFG, mk_op1(0x2,I_DOUBLE), "setcfg", -0, WAIT, mk_op(0xF), "bpt", -0, WAIT, mk_op(0xD), "flag", -0, WAIT, mk_op(0xE), "svc", -0, WAIT, mk_op(0xA), "nop", -0, WAIT, mk_op(0xB), "wait", +{0, SAVE, mk_op(0x6), "save"}, +{0, SAVE, mk_op(0x7), "restore"}, +{0, ENTER, mk_op(0x8), "enter"}, +{0, SAVE, mk_op(0x9), "exit"}, +{0, LPR, mk_op1(0x6,I_BYTE), "lprb"}, +{0, LPR, mk_op1(0x6,I_WORD), "lprw"}, +{0, LPR, mk_op1(0x6,I_DOUBLE), "lprd"}, +{0, LPR, mk_op1(0x2,I_BYTE), "sprb"}, +{0, LPR, mk_op1(0x2,I_WORD), "sprw"}, +{0, LPR, mk_op1(0x2,I_DOUBLE), "sprd"}, +{0, SETCFG, mk_op1(0x2,I_DOUBLE), "setcfg"}, +{0, WAIT, mk_op(0xF), "bpt"}, +{0, WAIT, mk_op(0xD), "flag"}, +{0, WAIT, mk_op(0xE), "svc"}, +{0, WAIT, mk_op(0xA), "nop"}, +{0, WAIT, mk_op(0xB), "wait"}, /* Memory management instructions */ -0, LMR, mk_op1(0x2,I_DOUBLE), "lmr", -0, LMR, mk_op1(0x3,I_DOUBLE), "smr", -0, RDVAL, mk_op1(0x0,I_DOUBLE), "rdval", -0, RDVAL, mk_op1(0x1,I_DOUBLE), "wrval", +{0, LMR, mk_op1(0x2,I_DOUBLE), "lmr"}, +{0, LMR, mk_op1(0x3,I_DOUBLE), "smr"}, +{0, RDVAL, mk_op1(0x0,I_DOUBLE), "rdval"}, +{0, RDVAL, mk_op1(0x1,I_DOUBLE), "wrval"}, #ifdef SU_ASSEM /* The assembler ref. man and the CPU description booklet differ in the encoding of these instructions */ -0, FFS, mk_op2c(0x6,I_BYTE,I_BYTE,1), "movsub", -0, FFS, mk_op2c(0x6,I_WORD,I_WORD,1), "movsuw", -0, FFS, mk_op2c(0x6,I_DOUBLE,I_DOUBLE,1),"movsud", -0, FFS, mk_op2c(0x6,I_BYTE,I_BYTE,3), "movusb", -0, FFS, mk_op2c(0x6,I_WORD,I_WORD,3), "movusw", -0, FFS, mk_op2c(0x6,I_DOUBLE,I_DOUBLE,3),"movusd", +{0, FFS, mk_op2c(0x6,I_BYTE,I_BYTE,1), "movsub"}, +{0, FFS, mk_op2c(0x6,I_WORD,I_WORD,1), "movsuw"}, +{0, FFS, mk_op2c(0x6,I_DOUBLE,I_DOUBLE,1),"movsud"}, +{0, FFS, mk_op2c(0x6,I_BYTE,I_BYTE,3), "movusb"}, +{0, FFS, mk_op2c(0x6,I_WORD,I_WORD,3), "movusw"}, +{0, FFS, mk_op2c(0x6,I_DOUBLE,I_DOUBLE,3),"movusd"}, #else /* assembler reference manual version */ -0, FFS, mk_op2c(0x7,I_BYTE,I_BYTE,0), "movsub", -0, FFS, mk_op2c(0x7,I_WORD,I_WORD,0), "movsuw", -0, FFS, mk_op2c(0x7,I_DOUBLE,I_DOUBLE,0),"movsud", -0, FFS, mk_op2c(0x6,I_BYTE,I_BYTE,0), "movusb", -0, FFS, mk_op2c(0x6,I_WORD,I_WORD,0), "movusw", -0, FFS, mk_op2c(0x6,I_DOUBLE,I_DOUBLE,0),"movusd", +{0, FFS, mk_op2c(0x7,I_BYTE,I_BYTE,0), "movsub"}, +{0, FFS, mk_op2c(0x7,I_WORD,I_WORD,0), "movsuw"}, +{0, FFS, mk_op2c(0x7,I_DOUBLE,I_DOUBLE,0),"movsud"}, +{0, FFS, mk_op2c(0x6,I_BYTE,I_BYTE,0), "movusb"}, +{0, FFS, mk_op2c(0x6,I_WORD,I_WORD,0), "movusw"}, +{0, FFS, mk_op2c(0x6,I_DOUBLE,I_DOUBLE,0),"movusd"}, #endif /* Floating point instructions */ -0, ADD_F, mk_op2(0xD,F_FLOAT,F_FLOAT), "absf", -0, ADD_F, mk_op2(0xD,F_LONG,F_LONG), "absl", -0, ADD_F, mk_op2(0x0,F_FLOAT,F_FLOAT), "addf", -0, ADD_F, mk_op2(0x0,F_LONG,F_LONG), "addl", -0, ADD_F, mk_op2(0x2,F_FLOAT,F_FLOAT), "cmpf", -0, ADD_F, mk_op2(0x2,F_LONG,F_LONG), "cmpl", -0, ADD_F, mk_op2(0x8,F_FLOAT,F_FLOAT), "divf", -0, ADD_F, mk_op2(0x8,F_LONG,F_LONG), "divl", -0, ADD_F, mk_op2(0xC,F_FLOAT,F_FLOAT), "mulf", -0, ADD_F, mk_op2(0xC,F_LONG,F_LONG), "mull", -0, ADD_F, mk_op2(0x4,F_FLOAT,F_FLOAT), "subf", -0, ADD_F, mk_op2(0x4,F_LONG,F_LONG), "subl", -0, ADD_F, mk_op2(0x5,F_FLOAT,F_FLOAT), "negf", -0, ADD_F, mk_op2(0x5,F_LONG,F_LONG), "negl", -0, ADD_F, mk_op2(0x1,F_FLOAT,F_FLOAT), "movf", -0, ADD_F, mk_op2(0x1,F_LONG,F_LONG), "movl", -0, MOVIF, mk_op2(0x0,I_BYTE,F_FLOAT), "movbf", -0, MOVIF, mk_op2(0x0,I_WORD,F_FLOAT), "movwf", -0, MOVIF, mk_op2(0x0,I_DOUBLE,F_FLOAT), "movdf", -0, MOVIF, mk_op2(0x0,I_BYTE,F_LONG), "movbl", -0, MOVIF, mk_op2(0x0,I_WORD,F_LONG), "movwl", -0, MOVIF, mk_op2(0x0,I_DOUBLE,F_LONG), "movdl", -0, MOVFL, mk_op2(0x3,F_FLOAT,F_LONG), "movfl", -0, MOVFL, mk_op2(0x2,F_LONG,F_FLOAT), "movlf", -0, TRUNC, mk_op2(0x7,F_FLOAT,I_BYTE), "floorfb", -0, TRUNC, mk_op2(0x7,F_FLOAT,I_WORD), "floorfw", -0, TRUNC, mk_op2(0x7,F_FLOAT,I_DOUBLE), "floorfd", -0, TRUNC, mk_op2(0x7,F_LONG,I_BYTE), "floorlb", -0, TRUNC, mk_op2(0x7,F_LONG,I_WORD), "floorlw", -0, TRUNC, mk_op2(0x7,F_LONG,I_DOUBLE), "floorld", -0, TRUNC, mk_op2(0x4,F_FLOAT,I_BYTE), "roundfb", -0, TRUNC, mk_op2(0x4,F_FLOAT,I_WORD), "roundfw", -0, TRUNC, mk_op2(0x4,F_FLOAT,I_DOUBLE), "roundfd", -0, TRUNC, mk_op2(0x4,F_LONG,I_BYTE), "roundlb", -0, TRUNC, mk_op2(0x4,F_LONG,I_WORD), "roundlw", -0, TRUNC, mk_op2(0x4,F_LONG,I_DOUBLE), "roundld", -0, TRUNC, mk_op2(0x5,F_FLOAT,I_BYTE), "truncfb", -0, TRUNC, mk_op2(0x5,F_FLOAT,I_WORD), "truncfw", -0, TRUNC, mk_op2(0x5,F_FLOAT,I_DOUBLE), "truncfd", -0, TRUNC, mk_op2(0x5,F_LONG,I_BYTE), "trunclb", -0, TRUNC, mk_op2(0x5,F_LONG,I_WORD), "trunclw", -0, TRUNC, mk_op2(0x5,F_LONG,I_DOUBLE), "truncld", -0, LFSR, mk_op(0x1), "lfsr", -0, LFSR, mk_op(0x6), "sfsr", +{0, ADD_F, mk_op2(0xD,F_FLOAT,F_FLOAT), "absf"}, +{0, ADD_F, mk_op2(0xD,F_LONG,F_LONG), "absl"}, +{0, ADD_F, mk_op2(0x0,F_FLOAT,F_FLOAT), "addf"}, +{0, ADD_F, mk_op2(0x0,F_LONG,F_LONG), "addl"}, +{0, ADD_F, mk_op2(0x2,F_FLOAT,F_FLOAT), "cmpf"}, +{0, ADD_F, mk_op2(0x2,F_LONG,F_LONG), "cmpl"}, +{0, ADD_F, mk_op2(0x8,F_FLOAT,F_FLOAT), "divf"}, +{0, ADD_F, mk_op2(0x8,F_LONG,F_LONG), "divl"}, +{0, ADD_F, mk_op2(0xC,F_FLOAT,F_FLOAT), "mulf"}, +{0, ADD_F, mk_op2(0xC,F_LONG,F_LONG), "mull"}, +{0, ADD_F, mk_op2(0x4,F_FLOAT,F_FLOAT), "subf"}, +{0, ADD_F, mk_op2(0x4,F_LONG,F_LONG), "subl"}, +{0, ADD_F, mk_op2(0x5,F_FLOAT,F_FLOAT), "negf"}, +{0, ADD_F, mk_op2(0x5,F_LONG,F_LONG), "negl"}, +{0, ADD_F, mk_op2(0x1,F_FLOAT,F_FLOAT), "movf"}, +{0, ADD_F, mk_op2(0x1,F_LONG,F_LONG), "movl"}, +{0, MOVIF, mk_op2(0x0,I_BYTE,F_FLOAT), "movbf"}, +{0, MOVIF, mk_op2(0x0,I_WORD,F_FLOAT), "movwf"}, +{0, MOVIF, mk_op2(0x0,I_DOUBLE,F_FLOAT), "movdf"}, +{0, MOVIF, mk_op2(0x0,I_BYTE,F_LONG), "movbl"}, +{0, MOVIF, mk_op2(0x0,I_WORD,F_LONG), "movwl"}, +{0, MOVIF, mk_op2(0x0,I_DOUBLE,F_LONG), "movdl"}, +{0, MOVFL, mk_op2(0x3,F_FLOAT,F_LONG), "movfl"}, +{0, MOVFL, mk_op2(0x2,F_LONG,F_FLOAT), "movlf"}, +{0, TRUNC, mk_op2(0x7,F_FLOAT,I_BYTE), "floorfb"}, +{0, TRUNC, mk_op2(0x7,F_FLOAT,I_WORD), "floorfw"}, +{0, TRUNC, mk_op2(0x7,F_FLOAT,I_DOUBLE), "floorfd"}, +{0, TRUNC, mk_op2(0x7,F_LONG,I_BYTE), "floorlb"}, +{0, TRUNC, mk_op2(0x7,F_LONG,I_WORD), "floorlw"}, +{0, TRUNC, mk_op2(0x7,F_LONG,I_DOUBLE), "floorld"}, +{0, TRUNC, mk_op2(0x4,F_FLOAT,I_BYTE), "roundfb"}, +{0, TRUNC, mk_op2(0x4,F_FLOAT,I_WORD), "roundfw"}, +{0, TRUNC, mk_op2(0x4,F_FLOAT,I_DOUBLE), "roundfd"}, +{0, TRUNC, mk_op2(0x4,F_LONG,I_BYTE), "roundlb"}, +{0, TRUNC, mk_op2(0x4,F_LONG,I_WORD), "roundlw"}, +{0, TRUNC, mk_op2(0x4,F_LONG,I_DOUBLE), "roundld"}, +{0, TRUNC, mk_op2(0x5,F_FLOAT,I_BYTE), "truncfb"}, +{0, TRUNC, mk_op2(0x5,F_FLOAT,I_WORD), "truncfw"}, +{0, TRUNC, mk_op2(0x5,F_FLOAT,I_DOUBLE), "truncfd"}, +{0, TRUNC, mk_op2(0x5,F_LONG,I_BYTE), "trunclb"}, +{0, TRUNC, mk_op2(0x5,F_LONG,I_WORD), "trunclw"}, +{0, TRUNC, mk_op2(0x5,F_LONG,I_DOUBLE), "truncld"}, +{0, LFSR, mk_op(0x1), "lfsr"}, +{0, LFSR, mk_op(0x6), "sfsr"}, /* Slave processor instructions */ -0, LCR, mk_op1(0x2,I_DOUBLE), "lcr", /* Sure ? */ -0, LCR, mk_op1(0x3,I_DOUBLE), "scr", /* Sure ? */ -0, CATST, mk_op1(0x0,I_DOUBLE), "catst0",/* Sure ? */ -0, CATST, mk_op1(0x1,I_DOUBLE), "catst1",/* Sure ? */ -0, LCSR, mk_op1(0x1,S_DOUBLE), "lcsr", /* Sure ? */ -0, LCSR, mk_op1(0x6,S_DOUBLE), "scsr", /* Sure ? */ -0, CCVSI, mk_op2(0x7,S_DOUBLE,I_BYTE), "ccv0db", -0, CCVSI, mk_op2(0x7,S_DOUBLE,I_WORD), "ccv0dw", -0, CCVSI, mk_op2(0x7,S_DOUBLE,I_DOUBLE), "ccv0dd", -0, CCVSI, mk_op2(0x7,S_QUAD,I_BYTE), "ccv0qb", -0, CCVSI, mk_op2(0x7,S_QUAD,I_WORD), "ccv0qw", -0, CCVSI, mk_op2(0x7,S_QUAD,I_DOUBLE), "ccv0qd", -0, CCVSI, mk_op2(0x5,S_DOUBLE,I_BYTE), "ccv1db", -0, CCVSI, mk_op2(0x5,S_DOUBLE,I_WORD), "ccv1dw", -0, CCVSI, mk_op2(0x5,S_DOUBLE,I_DOUBLE), "ccv1dd", -0, CCVSI, mk_op2(0x5,S_QUAD,I_BYTE), "ccv1qb", -0, CCVSI, mk_op2(0x5,S_QUAD,I_WORD), "ccv1qw", -0, CCVSI, mk_op2(0x5,S_QUAD,I_DOUBLE), "ccv1qd", -0, CCVSI, mk_op2(0x4,S_DOUBLE,I_BYTE), "ccv2db", -0, CCVSI, mk_op2(0x4,S_DOUBLE,I_WORD), "ccv2dw", -0, CCVSI, mk_op2(0x4,S_DOUBLE,I_DOUBLE), "ccv2dd", -0, CCVSI, mk_op2(0x4,S_QUAD,I_BYTE), "ccv2qb", -0, CCVSI, mk_op2(0x4,S_QUAD,I_WORD), "ccv2qw", -0, CCVSI, mk_op2(0x4,S_QUAD,I_DOUBLE), "ccv2qd", -0, CCVIS, mk_op2(0x0,I_BYTE,S_DOUBLE), "ccv3bd", -0, CCVIS, mk_op2(0x0,I_WORD,S_DOUBLE), "ccv3wd", -0, CCVIS, mk_op2(0x0,I_DOUBLE,S_DOUBLE), "ccv3dd", -0, CCVIS, mk_op2(0x0,I_BYTE,S_QUAD), "ccv3bq", -0, CCVIS, mk_op2(0x0,I_WORD,S_QUAD), "ccv3wq", -0, CCVIS, mk_op2(0x0,I_DOUBLE,S_QUAD), "ccv3dq", -0, CCVSS, mk_op2(0x3,S_DOUBLE,S_QUAD), "ccv4dq", -0, CCVSS, mk_op2(0x2,S_QUAD,S_DOUBLE), "ccv5qd", -0, CMOV, mk_op2(0x0,S_DOUBLE,S_DOUBLE), "ccal0d", -0, CMOV, mk_op2(0x0,S_QUAD,S_QUAD), "ccal0q", -0, CMOV, mk_op2(0x4,S_DOUBLE,S_DOUBLE), "ccal1d", -0, CMOV, mk_op2(0x4,S_QUAD,S_QUAD), "ccal1q", -0, CMOV, mk_op2(0xC,S_DOUBLE,S_DOUBLE), "ccal2d", -0, CMOV, mk_op2(0xC,S_QUAD,S_QUAD), "ccal2q", -0, CMOV, mk_op2(0x8,S_DOUBLE,S_DOUBLE), "ccal3d", -0, CMOV, mk_op2(0x8,S_QUAD,S_QUAD), "ccal3q", -0, CMOV, mk_op2(0x2,S_DOUBLE,S_DOUBLE), "ccmpd", -0, CMOV, mk_op2(0x2,S_QUAD,S_QUAD), "ccmpq", -0, CMOV, mk_op2(0x1,S_DOUBLE,S_DOUBLE), "cmov0d", -0, CMOV, mk_op2(0x1,S_QUAD,S_QUAD), "cmov0q", -0, CMOV, mk_op2(0xD,S_DOUBLE,S_DOUBLE), "cmov1d", -0, CMOV, mk_op2(0xD,S_QUAD,S_QUAD), "cmov1q", -0, CMOV, mk_op2(0x5,S_DOUBLE,S_DOUBLE), "cmov2d", -0, CMOV, mk_op2(0x5,S_QUAD,S_QUAD), "cmov2q", +{0, LCR, mk_op1(0x2,I_DOUBLE), "lcr"}, /* Sure ? */ +{0, LCR, mk_op1(0x3,I_DOUBLE), "scr"}, /* Sure ? */ +{0, CATST, mk_op1(0x0,I_DOUBLE), "catst0"},/* Sure ? */ +{0, CATST, mk_op1(0x1,I_DOUBLE), "catst1"},/* Sure ? */ +{0, LCSR, mk_op1(0x1,S_DOUBLE), "lcsr"}, /* Sure ? */ +{0, LCSR, mk_op1(0x6,S_DOUBLE), "scsr"}, /* Sure ? */ +{0, CCVSI, mk_op2(0x7,S_DOUBLE,I_BYTE), "ccv0db"}, +{0, CCVSI, mk_op2(0x7,S_DOUBLE,I_WORD), "ccv0dw"}, +{0, CCVSI, mk_op2(0x7,S_DOUBLE,I_DOUBLE), "ccv0dd"}, +{0, CCVSI, mk_op2(0x7,S_QUAD,I_BYTE), "ccv0qb"}, +{0, CCVSI, mk_op2(0x7,S_QUAD,I_WORD), "ccv0qw"}, +{0, CCVSI, mk_op2(0x7,S_QUAD,I_DOUBLE), "ccv0qd"}, +{0, CCVSI, mk_op2(0x5,S_DOUBLE,I_BYTE), "ccv1db"}, +{0, CCVSI, mk_op2(0x5,S_DOUBLE,I_WORD), "ccv1dw"}, +{0, CCVSI, mk_op2(0x5,S_DOUBLE,I_DOUBLE), "ccv1dd"}, +{0, CCVSI, mk_op2(0x5,S_QUAD,I_BYTE), "ccv1qb"}, +{0, CCVSI, mk_op2(0x5,S_QUAD,I_WORD), "ccv1qw"}, +{0, CCVSI, mk_op2(0x5,S_QUAD,I_DOUBLE), "ccv1qd"}, +{0, CCVSI, mk_op2(0x4,S_DOUBLE,I_BYTE), "ccv2db"}, +{0, CCVSI, mk_op2(0x4,S_DOUBLE,I_WORD), "ccv2dw"}, +{0, CCVSI, mk_op2(0x4,S_DOUBLE,I_DOUBLE), "ccv2dd"}, +{0, CCVSI, mk_op2(0x4,S_QUAD,I_BYTE), "ccv2qb"}, +{0, CCVSI, mk_op2(0x4,S_QUAD,I_WORD), "ccv2qw"}, +{0, CCVSI, mk_op2(0x4,S_QUAD,I_DOUBLE), "ccv2qd"}, +{0, CCVIS, mk_op2(0x0,I_BYTE,S_DOUBLE), "ccv3bd"}, +{0, CCVIS, mk_op2(0x0,I_WORD,S_DOUBLE), "ccv3wd"}, +{0, CCVIS, mk_op2(0x0,I_DOUBLE,S_DOUBLE), "ccv3dd"}, +{0, CCVIS, mk_op2(0x0,I_BYTE,S_QUAD), "ccv3bq"}, +{0, CCVIS, mk_op2(0x0,I_WORD,S_QUAD), "ccv3wq"}, +{0, CCVIS, mk_op2(0x0,I_DOUBLE,S_QUAD), "ccv3dq"}, +{0, CCVSS, mk_op2(0x3,S_DOUBLE,S_QUAD), "ccv4dq"}, +{0, CCVSS, mk_op2(0x2,S_QUAD,S_DOUBLE), "ccv5qd"}, +{0, CMOV, mk_op2(0x0,S_DOUBLE,S_DOUBLE), "ccal0d"}, +{0, CMOV, mk_op2(0x0,S_QUAD,S_QUAD), "ccal0q"}, +{0, CMOV, mk_op2(0x4,S_DOUBLE,S_DOUBLE), "ccal1d"}, +{0, CMOV, mk_op2(0x4,S_QUAD,S_QUAD), "ccal1q"}, +{0, CMOV, mk_op2(0xC,S_DOUBLE,S_DOUBLE), "ccal2d"}, +{0, CMOV, mk_op2(0xC,S_QUAD,S_QUAD), "ccal2q"}, +{0, CMOV, mk_op2(0x8,S_DOUBLE,S_DOUBLE), "ccal3d"}, +{0, CMOV, mk_op2(0x8,S_QUAD,S_QUAD), "ccal3q"}, +{0, CMOV, mk_op2(0x2,S_DOUBLE,S_DOUBLE), "ccmpd"}, +{0, CMOV, mk_op2(0x2,S_QUAD,S_QUAD), "ccmpq"}, +{0, CMOV, mk_op2(0x1,S_DOUBLE,S_DOUBLE), "cmov0d"}, +{0, CMOV, mk_op2(0x1,S_QUAD,S_QUAD), "cmov0q"}, +{0, CMOV, mk_op2(0xD,S_DOUBLE,S_DOUBLE), "cmov1d"}, +{0, CMOV, mk_op2(0xD,S_QUAD,S_QUAD), "cmov1q"}, +{0, CMOV, mk_op2(0x5,S_DOUBLE,S_DOUBLE), "cmov2d"}, +{0, CMOV, mk_op2(0x5,S_QUAD,S_QUAD), "cmov2q"}, diff --git a/mach/pdp/as/mach3.c b/mach/pdp/as/mach3.c index 10abfa399..42c5cdf26 100644 --- a/mach/pdp/as/mach3.c +++ b/mach/pdp/as/mach3.c @@ -7,149 +7,149 @@ /*, * PDP 11 keywords, */ -0, REG, 00, "r0", -0, REG, 01, "r1", -0, REG, 02, "r2", -0, REG, 03, "r3", -0, REG, 04, "r4", -0, REG, 05, "r5", -0, REG, 06, "r6", -0, REG, 06, "sp", -0, REG, 07, "r7", -0, REG, 07, "pc", -0, FREG, 00, "fr0", -0, FREG, 01, "fr1", -0, FREG, 02, "fr2", -0, FREG, 03, "fr3", -0, FRSP, 04, "fr4", -0, FRSP, 05, "fr5", -0, OP_SO, 05000, "clr", -0, OP_SO, 0105000, "clrb", -0, OP_SO, 05100, "com", -0, OP_SO, 0105100, "comb", -0, OP_SO, 005200, "inc", -0, OP_SO, 0105200, "incb", -0, OP_SO, 005300, "dec", -0, OP_SO, 0105300, "decb", -0, OP_SO, 005400, "neg", -0, OP_SO, 0105400, "negb", -0, OP_SO, 005700, "tst", -0, OP_SO, 0105700, "tstb", -0, OP_SO, 006200, "asr", -0, OP_SO, 0106200, "asrb", -0, OP_SO, 006300, "asl", -0, OP_SO, 0106300, "aslb", -0, OP_SO, 006000, "ror", -0, OP_SO, 0106000, "rorb", -0, OP_SO, 006100, "rol", -0, OP_SO, 0106100, "rolb", -0, OP_SO, 000300, "swab", -0, OP_SO, 005500, "adc", -0, OP_SO, 0105500, "adcb", -0, OP_SO, 005600, "sbc", -0, OP_SO, 0105600, "sbcb", -0, OP_SO, 006700, "sxt", -0, OP_DO, 010000, "mov", -0, OP_DO, 0110000, "movb", -0, OP_DO, 020000, "cmp", -0, OP_DO, 0120000, "cmpb", -0, OP_DO, 060000, "add", -0, OP_DO, 0160000, "sub", -0, OP_DO, 030000, "bit", -0, OP_DO, 0130000, "bitb", -0, OP_DO, 040000, "bic", -0, OP_DO, 0140000, "bicb", -0, OP_DO, 050000, "bis", -0, OP_DO, 0150000, "bisb", -0, OP_R_SO, 074000, "xor", -0, JMP, 0100, "jmp", -0, BR, 0400, "br", -0, BR, 01000, "bne", -0, BR, 01400, "beq", -0, BR, 0100000, "bpl", -0, BR, 0100400, "bmi", -0, BR, 0102000, "bvc", -0, BR, 0102400, "bvs", -0, BR, 0103000, "bcc", -0, BR, 0103400, "bcs", -0, BR, 002000, "bge", -0, BR, 002400, "blt", -0, BR, 003000, "bgt", -0, BR, 003400, "ble", -0, BR, 0101000, "bhi", -0, BR, 0101400, "blos", -0, BR, 0103000, "bhis", -0, BR, 0103400, "blo", -0, EJMP, 0400, "jbr", -0, EJMP, 01000, "jne", -0, EJMP, 01400, "jeq", -0, EJMP, 0100000, "jpl", -0, EJMP, 0100400, "jmi", -0, EJMP, 0102000, "jvc", -0, EJMP, 0102400, "jvs", -0, EJMP, 0103000, "jcc", -0, EJMP, 0103400, "jcs", -0, EJMP, 02000, "jge", -0, EJMP, 02400, "jlt", -0, EJMP, 03000, "jgt", -0, EJMP, 03400, "jle", -0, EJMP, 0101000, "jhi", -0, EJMP, 0101400, "jlos", -0, EJMP, 0103000, "jhis", -0, EJMP, 0103400, "jlo", -0, JSR, 004000, "jsr", -0, RTS, 000200, "rts", -0, MARK, 006400, "mark", -0, SOB, 077000, "sob", -0, SPL, 0230, "spl", -0, TRAP, 0104000, "emt", -0, TRAP, 0104400, "trap", -0, TRAP, 0104400, "sys", -0, OP_NO, 03, "bpt", -0, OP_NO, 04, "iot", -0, OP_NO, 02, "rti", -0, OP_NO, 06, "rtt", -0, OP_NO, 0, "halt", -0, OP_NO, 01, "wait", -0, OP_NO, 05, "reset", -0, OP_NO, 0170000, "cfcc", -0, OP_NO, 0170002, "seti", -0, OP_NO, 0170012, "setl", -0, OP_NO, 0170001, "setf", -0, OP_NO, 0170011, "setd", -0, CLEARCC, 0241, "clc", -0, CLEARCC, 0242, "clv", -0, CLEARCC, 0244, "clz", -0, CLEARCC, 0250, "cln", -0, SETCC, 0261, "sec", -0, SETCC, 0262, "sev", -0, SETCC, 0264, "sez", -0, SETCC, 0270, "sen", -0, OP_SO_R, 070000, "mul", -0, OP_SO_R, 071000, "div", -0, OP_SO_R, 072000, "ash", -0, OP_SO_R, 073000, "ashc", -0, MFP, 006500, "mfpi", -0, MFP, 0106500, "mfpd", -0, MFP, 006600, "mtpi", -0, MFP, 0106600, "mtpd", -0, FOP_FSO_FR, 0172000, "addf", -0, FOP_FSO_FR, 0173000, "subf", -0, FOP_FSO_FR, 0171000, "mulf", -0, FOP_FSO_FR, 0174400, "divf", -0, FOP_FSO_FR, 0173400, "cmpf", -0, FOP_FSO_FR, 0171400, "modf", -0, FOP_FSO, 0170400, "clrf", -0, FOP_FSO, 0170700, "negf", -0, FOP_FSO, 0170600, "absf", -0, FOP_FSO, 0170500, "tstf", -0, FOP_SO, 0170100, "ldfps", -0, FOP_SO, 0170200, "stfps", -0, FOP_SO, 0170300, "stst", -0, MOVF, 0, "movf", -0, FOP_SO_FR, 0177000, "movif", -0, FOP_SO_FR, 0176400, "movie", -0, FOP_FR_SO, 0175400, "movfi", -0, FOP_FR_SO, 0175000, "movei", -0, FOP_FSO_FR, 0177400, "movof", -0, FOP_FR_FSO, 0176000, "movfo", +{0, REG, 00, "r0"}, +{0, REG, 01, "r1"}, +{0, REG, 02, "r2"}, +{0, REG, 03, "r3"}, +{0, REG, 04, "r4"}, +{0, REG, 05, "r5"}, +{0, REG, 06, "r6"}, +{0, REG, 06, "sp"}, +{0, REG, 07, "r7"}, +{0, REG, 07, "pc"}, +{0, FREG, 00, "fr0"}, +{0, FREG, 01, "fr1"}, +{0, FREG, 02, "fr2"}, +{0, FREG, 03, "fr3"}, +{0, FRSP, 04, "fr4"}, +{0, FRSP, 05, "fr5"}, +{0, OP_SO, 05000, "clr"}, +{0, OP_SO, 0105000, "clrb"}, +{0, OP_SO, 05100, "com"}, +{0, OP_SO, 0105100, "comb"}, +{0, OP_SO, 005200, "inc"}, +{0, OP_SO, 0105200, "incb"}, +{0, OP_SO, 005300, "dec"}, +{0, OP_SO, 0105300, "decb"}, +{0, OP_SO, 005400, "neg"}, +{0, OP_SO, 0105400, "negb"}, +{0, OP_SO, 005700, "tst"}, +{0, OP_SO, 0105700, "tstb"}, +{0, OP_SO, 006200, "asr"}, +{0, OP_SO, 0106200, "asrb"}, +{0, OP_SO, 006300, "asl"}, +{0, OP_SO, 0106300, "aslb"}, +{0, OP_SO, 006000, "ror"}, +{0, OP_SO, 0106000, "rorb"}, +{0, OP_SO, 006100, "rol"}, +{0, OP_SO, 0106100, "rolb"}, +{0, OP_SO, 000300, "swab"}, +{0, OP_SO, 005500, "adc"}, +{0, OP_SO, 0105500, "adcb"}, +{0, OP_SO, 005600, "sbc"}, +{0, OP_SO, 0105600, "sbcb"}, +{0, OP_SO, 006700, "sxt"}, +{0, OP_DO, 010000, "mov"}, +{0, OP_DO, 0110000, "movb"}, +{0, OP_DO, 020000, "cmp"}, +{0, OP_DO, 0120000, "cmpb"}, +{0, OP_DO, 060000, "add"}, +{0, OP_DO, 0160000, "sub"}, +{0, OP_DO, 030000, "bit"}, +{0, OP_DO, 0130000, "bitb"}, +{0, OP_DO, 040000, "bic"}, +{0, OP_DO, 0140000, "bicb"}, +{0, OP_DO, 050000, "bis"}, +{0, OP_DO, 0150000, "bisb"}, +{0, OP_R_SO, 074000, "xor"}, +{0, JMP, 0100, "jmp"}, +{0, BR, 0400, "br"}, +{0, BR, 01000, "bne"}, +{0, BR, 01400, "beq"}, +{0, BR, 0100000, "bpl"}, +{0, BR, 0100400, "bmi"}, +{0, BR, 0102000, "bvc"}, +{0, BR, 0102400, "bvs"}, +{0, BR, 0103000, "bcc"}, +{0, BR, 0103400, "bcs"}, +{0, BR, 002000, "bge"}, +{0, BR, 002400, "blt"}, +{0, BR, 003000, "bgt"}, +{0, BR, 003400, "ble"}, +{0, BR, 0101000, "bhi"}, +{0, BR, 0101400, "blos"}, +{0, BR, 0103000, "bhis"}, +{0, BR, 0103400, "blo"}, +{0, EJMP, 0400, "jbr"}, +{0, EJMP, 01000, "jne"}, +{0, EJMP, 01400, "jeq"}, +{0, EJMP, 0100000, "jpl"}, +{0, EJMP, 0100400, "jmi"}, +{0, EJMP, 0102000, "jvc"}, +{0, EJMP, 0102400, "jvs"}, +{0, EJMP, 0103000, "jcc"}, +{0, EJMP, 0103400, "jcs"}, +{0, EJMP, 02000, "jge"}, +{0, EJMP, 02400, "jlt"}, +{0, EJMP, 03000, "jgt"}, +{0, EJMP, 03400, "jle"}, +{0, EJMP, 0101000, "jhi"}, +{0, EJMP, 0101400, "jlos"}, +{0, EJMP, 0103000, "jhis"}, +{0, EJMP, 0103400, "jlo"}, +{0, JSR, 004000, "jsr"}, +{0, RTS, 000200, "rts"}, +{0, MARK, 006400, "mark"}, +{0, SOB, 077000, "sob"}, +{0, SPL, 0230, "spl"}, +{0, TRAP, 0104000, "emt"}, +{0, TRAP, 0104400, "trap"}, +{0, TRAP, 0104400, "sys"}, +{0, OP_NO, 03, "bpt"}, +{0, OP_NO, 04, "iot"}, +{0, OP_NO, 02, "rti"}, +{0, OP_NO, 06, "rtt"}, +{0, OP_NO, 0, "halt"}, +{0, OP_NO, 01, "wait"}, +{0, OP_NO, 05, "reset"}, +{0, OP_NO, 0170000, "cfcc"}, +{0, OP_NO, 0170002, "seti"}, +{0, OP_NO, 0170012, "setl"}, +{0, OP_NO, 0170001, "setf"}, +{0, OP_NO, 0170011, "setd"}, +{0, CLEARCC, 0241, "clc"}, +{0, CLEARCC, 0242, "clv"}, +{0, CLEARCC, 0244, "clz"}, +{0, CLEARCC, 0250, "cln"}, +{0, SETCC, 0261, "sec"}, +{0, SETCC, 0262, "sev"}, +{0, SETCC, 0264, "sez"}, +{0, SETCC, 0270, "sen"}, +{0, OP_SO_R, 070000, "mul"}, +{0, OP_SO_R, 071000, "div"}, +{0, OP_SO_R, 072000, "ash"}, +{0, OP_SO_R, 073000, "ashc"}, +{0, MFP, 006500, "mfpi"}, +{0, MFP, 0106500, "mfpd"}, +{0, MFP, 006600, "mtpi"}, +{0, MFP, 0106600, "mtpd"}, +{0, FOP_FSO_FR, 0172000, "addf"}, +{0, FOP_FSO_FR, 0173000, "subf"}, +{0, FOP_FSO_FR, 0171000, "mulf"}, +{0, FOP_FSO_FR, 0174400, "divf"}, +{0, FOP_FSO_FR, 0173400, "cmpf"}, +{0, FOP_FSO_FR, 0171400, "modf"}, +{0, FOP_FSO, 0170400, "clrf"}, +{0, FOP_FSO, 0170700, "negf"}, +{0, FOP_FSO, 0170600, "absf"}, +{0, FOP_FSO, 0170500, "tstf"}, +{0, FOP_SO, 0170100, "ldfps"}, +{0, FOP_SO, 0170200, "stfps"}, +{0, FOP_SO, 0170300, "stst"}, +{0, MOVF, 0, "movf"}, +{0, FOP_SO_FR, 0177000, "movif"}, +{0, FOP_SO_FR, 0176400, "movie"}, +{0, FOP_FR_SO, 0175400, "movfi"}, +{0, FOP_FR_SO, 0175000, "movei"}, +{0, FOP_FSO_FR, 0177400, "movof"}, +{0, FOP_FR_FSO, 0176000, "movfo"}, diff --git a/mach/powerpc/as/mach3.c b/mach/powerpc/as/mach3.c index 99507087d..35124e09a 100644 --- a/mach/powerpc/as/mach3.c +++ b/mach/powerpc/as/mach3.c @@ -5,103 +5,103 @@ /* Integer registers */ -0, GPR, 0, "r0", -0, GPR, 1, "r1", -0, GPR, 1, "sp", -0, GPR, 2, "r2", -0, GPR, 2, "fp", -0, GPR, 3, "r3", -0, GPR, 4, "r4", -0, GPR, 5, "r5", -0, GPR, 6, "r6", -0, GPR, 7, "r7", -0, GPR, 8, "r8", -0, GPR, 9, "r9", -0, GPR, 10, "r10", -0, GPR, 11, "r11", -0, GPR, 12, "r12", -0, GPR, 13, "r13", -0, GPR, 14, "r14", -0, GPR, 15, "r15", -0, GPR, 16, "r16", -0, GPR, 17, "r17", -0, GPR, 18, "r18", -0, GPR, 19, "r19", -0, GPR, 20, "r20", -0, GPR, 21, "r21", -0, GPR, 22, "r22", -0, GPR, 23, "r23", -0, GPR, 24, "r24", -0, GPR, 25, "r25", -0, GPR, 26, "r26", -0, GPR, 27, "r27", -0, GPR, 28, "r28", -0, GPR, 29, "r29", -0, GPR, 30, "r30", -0, GPR, 31, "r31", +{0, GPR, 0, "r0"}, +{0, GPR, 1, "r1"}, +{0, GPR, 1, "sp"}, +{0, GPR, 2, "r2"}, +{0, GPR, 2, "fp"}, +{0, GPR, 3, "r3"}, +{0, GPR, 4, "r4"}, +{0, GPR, 5, "r5"}, +{0, GPR, 6, "r6"}, +{0, GPR, 7, "r7"}, +{0, GPR, 8, "r8"}, +{0, GPR, 9, "r9"}, +{0, GPR, 10, "r10"}, +{0, GPR, 11, "r11"}, +{0, GPR, 12, "r12"}, +{0, GPR, 13, "r13"}, +{0, GPR, 14, "r14"}, +{0, GPR, 15, "r15"}, +{0, GPR, 16, "r16"}, +{0, GPR, 17, "r17"}, +{0, GPR, 18, "r18"}, +{0, GPR, 19, "r19"}, +{0, GPR, 20, "r20"}, +{0, GPR, 21, "r21"}, +{0, GPR, 22, "r22"}, +{0, GPR, 23, "r23"}, +{0, GPR, 24, "r24"}, +{0, GPR, 25, "r25"}, +{0, GPR, 26, "r26"}, +{0, GPR, 27, "r27"}, +{0, GPR, 28, "r28"}, +{0, GPR, 29, "r29"}, +{0, GPR, 30, "r30"}, +{0, GPR, 31, "r31"}, /* Floating-point registers */ -0, FPR, 0, "f0", -0, FPR, 1, "f1", -0, FPR, 2, "f2", -0, FPR, 3, "f3", -0, FPR, 4, "f4", -0, FPR, 5, "f5", -0, FPR, 6, "f6", -0, FPR, 7, "f7", -0, FPR, 8, "f8", -0, FPR, 9, "f9", -0, FPR, 10, "f10", -0, FPR, 11, "f11", -0, FPR, 12, "f12", -0, FPR, 13, "f13", -0, FPR, 14, "f14", -0, FPR, 15, "f15", -0, FPR, 16, "f16", -0, FPR, 17, "f17", -0, FPR, 18, "f18", -0, FPR, 19, "f19", -0, FPR, 20, "f20", -0, FPR, 21, "f21", -0, FPR, 22, "f22", -0, FPR, 23, "f23", -0, FPR, 24, "f24", -0, FPR, 25, "f25", -0, FPR, 26, "f26", -0, FPR, 27, "f27", -0, FPR, 28, "f28", -0, FPR, 29, "f29", -0, FPR, 30, "f30", -0, FPR, 31, "f31", +{0, FPR, 0, "f0"}, +{0, FPR, 1, "f1"}, +{0, FPR, 2, "f2"}, +{0, FPR, 3, "f3"}, +{0, FPR, 4, "f4"}, +{0, FPR, 5, "f5"}, +{0, FPR, 6, "f6"}, +{0, FPR, 7, "f7"}, +{0, FPR, 8, "f8"}, +{0, FPR, 9, "f9"}, +{0, FPR, 10, "f10"}, +{0, FPR, 11, "f11"}, +{0, FPR, 12, "f12"}, +{0, FPR, 13, "f13"}, +{0, FPR, 14, "f14"}, +{0, FPR, 15, "f15"}, +{0, FPR, 16, "f16"}, +{0, FPR, 17, "f17"}, +{0, FPR, 18, "f18"}, +{0, FPR, 19, "f19"}, +{0, FPR, 20, "f20"}, +{0, FPR, 21, "f21"}, +{0, FPR, 22, "f22"}, +{0, FPR, 23, "f23"}, +{0, FPR, 24, "f24"}, +{0, FPR, 25, "f25"}, +{0, FPR, 26, "f26"}, +{0, FPR, 27, "f27"}, +{0, FPR, 28, "f28"}, +{0, FPR, 29, "f29"}, +{0, FPR, 30, "f30"}, +{0, FPR, 31, "f31"}, /* Special registers */ -0, SPR, 32, "xer", -0, SPR, 256, "lr", -0, SPR, 288, "ctr", +{0, SPR, 32, "xer"}, +{0, SPR, 256, "lr"}, +{0, SPR, 288, "ctr"}, /* Condition registers */ -0, CR, 0, "cr0", -0, CR, 1, "cr1", -0, CR, 2, "cr2", -0, CR, 3, "cr3", -0, CR, 4, "cr4", -0, CR, 5, "cr5", -0, CR, 6, "cr6", -0, CR, 7, "cr7", +{0, CR, 0, "cr0"}, +{0, CR, 1, "cr1"}, +{0, CR, 2, "cr2"}, +{0, CR, 3, "cr3"}, +{0, CR, 4, "cr4"}, +{0, CR, 5, "cr5"}, +{0, CR, 6, "cr6"}, +{0, CR, 7, "cr7"}, /* Condition code flag */ -0, C, 0, ".", +{0, C, 0, "."}, /* Special instructions */ -0, OP_LI32, 0, "li32", -0, OP_HI, 0, "hi16", -0, OP_HA, 0, "ha16", -0, OP_LO, 0, "lo16", +{0, OP_LI32, 0, "li32"}, +{0, OP_HI, 0, "hi16"}, +{0, OP_HA, 0, "ha16"}, +{0, OP_LO, 0, "lo16"}, /* The next page numbers are from PowerPC User Instruction Set * Architecture, Book I, Version 2.01. @@ -109,583 +109,583 @@ /* Branch processor instructions (page 20) */ -0, OP_LIL, 18<<26 | 0<<1 | 0<<0, "b", -0, OP_LIA, 18<<26 | 1<<1 | 0<<0, "ba", -0, OP_LIL, 18<<26 | 0<<1 | 1<<0, "bl", -0, OP_LIA, 18<<26 | 1<<1 | 1<<0, "bla", -0, OP_BO_BI_BDL, 16<<26 | 0<<1 | 0<<0, "bc", -0, OP_BO_BI_BDA, 16<<26 | 1<<1 | 0<<0, "bca", -0, OP_BO_BI_BDL, 16<<26 | 0<<1 | 1<<0, "bcl", -0, OP_BO_BI_BDA, 16<<26 | 1<<1 | 1<<0, "bcla", -0, OP_BO_BI_BH, 19<<26 | 16<<1 | 0<<0, "bclr", -0, OP_BO_BI_BH, 19<<26 | 16<<1 | 1<<0, "bclrl", -0, OP_BO_BI_BH, 19<<26 | 528<<1 | 0<<0, "bcctr", -0, OP_BO_BI_BH, 19<<26 | 528<<1 | 1<<0, "bcctrl", -0, OP_LEV, 17<<26 | 1<<1, "sc", -0, OP_BT_BA_BB, 19<<26 | 257<<1, "crand", -0, OP_BT_BA_BB, 19<<26 | 449<<1, "cror", -0, OP_BT_BA_BB, 19<<26 | 193<<1, "crxor", -0, OP_BT_BA_BB, 19<<26 | 225<<1, "crnand", -0, OP_BT_BA_BB, 19<<26 | 33<<1, "crnor", -0, OP_BT_BA_BB, 19<<26 | 289<<1, "creqv", -0, OP_BT_BA_BB, 19<<26 | 129<<1, "crandc", -0, OP_BT_BA_BB, 19<<26 | 417<<1, "crorc", -0, OP_BF_BFA, 19<<26 | 0<<1, "mcrf", +{0, OP_LIL, 18<<26 | 0<<1 | 0<<0, "b"}, +{0, OP_LIA, 18<<26 | 1<<1 | 0<<0, "ba"}, +{0, OP_LIL, 18<<26 | 0<<1 | 1<<0, "bl"}, +{0, OP_LIA, 18<<26 | 1<<1 | 1<<0, "bla"}, +{0, OP_BO_BI_BDL, 16<<26 | 0<<1 | 0<<0, "bc"}, +{0, OP_BO_BI_BDA, 16<<26 | 1<<1 | 0<<0, "bca"}, +{0, OP_BO_BI_BDL, 16<<26 | 0<<1 | 1<<0, "bcl"}, +{0, OP_BO_BI_BDA, 16<<26 | 1<<1 | 1<<0, "bcla"}, +{0, OP_BO_BI_BH, 19<<26 | 16<<1 | 0<<0, "bclr"}, +{0, OP_BO_BI_BH, 19<<26 | 16<<1 | 1<<0, "bclrl"}, +{0, OP_BO_BI_BH, 19<<26 | 528<<1 | 0<<0, "bcctr"}, +{0, OP_BO_BI_BH, 19<<26 | 528<<1 | 1<<0, "bcctrl"}, +{0, OP_LEV, 17<<26 | 1<<1, "sc"}, +{0, OP_BT_BA_BB, 19<<26 | 257<<1, "crand"}, +{0, OP_BT_BA_BB, 19<<26 | 449<<1, "cror"}, +{0, OP_BT_BA_BB, 19<<26 | 193<<1, "crxor"}, +{0, OP_BT_BA_BB, 19<<26 | 225<<1, "crnand"}, +{0, OP_BT_BA_BB, 19<<26 | 33<<1, "crnor"}, +{0, OP_BT_BA_BB, 19<<26 | 289<<1, "creqv"}, +{0, OP_BT_BA_BB, 19<<26 | 129<<1, "crandc"}, +{0, OP_BT_BA_BB, 19<<26 | 417<<1, "crorc"}, +{0, OP_BF_BFA, 19<<26 | 0<<1, "mcrf"}, /* extended mnemonics for bc, bcctr, bclr (page 144) */ -0, OP_BH, 19<<26 | 20<<21 | 528<<1 | 0<<0, "bctr", -0, OP_BH, 19<<26 | 20<<21 | 528<<1 | 1<<0, "bctrl", -0, OP_BDL, 16<<26 | 16<<21 | 0<<1 | 0<<0, "bdnz", -0, OP_BDA, 16<<26 | 16<<21 | 1<<1 | 0<<0, "bdnza", -0, OP_BH, 19<<26 | 16<<21 | 16<<1 | 0<<0, "bdnzlr", -0, OP_BDL, 16<<26 | 16<<21 | 0<<1 | 1<<0, "bdnzl", -0, OP_BDA, 16<<26 | 16<<21 | 1<<1 | 1<<0, "bdnzla", -0, OP_BH, 19<<26 | 16<<21 | 16<<1 | 1<<0, "bdnzlrl", -0, OP_BI_BDL, 16<<26 | 0<<21 | 0<<1 | 0<<0, "bdnzf", -0, OP_BI_BDA, 16<<26 | 0<<21 | 1<<1 | 0<<0, "bdnzfa", -0, OP_BI_BH, 19<<26 | 0<<21 | 16<<1 | 0<<0, "bdnzflr", -0, OP_BI_BDL, 16<<26 | 0<<21 | 0<<1 | 1<<0, "bdnzfl", -0, OP_BI_BDA, 16<<26 | 0<<21 | 1<<1 | 1<<0, "bdnzfla", -0, OP_BI_BH, 19<<26 | 0<<21 | 16<<1 | 1<<0, "bdnzflrl", -0, OP_BI_BDL, 16<<26 | 8<<21 | 0<<1 | 0<<0, "bdnzt", -0, OP_BI_BDA, 16<<26 | 8<<21 | 1<<1 | 0<<0, "bdnzta", -0, OP_BI_BH, 19<<26 | 8<<21 | 16<<1 | 0<<0, "bdnztlr", -0, OP_BI_BDL, 16<<26 | 8<<21 | 0<<1 | 1<<0, "bdnztl", -0, OP_BI_BDA, 16<<26 | 8<<21 | 1<<1 | 1<<0, "bdnztla", -0, OP_BI_BH, 19<<26 | 8<<21 | 16<<1 | 1<<0, "bdnztlrl", -0, OP_BDL, 16<<26 | 18<<21 | 0<<1 | 0<<0, "bdz", -0, OP_BDA, 16<<26 | 18<<21 | 1<<1 | 0<<0, "bdza", -0, OP_BH, 19<<26 | 18<<21 | 16<<1 | 0<<0, "bdzlr", -0, OP_BDL, 16<<26 | 18<<21 | 0<<1 | 1<<0, "bdzl", -0, OP_BDA, 16<<26 | 18<<21 | 1<<1 | 1<<0, "bdzla", -0, OP_BH, 19<<26 | 18<<21 | 16<<1 | 1<<0, "bdzlrl", -0, OP_BI_BDL, 16<<26 | 2<<21 | 0<<1 | 0<<0, "bdzf", -0, OP_BI_BDA, 16<<26 | 2<<21 | 1<<1 | 0<<0, "bdzfa", -0, OP_BI_BH, 19<<26 | 2<<21 | 16<<1 | 0<<0, "bdzflr", -0, OP_BI_BDL, 16<<26 | 2<<21 | 0<<1 | 1<<0, "bdzfl", -0, OP_BI_BDA, 16<<26 | 2<<21 | 1<<1 | 1<<0, "bdzfla", -0, OP_BI_BH, 19<<26 | 2<<21 | 16<<1 | 1<<0, "bdzflrl", -0, OP_BI_BDL, 16<<26 | 10<<21 | 0<<1 | 0<<0, "bdzt", -0, OP_BI_BDA, 16<<26 | 10<<21 | 1<<1 | 0<<0, "bdzta", -0, OP_BI_BH, 19<<26 | 10<<21 | 16<<1 | 0<<0, "bdztlr", -0, OP_BI_BDL, 16<<26 | 10<<21 | 0<<1 | 1<<0, "bdztl", -0, OP_BI_BDA, 16<<26 | 10<<21 | 1<<1 | 1<<0, "bdztla", -0, OP_BI_BH, 19<<26 | 10<<21 | 16<<1 | 1<<0, "bdztlrl", -0, OP_BI_BDL, 16<<26 | 4<<21 | 0<<1 | 0<<0, "bf", -0, OP_BI_BDA, 16<<26 | 4<<21 | 1<<1 | 0<<0, "bfa", -0, OP_BI_BH, 19<<26 | 4<<21 | 528<<1 | 0<<0, "bfctr", -0, OP_BI_BH, 19<<26 | 4<<21 | 528<<1 | 1<<0, "bfctrl", -0, OP_BI_BDL, 16<<26 | 4<<21 | 0<<1 | 1<<0, "bfl", -0, OP_BI_BDA, 16<<26 | 4<<21 | 0<<1 | 1<<0, "bfla", -0, OP_BI_BH, 19<<26 | 4<<21 | 16<<1 | 0<<0, "bflr", -0, OP_BI_BH, 19<<26 | 4<<21 | 16<<1 | 1<<0, "bflrl", -0, OP_BH, 19<<26 | 20<<21 | 16<<1 | 0<<0, "blr", -0, OP_BH, 19<<26 | 20<<21 | 16<<1 | 1<<0, "blrl", -0, OP_BI_BDL, 16<<26 | 12<<21 | 0<<1 | 0<<0, "bt", -0, OP_BI_BDA, 16<<26 | 12<<21 | 1<<1 | 0<<0, "bta", -0, OP_BI_BH, 19<<26 | 12<<21 | 528<<1 | 0<<0, "btctr", -0, OP_BI_BH, 19<<26 | 12<<21 | 528<<1 | 1<<0, "btctrl", -0, OP_BI_BDL, 16<<26 | 12<<21 | 0<<1 | 1<<0, "btl", -0, OP_BI_BDA, 16<<26 | 12<<21 | 0<<1 | 1<<0, "btla", -0, OP_BI_BH, 19<<26 | 12<<21 | 16<<1 | 0<<0, "btlr", -0, OP_BI_BH, 19<<26 | 12<<21 | 16<<1 | 1<<0, "btlrl", +{0, OP_BH, 19<<26 | 20<<21 | 528<<1 | 0<<0, "bctr"}, +{0, OP_BH, 19<<26 | 20<<21 | 528<<1 | 1<<0, "bctrl"}, +{0, OP_BDL, 16<<26 | 16<<21 | 0<<1 | 0<<0, "bdnz"}, +{0, OP_BDA, 16<<26 | 16<<21 | 1<<1 | 0<<0, "bdnza"}, +{0, OP_BH, 19<<26 | 16<<21 | 16<<1 | 0<<0, "bdnzlr"}, +{0, OP_BDL, 16<<26 | 16<<21 | 0<<1 | 1<<0, "bdnzl"}, +{0, OP_BDA, 16<<26 | 16<<21 | 1<<1 | 1<<0, "bdnzla"}, +{0, OP_BH, 19<<26 | 16<<21 | 16<<1 | 1<<0, "bdnzlrl"}, +{0, OP_BI_BDL, 16<<26 | 0<<21 | 0<<1 | 0<<0, "bdnzf"}, +{0, OP_BI_BDA, 16<<26 | 0<<21 | 1<<1 | 0<<0, "bdnzfa"}, +{0, OP_BI_BH, 19<<26 | 0<<21 | 16<<1 | 0<<0, "bdnzflr"}, +{0, OP_BI_BDL, 16<<26 | 0<<21 | 0<<1 | 1<<0, "bdnzfl"}, +{0, OP_BI_BDA, 16<<26 | 0<<21 | 1<<1 | 1<<0, "bdnzfla"}, +{0, OP_BI_BH, 19<<26 | 0<<21 | 16<<1 | 1<<0, "bdnzflrl"}, +{0, OP_BI_BDL, 16<<26 | 8<<21 | 0<<1 | 0<<0, "bdnzt"}, +{0, OP_BI_BDA, 16<<26 | 8<<21 | 1<<1 | 0<<0, "bdnzta"}, +{0, OP_BI_BH, 19<<26 | 8<<21 | 16<<1 | 0<<0, "bdnztlr"}, +{0, OP_BI_BDL, 16<<26 | 8<<21 | 0<<1 | 1<<0, "bdnztl"}, +{0, OP_BI_BDA, 16<<26 | 8<<21 | 1<<1 | 1<<0, "bdnztla"}, +{0, OP_BI_BH, 19<<26 | 8<<21 | 16<<1 | 1<<0, "bdnztlrl"}, +{0, OP_BDL, 16<<26 | 18<<21 | 0<<1 | 0<<0, "bdz"}, +{0, OP_BDA, 16<<26 | 18<<21 | 1<<1 | 0<<0, "bdza"}, +{0, OP_BH, 19<<26 | 18<<21 | 16<<1 | 0<<0, "bdzlr"}, +{0, OP_BDL, 16<<26 | 18<<21 | 0<<1 | 1<<0, "bdzl"}, +{0, OP_BDA, 16<<26 | 18<<21 | 1<<1 | 1<<0, "bdzla"}, +{0, OP_BH, 19<<26 | 18<<21 | 16<<1 | 1<<0, "bdzlrl"}, +{0, OP_BI_BDL, 16<<26 | 2<<21 | 0<<1 | 0<<0, "bdzf"}, +{0, OP_BI_BDA, 16<<26 | 2<<21 | 1<<1 | 0<<0, "bdzfa"}, +{0, OP_BI_BH, 19<<26 | 2<<21 | 16<<1 | 0<<0, "bdzflr"}, +{0, OP_BI_BDL, 16<<26 | 2<<21 | 0<<1 | 1<<0, "bdzfl"}, +{0, OP_BI_BDA, 16<<26 | 2<<21 | 1<<1 | 1<<0, "bdzfla"}, +{0, OP_BI_BH, 19<<26 | 2<<21 | 16<<1 | 1<<0, "bdzflrl"}, +{0, OP_BI_BDL, 16<<26 | 10<<21 | 0<<1 | 0<<0, "bdzt"}, +{0, OP_BI_BDA, 16<<26 | 10<<21 | 1<<1 | 0<<0, "bdzta"}, +{0, OP_BI_BH, 19<<26 | 10<<21 | 16<<1 | 0<<0, "bdztlr"}, +{0, OP_BI_BDL, 16<<26 | 10<<21 | 0<<1 | 1<<0, "bdztl"}, +{0, OP_BI_BDA, 16<<26 | 10<<21 | 1<<1 | 1<<0, "bdztla"}, +{0, OP_BI_BH, 19<<26 | 10<<21 | 16<<1 | 1<<0, "bdztlrl"}, +{0, OP_BI_BDL, 16<<26 | 4<<21 | 0<<1 | 0<<0, "bf"}, +{0, OP_BI_BDA, 16<<26 | 4<<21 | 1<<1 | 0<<0, "bfa"}, +{0, OP_BI_BH, 19<<26 | 4<<21 | 528<<1 | 0<<0, "bfctr"}, +{0, OP_BI_BH, 19<<26 | 4<<21 | 528<<1 | 1<<0, "bfctrl"}, +{0, OP_BI_BDL, 16<<26 | 4<<21 | 0<<1 | 1<<0, "bfl"}, +{0, OP_BI_BDA, 16<<26 | 4<<21 | 0<<1 | 1<<0, "bfla"}, +{0, OP_BI_BH, 19<<26 | 4<<21 | 16<<1 | 0<<0, "bflr"}, +{0, OP_BI_BH, 19<<26 | 4<<21 | 16<<1 | 1<<0, "bflrl"}, +{0, OP_BH, 19<<26 | 20<<21 | 16<<1 | 0<<0, "blr"}, +{0, OP_BH, 19<<26 | 20<<21 | 16<<1 | 1<<0, "blrl"}, +{0, OP_BI_BDL, 16<<26 | 12<<21 | 0<<1 | 0<<0, "bt"}, +{0, OP_BI_BDA, 16<<26 | 12<<21 | 1<<1 | 0<<0, "bta"}, +{0, OP_BI_BH, 19<<26 | 12<<21 | 528<<1 | 0<<0, "btctr"}, +{0, OP_BI_BH, 19<<26 | 12<<21 | 528<<1 | 1<<0, "btctrl"}, +{0, OP_BI_BDL, 16<<26 | 12<<21 | 0<<1 | 1<<0, "btl"}, +{0, OP_BI_BDA, 16<<26 | 12<<21 | 0<<1 | 1<<0, "btla"}, +{0, OP_BI_BH, 19<<26 | 12<<21 | 16<<1 | 0<<0, "btlr"}, +{0, OP_BI_BH, 19<<26 | 12<<21 | 16<<1 | 1<<0, "btlrl"}, /* extended m with condition in BI (page 146) */ -0, OP_BICR_BDL, 16<<26 | 12<<21 | 2<<16 | 0<<1 | 0<<0, "beq", -0, OP_BICR_BDA, 16<<26 | 12<<21 | 2<<16 | 1<<1 | 0<<0, "beqa", -0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 528<<1 | 0<<0, "beqctr", -0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 528<<1 | 1<<0, "beqctrl", -0, OP_BICR_BDL, 16<<26 | 12<<21 | 2<<16 | 0<<1 | 1<<0, "beql", -0, OP_BICR_BDA, 16<<26 | 12<<21 | 2<<16 | 1<<1 | 1<<0, "beqla", -0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 16<<1 | 0<<0, "beqlr", -0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 16<<1 | 1<<0, "beqlrl", -0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 0<<0, "bge", -0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 0<<0, "bgea", -0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 0<<0, "bgectr", -0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 1<<0, "bgectrl", -0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 1<<0, "bgel", -0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 1<<0, "bgela", -0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 0<<0, "bgelr", -0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 1<<0, "bgelrl", -0, OP_BICR_BDL, 16<<26 | 12<<21 | 1<<16 | 0<<1 | 0<<0, "bgt", -0, OP_BICR_BDA, 16<<26 | 12<<21 | 1<<16 | 1<<1 | 0<<0, "bgta", -0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 528<<1 | 0<<0, "bgtctr", -0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 528<<1 | 1<<0, "bgtctrl", -0, OP_BICR_BDL, 16<<26 | 12<<21 | 1<<16 | 0<<1 | 1<<0, "bgtl", -0, OP_BICR_BDA, 16<<26 | 12<<21 | 1<<16 | 1<<1 | 1<<0, "bgtla", -0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 16<<1 | 0<<0, "bgtlr", -0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 16<<1 | 1<<0, "bgtlrl", -0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 0<<0, "ble", -0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 0<<0, "blea", -0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 0<<0, "blectr", -0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 1<<0, "blectrl", -0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 1<<0, "blel", -0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 1<<0, "blela", -0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 0<<0, "blelr", -0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 1<<0, "blelrl", -0, OP_BICR_BDL, 16<<26 | 12<<21 | 0<<16 | 0<<1 | 0<<0, "blt", -0, OP_BICR_BDA, 16<<26 | 12<<21 | 0<<16 | 1<<1 | 0<<0, "blta", -0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 528<<1 | 0<<0, "bltctr", -0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 528<<1 | 1<<0, "bltctrl", -0, OP_BICR_BDL, 16<<26 | 12<<21 | 0<<16 | 0<<1 | 1<<0, "bltl", -0, OP_BICR_BDA, 16<<26 | 12<<21 | 0<<16 | 1<<1 | 1<<0, "bltla", -0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 16<<1 | 0<<0, "bltlr", -0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 16<<1 | 1<<0, "bltlrl", -0, OP_BICR_BDL, 16<<26 | 4<<21 | 2<<16 | 0<<1 | 0<<0, "bne", -0, OP_BICR_BDA, 16<<26 | 4<<21 | 2<<16 | 1<<1 | 0<<0, "bnea", -0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 528<<1 | 0<<0, "bnectr", -0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 528<<1 | 1<<0, "bnectrl", -0, OP_BICR_BDL, 16<<26 | 4<<21 | 2<<16 | 0<<1 | 1<<0, "bnel", -0, OP_BICR_BDA, 16<<26 | 4<<21 | 2<<16 | 1<<1 | 1<<0, "bnela", -0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 16<<1 | 0<<0, "bnelr", -0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 16<<1 | 1<<0, "bnelrl", -0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 0<<0, "bng", -0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 0<<0, "bnga", -0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 0<<0, "bngctr", -0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 1<<0, "bngctrl", -0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 1<<0, "bngl", -0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 1<<0, "bngla", -0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 0<<0, "bnglr", -0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 1<<0, "bnglrl", -0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 0<<0, "bnl", -0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 0<<0, "bnla", -0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 0<<0, "bnlctr", -0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 1<<0, "bnlctrl", -0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 1<<0, "bnll", -0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 1<<0, "bnlla", -0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 0<<0, "bnllr", -0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 1<<0, "bnllrl", -0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 0<<0, "bns", -0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 0<<0, "bnsa", -0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 0<<0, "bnsctr", -0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 1<<0, "bnsctrl", -0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 1<<0, "bnsl", -0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 1<<0, "bnsla", -0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 0<<0, "bnslr", -0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 1<<0, "bnslrl", -0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 0<<0, "bnu", -0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 0<<0, "bnua", -0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 0<<0, "bnuctr", -0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 1<<0, "bnuctrl", -0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 1<<0, "bnul", -0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 1<<0, "bnula", -0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 0<<0, "bnulr", -0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 1<<0, "bnulrl", -0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 0<<0, "bso", -0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 0<<0, "bsoa", -0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 0<<0, "bsoctr", -0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 1<<0, "bsoctrl", -0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 1<<0, "bsol", -0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 1<<0, "bsola", -0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 0<<0, "bsolr", -0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 1<<0, "bsolrl", -0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 0<<0, "bun", -0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 0<<0, "buna", -0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 0<<0, "bunctr", -0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 1<<0, "bunctrl", -0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 1<<0, "bunl", -0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 1<<0, "bunla", -0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 0<<0, "bunlr", -0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 1<<0, "bunlrl", +{0, OP_BICR_BDL, 16<<26 | 12<<21 | 2<<16 | 0<<1 | 0<<0, "beq"}, +{0, OP_BICR_BDA, 16<<26 | 12<<21 | 2<<16 | 1<<1 | 0<<0, "beqa"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 528<<1 | 0<<0, "beqctr"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 528<<1 | 1<<0, "beqctrl"}, +{0, OP_BICR_BDL, 16<<26 | 12<<21 | 2<<16 | 0<<1 | 1<<0, "beql"}, +{0, OP_BICR_BDA, 16<<26 | 12<<21 | 2<<16 | 1<<1 | 1<<0, "beqla"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 16<<1 | 0<<0, "beqlr"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 16<<1 | 1<<0, "beqlrl"}, +{0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 0<<0, "bge"}, +{0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 0<<0, "bgea"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 0<<0, "bgectr"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 1<<0, "bgectrl"}, +{0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 1<<0, "bgel"}, +{0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 1<<0, "bgela"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 0<<0, "bgelr"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 1<<0, "bgelrl"}, +{0, OP_BICR_BDL, 16<<26 | 12<<21 | 1<<16 | 0<<1 | 0<<0, "bgt"}, +{0, OP_BICR_BDA, 16<<26 | 12<<21 | 1<<16 | 1<<1 | 0<<0, "bgta"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 528<<1 | 0<<0, "bgtctr"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 528<<1 | 1<<0, "bgtctrl"}, +{0, OP_BICR_BDL, 16<<26 | 12<<21 | 1<<16 | 0<<1 | 1<<0, "bgtl"}, +{0, OP_BICR_BDA, 16<<26 | 12<<21 | 1<<16 | 1<<1 | 1<<0, "bgtla"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 16<<1 | 0<<0, "bgtlr"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 1<<16 | 16<<1 | 1<<0, "bgtlrl"}, +{0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 0<<0, "ble"}, +{0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 0<<0, "blea"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 0<<0, "blectr"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 1<<0, "blectrl"}, +{0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 1<<0, "blel"}, +{0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 1<<0, "blela"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 0<<0, "blelr"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 1<<0, "blelrl"}, +{0, OP_BICR_BDL, 16<<26 | 12<<21 | 0<<16 | 0<<1 | 0<<0, "blt"}, +{0, OP_BICR_BDA, 16<<26 | 12<<21 | 0<<16 | 1<<1 | 0<<0, "blta"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 528<<1 | 0<<0, "bltctr"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 528<<1 | 1<<0, "bltctrl"}, +{0, OP_BICR_BDL, 16<<26 | 12<<21 | 0<<16 | 0<<1 | 1<<0, "bltl"}, +{0, OP_BICR_BDA, 16<<26 | 12<<21 | 0<<16 | 1<<1 | 1<<0, "bltla"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 16<<1 | 0<<0, "bltlr"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 0<<16 | 16<<1 | 1<<0, "bltlrl"}, +{0, OP_BICR_BDL, 16<<26 | 4<<21 | 2<<16 | 0<<1 | 0<<0, "bne"}, +{0, OP_BICR_BDA, 16<<26 | 4<<21 | 2<<16 | 1<<1 | 0<<0, "bnea"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 528<<1 | 0<<0, "bnectr"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 528<<1 | 1<<0, "bnectrl"}, +{0, OP_BICR_BDL, 16<<26 | 4<<21 | 2<<16 | 0<<1 | 1<<0, "bnel"}, +{0, OP_BICR_BDA, 16<<26 | 4<<21 | 2<<16 | 1<<1 | 1<<0, "bnela"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 16<<1 | 0<<0, "bnelr"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 2<<16 | 16<<1 | 1<<0, "bnelrl"}, +{0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 0<<0, "bng"}, +{0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 0<<0, "bnga"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 0<<0, "bngctr"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 528<<1 | 1<<0, "bngctrl"}, +{0, OP_BICR_BDL, 16<<26 | 4<<21 | 1<<16 | 0<<1 | 1<<0, "bngl"}, +{0, OP_BICR_BDA, 16<<26 | 4<<21 | 1<<16 | 1<<1 | 1<<0, "bngla"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 0<<0, "bnglr"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 1<<16 | 16<<1 | 1<<0, "bnglrl"}, +{0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 0<<0, "bnl"}, +{0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 0<<0, "bnla"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 0<<0, "bnlctr"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 528<<1 | 1<<0, "bnlctrl"}, +{0, OP_BICR_BDL, 16<<26 | 4<<21 | 0<<16 | 0<<1 | 1<<0, "bnll"}, +{0, OP_BICR_BDA, 16<<26 | 4<<21 | 0<<16 | 1<<1 | 1<<0, "bnlla"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 0<<0, "bnllr"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 0<<16 | 16<<1 | 1<<0, "bnllrl"}, +{0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 0<<0, "bns"}, +{0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 0<<0, "bnsa"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 0<<0, "bnsctr"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 1<<0, "bnsctrl"}, +{0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 1<<0, "bnsl"}, +{0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 1<<0, "bnsla"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 0<<0, "bnslr"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 1<<0, "bnslrl"}, +{0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 0<<0, "bnu"}, +{0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 0<<0, "bnua"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 0<<0, "bnuctr"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 528<<1 | 1<<0, "bnuctrl"}, +{0, OP_BICR_BDL, 16<<26 | 4<<21 | 3<<16 | 0<<1 | 1<<0, "bnul"}, +{0, OP_BICR_BDA, 16<<26 | 4<<21 | 3<<16 | 1<<1 | 1<<0, "bnula"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 0<<0, "bnulr"}, +{0, OP_BICR_BH, 19<<26 | 4<<21 | 3<<16 | 16<<1 | 1<<0, "bnulrl"}, +{0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 0<<0, "bso"}, +{0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 0<<0, "bsoa"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 0<<0, "bsoctr"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 1<<0, "bsoctrl"}, +{0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 1<<0, "bsol"}, +{0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 1<<0, "bsola"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 0<<0, "bsolr"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 1<<0, "bsolrl"}, +{0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 0<<0, "bun"}, +{0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 0<<0, "buna"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 0<<0, "bunctr"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 528<<1 | 1<<0, "bunctrl"}, +{0, OP_BICR_BDL, 16<<26 | 12<<21 | 3<<16 | 0<<1 | 1<<0, "bunl"}, +{0, OP_BICR_BDA, 16<<26 | 12<<21 | 3<<16 | 1<<1 | 1<<0, "bunla"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 0<<0, "bunlr"}, +{0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 1<<0, "bunlrl"}, /* extended m for cr logic (page 147) */ -0, OP_BT_BT_BT, 19<<26 | 289<<1, "crset", -0, OP_BT_BT_BT, 19<<26 | 193<<1, "crclr", -0, OP_BT_BA_BA, 19<<26 | 449<<1, "crmove", -0, OP_BT_BA_BA, 19<<26 | 33<<1, "crnot", +{0, OP_BT_BT_BT, 19<<26 | 289<<1, "crset"}, +{0, OP_BT_BT_BT, 19<<26 | 193<<1, "crclr"}, +{0, OP_BT_BA_BA, 19<<26 | 449<<1, "crmove"}, +{0, OP_BT_BA_BA, 19<<26 | 33<<1, "crnot"}, /* Fixed point instructions (page 29) */ -0, OP_RT_RA_D, 34<<26, "lbz", -0, OP_RT_RA_RB, 31<<26 | 87<<1, "lbzx", -0, OP_RT_RA_D, 35<<26, "lbzu", -0, OP_RT_RA_RB, 31<<26 | 119<<1, "lbzux", -0, OP_RT_RA_D, 40<<26, "lhz", -0, OP_RT_RA_RB, 31<<26 | 279<<1, "lhzx", -0, OP_RT_RA_D, 41<<26, "lhzu", -0, OP_RT_RA_RB, 31<<26 | 311<<1, "lhzux", -0, OP_RT_RA_D, 42<<26, "lha", -0, OP_RT_RA_RB, 31<<26 | 343<<1, "lhax", -0, OP_RT_RA_D, 43<<26, "lhau", -0, OP_RT_RA_RB, 31<<26 | 375<<1, "lhaux", -0, OP_RT_RA_D, 32<<26, "lwz", -0, OP_RT_RA_RB, 31<<26 | 23<<1, "lwzx", -0, OP_RT_RA_D, 33<<26, "lwzu", -0, OP_RT_RA_RB, 31<<26 | 55<<1, "lwzux", -0, OP_RT_RA_DS, 58<<26 | 2<<0, "lwa", -0, OP_RT_RA_RB, 31<<26 | 341<<1, "lwax", -0, OP_RT_RA_RB, 31<<26 | 363<<1, "lwaux", -0, OP_RT_RA_DS, 58<<26, "ld", -0, OP_RT_RA_RB, 31<<26 | 21<<1, "ldx", -0, OP_RT_RA_DS, 58<<26 | 1<<0, "ldu", -0, OP_RT_RA_RB, 31<<26 | 53<<1, "ldux", +{0, OP_RT_RA_D, 34<<26, "lbz"}, +{0, OP_RT_RA_RB, 31<<26 | 87<<1, "lbzx"}, +{0, OP_RT_RA_D, 35<<26, "lbzu"}, +{0, OP_RT_RA_RB, 31<<26 | 119<<1, "lbzux"}, +{0, OP_RT_RA_D, 40<<26, "lhz"}, +{0, OP_RT_RA_RB, 31<<26 | 279<<1, "lhzx"}, +{0, OP_RT_RA_D, 41<<26, "lhzu"}, +{0, OP_RT_RA_RB, 31<<26 | 311<<1, "lhzux"}, +{0, OP_RT_RA_D, 42<<26, "lha"}, +{0, OP_RT_RA_RB, 31<<26 | 343<<1, "lhax"}, +{0, OP_RT_RA_D, 43<<26, "lhau"}, +{0, OP_RT_RA_RB, 31<<26 | 375<<1, "lhaux"}, +{0, OP_RT_RA_D, 32<<26, "lwz"}, +{0, OP_RT_RA_RB, 31<<26 | 23<<1, "lwzx"}, +{0, OP_RT_RA_D, 33<<26, "lwzu"}, +{0, OP_RT_RA_RB, 31<<26 | 55<<1, "lwzux"}, +{0, OP_RT_RA_DS, 58<<26 | 2<<0, "lwa"}, +{0, OP_RT_RA_RB, 31<<26 | 341<<1, "lwax"}, +{0, OP_RT_RA_RB, 31<<26 | 363<<1, "lwaux"}, +{0, OP_RT_RA_DS, 58<<26, "ld"}, +{0, OP_RT_RA_RB, 31<<26 | 21<<1, "ldx"}, +{0, OP_RT_RA_DS, 58<<26 | 1<<0, "ldu"}, +{0, OP_RT_RA_RB, 31<<26 | 53<<1, "ldux"}, -0, OP_RS_RA_D, 38<<26, "stb", -0, OP_RS_RA_RB, 31<<26 | 215<<1, "stbx", -0, OP_RS_RA_D, 39<<26, "stbu", -0, OP_RS_RA_RB, 31<<26 | 247<<1, "stbux", -0, OP_RS_RA_D, 44<<26, "sth", -0, OP_RS_RA_RB, 31<<26 | 407<<1, "sthx", -0, OP_RS_RA_D, 45<<26, "sthu", -0, OP_RS_RA_RB, 31<<26 | 439<<1, "sthux", -0, OP_RS_RA_D, 36<<26, "stw", -0, OP_RS_RA_RB, 31<<26 | 151<<1, "stwx", -0, OP_RS_RA_D, 37<<26, "stwu", -0, OP_RS_RA_RB, 31<<26 | 183<<1, "stwux", -0, OP_RS_RA_DS, 62<<26, "std", -0, OP_RS_RA_RB, 31<<26 | 149<<1, "stdx", -0, OP_RS_RA_DS, 62<<26 | 1<<0, "stdu", -0, OP_RS_RA_RB, 31<<26 | 181<<1, "stdux", +{0, OP_RS_RA_D, 38<<26, "stb"}, +{0, OP_RS_RA_RB, 31<<26 | 215<<1, "stbx"}, +{0, OP_RS_RA_D, 39<<26, "stbu"}, +{0, OP_RS_RA_RB, 31<<26 | 247<<1, "stbux"}, +{0, OP_RS_RA_D, 44<<26, "sth"}, +{0, OP_RS_RA_RB, 31<<26 | 407<<1, "sthx"}, +{0, OP_RS_RA_D, 45<<26, "sthu"}, +{0, OP_RS_RA_RB, 31<<26 | 439<<1, "sthux"}, +{0, OP_RS_RA_D, 36<<26, "stw"}, +{0, OP_RS_RA_RB, 31<<26 | 151<<1, "stwx"}, +{0, OP_RS_RA_D, 37<<26, "stwu"}, +{0, OP_RS_RA_RB, 31<<26 | 183<<1, "stwux"}, +{0, OP_RS_RA_DS, 62<<26, "std"}, +{0, OP_RS_RA_RB, 31<<26 | 149<<1, "stdx"}, +{0, OP_RS_RA_DS, 62<<26 | 1<<0, "stdu"}, +{0, OP_RS_RA_RB, 31<<26 | 181<<1, "stdux"}, /* page 42 */ -0, OP_RT_RA_RB, 31<<26 | 790<<1, "lhbrx", -0, OP_RT_RA_RB, 31<<26 | 534<<1, "lwbrx", -0, OP_RS_RA_RB, 31<<26 | 918<<1, "sthbrx", -0, OP_RS_RA_RB, 31<<26 | 662<<1, "stwbrx", +{0, OP_RT_RA_RB, 31<<26 | 790<<1, "lhbrx"}, +{0, OP_RT_RA_RB, 31<<26 | 534<<1, "lwbrx"}, +{0, OP_RS_RA_RB, 31<<26 | 918<<1, "sthbrx"}, +{0, OP_RS_RA_RB, 31<<26 | 662<<1, "stwbrx"}, /* page 44 */ -0, OP_RT_RA_D, 46<<26, "lmw", -0, OP_RS_RA_D, 47<<26, "stmw", +{0, OP_RT_RA_D, 46<<26, "lmw"}, +{0, OP_RS_RA_D, 47<<26, "stmw"}, /* page 45 */ -0, OP_RT_RA_NB, 31<<26 | 597<<1, "lswi", -0, OP_RT_RA_RB, 31<<26 | 533<<1, "lswx", -0, OP_RS_RA_NB, 31<<26 | 725<<1, "stswi", -0, OP_RS_RA_RB, 31<<26 | 661<<1, "stswx", +{0, OP_RT_RA_NB, 31<<26 | 597<<1, "lswi"}, +{0, OP_RT_RA_RB, 31<<26 | 533<<1, "lswx"}, +{0, OP_RS_RA_NB, 31<<26 | 725<<1, "stswi"}, +{0, OP_RS_RA_RB, 31<<26 | 661<<1, "stswx"}, /* page 49 */ -0, OP_RT_RA_SI, 14<<26, "addi", -0, OP_RT_RA_SI, 15<<26, "addis", -0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 266<<1, "add", -0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 266<<1, "addo", -0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 40<<1, "subf", -0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 40<<1, "subfo", -0, OP_RT_RA_SI_addic, 12<<26, "addic", /* special case C */ -0, OP_RT_RA_SI, 8<<26, "subfic", -0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 10<<1, "addc", -0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 10<<1, "addco", -0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 8<<1, "subfc", -0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 8<<1, "subfco", -0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 138<<1, "adde", -0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 138<<1, "addeo", -0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 136<<1, "subfe", -0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 136<<1, "subfeo", -0, OP_RT_RA_C, 31<<26 | 0<<10 | 234<<1, "addme", -0, OP_RT_RA_C, 31<<26 | 1<<10 | 234<<1, "addmeo", -0, OP_RT_RA_C, 31<<26 | 0<<10 | 232<<1, "subfme", -0, OP_RT_RA_C, 31<<26 | 1<<10 | 232<<1, "subfmeo", -0, OP_RT_RA_C, 31<<26 | 0<<10 | 202<<1, "addze", -0, OP_RT_RA_C, 31<<26 | 1<<10 | 202<<1, "addzeo", -0, OP_RT_RA_C, 31<<26 | 0<<10 | 200<<1, "subfze", -0, OP_RT_RA_C, 31<<26 | 1<<10 | 200<<1, "subfzeo", -0, OP_RT_RA_C, 31<<26 | 0<<10 | 104<<1, "neg", -0, OP_RT_RA_C, 31<<26 | 1<<10 | 104<<1, "nego", +{0, OP_RT_RA_SI, 14<<26, "addi"}, +{0, OP_RT_RA_SI, 15<<26, "addis"}, +{0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 266<<1, "add"}, +{0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 266<<1, "addo"}, +{0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 40<<1, "subf"}, +{0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 40<<1, "subfo"}, +{0, OP_RT_RA_SI_addic, 12<<26, "addic"}, /* special case C */ +{0, OP_RT_RA_SI, 8<<26, "subfic"}, +{0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 10<<1, "addc"}, +{0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 10<<1, "addco"}, +{0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 8<<1, "subfc"}, +{0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 8<<1, "subfco"}, +{0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 138<<1, "adde"}, +{0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 138<<1, "addeo"}, +{0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 136<<1, "subfe"}, +{0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 136<<1, "subfeo"}, +{0, OP_RT_RA_C, 31<<26 | 0<<10 | 234<<1, "addme"}, +{0, OP_RT_RA_C, 31<<26 | 1<<10 | 234<<1, "addmeo"}, +{0, OP_RT_RA_C, 31<<26 | 0<<10 | 232<<1, "subfme"}, +{0, OP_RT_RA_C, 31<<26 | 1<<10 | 232<<1, "subfmeo"}, +{0, OP_RT_RA_C, 31<<26 | 0<<10 | 202<<1, "addze"}, +{0, OP_RT_RA_C, 31<<26 | 1<<10 | 202<<1, "addzeo"}, +{0, OP_RT_RA_C, 31<<26 | 0<<10 | 200<<1, "subfze"}, +{0, OP_RT_RA_C, 31<<26 | 1<<10 | 200<<1, "subfzeo"}, +{0, OP_RT_RA_C, 31<<26 | 0<<10 | 104<<1, "neg"}, +{0, OP_RT_RA_C, 31<<26 | 1<<10 | 104<<1, "nego"}, /* extended m for addition (pages 153, 154) */ -0, OP_RT_RA_D, 14<<26, "la", -0, OP_RT_SI, 14<<26 | 0<<16, "li", -0, OP_RT_SI, 15<<26 | 0<<16, "lis", +{0, OP_RT_RA_D, 14<<26, "la"}, +{0, OP_RT_SI, 14<<26 | 0<<16, "li"}, +{0, OP_RT_SI, 15<<26 | 0<<16, "lis"}, /* extended m for subtraction (pages 147, 148) */ -0, OP_RT_RB_RA_C, 31<<26 | 0<<10 | 40<<1, "sub", -0, OP_RT_RB_RA_C, 31<<26 | 1<<10 | 40<<1, "subo", -0, OP_RT_RB_RA_C, 31<<26 | 0<<10 | 8<<1, "subc", -0, OP_RT_RB_RA_C, 31<<26 | 0<<10 | 8<<1, "subco", -0, OP_RT_RA_SI_subi, 14<<26, "subi", -0, OP_RT_RA_SI_subi, 15<<26, "subis", -0, OP_RT_RA_SI_subic, 12<<26, "subic", +{0, OP_RT_RB_RA_C, 31<<26 | 0<<10 | 40<<1, "sub"}, +{0, OP_RT_RB_RA_C, 31<<26 | 1<<10 | 40<<1, "subo"}, +{0, OP_RT_RB_RA_C, 31<<26 | 0<<10 | 8<<1, "subc"}, +{0, OP_RT_RB_RA_C, 31<<26 | 0<<10 | 8<<1, "subco"}, +{0, OP_RT_RA_SI_subi, 14<<26, "subi"}, +{0, OP_RT_RA_SI_subi, 15<<26, "subis"}, +{0, OP_RT_RA_SI_subic, 12<<26, "subic"}, /* page 54 */ -0, OP_RT_RA_SI, 7<<26, "mulli", -0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 233<<1, "mulld", -0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 233<<1, "mulldo", -0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 235<<1, "mullw", -0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 235<<1, "mullwo", -0, OP_RT_RA_RB_C, 31<<26 | 73<<1, "mulhd", -0, OP_RT_RA_RB_C, 31<<26 | 75<<1, "mulhw", -0, OP_RT_RA_RB_C, 31<<26 | 9<<1, "mulhdu", -0, OP_RT_RA_RB_C, 31<<26 | 11<<1, "mulhwu", +{0, OP_RT_RA_SI, 7<<26, "mulli"}, +{0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 233<<1, "mulld"}, +{0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 233<<1, "mulldo"}, +{0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 235<<1, "mullw"}, +{0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 235<<1, "mullwo"}, +{0, OP_RT_RA_RB_C, 31<<26 | 73<<1, "mulhd"}, +{0, OP_RT_RA_RB_C, 31<<26 | 75<<1, "mulhw"}, +{0, OP_RT_RA_RB_C, 31<<26 | 9<<1, "mulhdu"}, +{0, OP_RT_RA_RB_C, 31<<26 | 11<<1, "mulhwu"}, /* page 56 */ -0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 489<<1, "divd", -0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 489<<1, "divdo", -0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 491<<1, "divw", -0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 491<<1, "divwo", -0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 457<<1, "divdu", -0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 457<<1, "divduo", -0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 459<<1, "divwu", -0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 459<<1, "divwuo", +{0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 489<<1, "divd"}, +{0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 489<<1, "divdo"}, +{0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 491<<1, "divw"}, +{0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 491<<1, "divwo"}, +{0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 457<<1, "divdu"}, +{0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 457<<1, "divduo"}, +{0, OP_RT_RA_RB_C, 31<<26 | 0<<10 | 459<<1, "divwu"}, +{0, OP_RT_RA_RB_C, 31<<26 | 1<<10 | 459<<1, "divwuo"}, /* page 58 */ -0, OP_BF_L_RA_SI, 11<<26, "cmpi", -0, OP_BF_L_RA_RB, 31<<26 | 0<<1, "cmp", -0, OP_BF_L_RA_UI, 10<<26, "cmpli", -0, OP_BF_L_RA_RB, 31<<26 | 32<<1, "cmpl", +{0, OP_BF_L_RA_SI, 11<<26, "cmpi"}, +{0, OP_BF_L_RA_RB, 31<<26 | 0<<1, "cmp"}, +{0, OP_BF_L_RA_UI, 10<<26, "cmpli"}, +{0, OP_BF_L_RA_RB, 31<<26 | 32<<1, "cmpl"}, /* extended m for comparison (page 149) */ -0, OP_BF_RA_SI, 11<<26 | 1<<21, "cmpdi", -0, OP_BF_RA_RB, 31<<26 | 1<<21 | 0<<1, "cmpd", -0, OP_BF_RA_UI, 10<<26 | 1<<21, "cmpldi", -0, OP_BF_RA_RB, 31<<26 | 1<<21 | 32<<1, "cmpld", -0, OP_BF_RA_SI, 11<<26 | 0<<21, "cmpwi", -0, OP_BF_RA_RB, 31<<26 | 0<<21 | 0<<1, "cmpw", -0, OP_BF_RA_UI, 10<<26 | 0<<21, "cmplwi", -0, OP_BF_RA_RB, 31<<26 | 0<<21 | 32<<1, "cmplw", +{0, OP_BF_RA_SI, 11<<26 | 1<<21, "cmpdi"}, +{0, OP_BF_RA_RB, 31<<26 | 1<<21 | 0<<1, "cmpd"}, +{0, OP_BF_RA_UI, 10<<26 | 1<<21, "cmpldi"}, +{0, OP_BF_RA_RB, 31<<26 | 1<<21 | 32<<1, "cmpld"}, +{0, OP_BF_RA_SI, 11<<26 | 0<<21, "cmpwi"}, +{0, OP_BF_RA_RB, 31<<26 | 0<<21 | 0<<1, "cmpw"}, +{0, OP_BF_RA_UI, 10<<26 | 0<<21, "cmplwi"}, +{0, OP_BF_RA_RB, 31<<26 | 0<<21 | 32<<1, "cmplw"}, /* page 60 */ -0, OP_TO_RA_SI, 2<<26, "tdi", -0, OP_TO_RA_SI, 3<<26, "twi", -0, OP_TO_RA_RB, 31<<26 | 68<<1, "td", -0, OP_TO_RA_RB, 31<<26 | 4<<1, "tw", +{0, OP_TO_RA_SI, 2<<26, "tdi"}, +{0, OP_TO_RA_SI, 3<<26, "twi"}, +{0, OP_TO_RA_RB, 31<<26 | 68<<1, "td"}, +{0, OP_TO_RA_RB, 31<<26 | 4<<1, "tw"}, /* extended m for traps (page 150) */ -0, OP_TOX_RA_RB, 31<<26 | 4<<21 | 68<<1, "tdeq", -0, OP_TOX_RA_SI, 2<<26 | 4<<21, "tdeqi", -0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 68<<1, "tdge", -0, OP_TOX_RA_SI, 2<<26 | 12<<21, "tdgei", -0, OP_TOX_RA_RB, 31<<26 | 8<<21 | 68<<1, "tdgt", -0, OP_TOX_RA_SI, 2<<26 | 8<<21, "tdgti", -0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 68<<1, "tdle", -0, OP_TOX_RA_SI, 2<<26 | 20<<21, "tdlei", -0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 68<<1, "tdlge", -0, OP_TOX_RA_SI, 2<<26 | 5<<21, "tdlgei", -0, OP_TOX_RA_RB, 31<<26 | 1<<21 | 68<<1, "tdlgt", -0, OP_TOX_RA_SI, 2<<26 | 1<<21, "tdlgti", -0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 68<<1, "tdlle", -0, OP_TOX_RA_SI, 2<<26 | 6<<21, "tdllei", -0, OP_TOX_RA_RB, 31<<26 | 2<<21 | 68<<1, "tdllt", -0, OP_TOX_RA_SI, 2<<26 | 2<<21, "tdllti", -0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 68<<1, "tdlng", -0, OP_TOX_RA_SI, 2<<26 | 6<<21, "tdlngi", -0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 68<<1, "tdlnl", -0, OP_TOX_RA_SI, 2<<26 | 5<<21, "tdlnli", -0, OP_TOX_RA_RB, 31<<26 | 16<<21 | 68<<1, "tdlt", -0, OP_TOX_RA_SI, 2<<26 | 16<<21, "tdlti", -0, OP_TOX_RA_RB, 31<<26 | 24<<21 | 68<<1, "tdne", -0, OP_TOX_RA_SI, 2<<26 | 24<<21, "tdnei", -0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 68<<1, "tdng", -0, OP_TOX_RA_SI, 2<<26 | 20<<21, "tdngi", -0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 68<<1, "tdnl", -0, OP_TOX_RA_SI, 2<<26 | 12<<21, "tdnli", -0, OP_TOX_RA_RB, 31<<26 | 31<<21 | 68<<1, "tdu", -0, OP_TOX_RA_SI, 2<<26 | 31<<21, "tdui", -0, OP, 31<<26 | 31<<21 | 4<<1, "trap", -0, OP_TOX_RA_RB, 31<<26 | 4<<21 | 4<<1, "tweq", -0, OP_TOX_RA_SI, 3<<26 | 4<<21, "tweqi", -0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 4<<1, "twge", -0, OP_TOX_RA_SI, 3<<26 | 12<<21, "twgei", -0, OP_TOX_RA_RB, 31<<26 | 8<<21 | 4<<1, "twgt", -0, OP_TOX_RA_SI, 3<<26 | 8<<21, "twgti", -0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 4<<1, "twle", -0, OP_TOX_RA_SI, 3<<26 | 20<<21, "twlei", -0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 4<<1, "twlge", -0, OP_TOX_RA_SI, 3<<26 | 5<<21, "twlgei", -0, OP_TOX_RA_RB, 31<<26 | 1<<21 | 4<<1, "twlgt", -0, OP_TOX_RA_SI, 3<<26 | 1<<21, "twlgti", -0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 4<<1, "twlle", -0, OP_TOX_RA_SI, 3<<26 | 6<<21, "twllei", -0, OP_TOX_RA_RB, 31<<26 | 2<<21 | 4<<1, "twllt", -0, OP_TOX_RA_SI, 3<<26 | 2<<21, "twllti", -0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 4<<1, "twlng", -0, OP_TOX_RA_SI, 3<<26 | 6<<21, "twlngi", -0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 4<<1, "twlnl", -0, OP_TOX_RA_SI, 3<<26 | 5<<21, "twlnli", -0, OP_TOX_RA_RB, 31<<26 | 16<<21 | 4<<1, "twlt", -0, OP_TOX_RA_SI, 3<<26 | 16<<21, "twlti", -0, OP_TOX_RA_RB, 31<<26 | 24<<21 | 4<<1, "twne", -0, OP_TOX_RA_SI, 3<<26 | 24<<21, "twnei", -0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 4<<1, "twng", -0, OP_TOX_RA_SI, 3<<26 | 20<<21, "twngi", -0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 4<<1, "twnl", -0, OP_TOX_RA_SI, 3<<26 | 12<<21, "twnli", -0, OP_TOX_RA_RB, 31<<26 | 31<<21 | 4<<1, "twu", -0, OP_TOX_RA_SI, 3<<26 | 31<<21, "twui", +{0, OP_TOX_RA_RB, 31<<26 | 4<<21 | 68<<1, "tdeq"}, +{0, OP_TOX_RA_SI, 2<<26 | 4<<21, "tdeqi"}, +{0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 68<<1, "tdge"}, +{0, OP_TOX_RA_SI, 2<<26 | 12<<21, "tdgei"}, +{0, OP_TOX_RA_RB, 31<<26 | 8<<21 | 68<<1, "tdgt"}, +{0, OP_TOX_RA_SI, 2<<26 | 8<<21, "tdgti"}, +{0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 68<<1, "tdle"}, +{0, OP_TOX_RA_SI, 2<<26 | 20<<21, "tdlei"}, +{0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 68<<1, "tdlge"}, +{0, OP_TOX_RA_SI, 2<<26 | 5<<21, "tdlgei"}, +{0, OP_TOX_RA_RB, 31<<26 | 1<<21 | 68<<1, "tdlgt"}, +{0, OP_TOX_RA_SI, 2<<26 | 1<<21, "tdlgti"}, +{0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 68<<1, "tdlle"}, +{0, OP_TOX_RA_SI, 2<<26 | 6<<21, "tdllei"}, +{0, OP_TOX_RA_RB, 31<<26 | 2<<21 | 68<<1, "tdllt"}, +{0, OP_TOX_RA_SI, 2<<26 | 2<<21, "tdllti"}, +{0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 68<<1, "tdlng"}, +{0, OP_TOX_RA_SI, 2<<26 | 6<<21, "tdlngi"}, +{0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 68<<1, "tdlnl"}, +{0, OP_TOX_RA_SI, 2<<26 | 5<<21, "tdlnli"}, +{0, OP_TOX_RA_RB, 31<<26 | 16<<21 | 68<<1, "tdlt"}, +{0, OP_TOX_RA_SI, 2<<26 | 16<<21, "tdlti"}, +{0, OP_TOX_RA_RB, 31<<26 | 24<<21 | 68<<1, "tdne"}, +{0, OP_TOX_RA_SI, 2<<26 | 24<<21, "tdnei"}, +{0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 68<<1, "tdng"}, +{0, OP_TOX_RA_SI, 2<<26 | 20<<21, "tdngi"}, +{0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 68<<1, "tdnl"}, +{0, OP_TOX_RA_SI, 2<<26 | 12<<21, "tdnli"}, +{0, OP_TOX_RA_RB, 31<<26 | 31<<21 | 68<<1, "tdu"}, +{0, OP_TOX_RA_SI, 2<<26 | 31<<21, "tdui"}, +{0, OP, 31<<26 | 31<<21 | 4<<1, "trap"}, +{0, OP_TOX_RA_RB, 31<<26 | 4<<21 | 4<<1, "tweq"}, +{0, OP_TOX_RA_SI, 3<<26 | 4<<21, "tweqi"}, +{0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 4<<1, "twge"}, +{0, OP_TOX_RA_SI, 3<<26 | 12<<21, "twgei"}, +{0, OP_TOX_RA_RB, 31<<26 | 8<<21 | 4<<1, "twgt"}, +{0, OP_TOX_RA_SI, 3<<26 | 8<<21, "twgti"}, +{0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 4<<1, "twle"}, +{0, OP_TOX_RA_SI, 3<<26 | 20<<21, "twlei"}, +{0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 4<<1, "twlge"}, +{0, OP_TOX_RA_SI, 3<<26 | 5<<21, "twlgei"}, +{0, OP_TOX_RA_RB, 31<<26 | 1<<21 | 4<<1, "twlgt"}, +{0, OP_TOX_RA_SI, 3<<26 | 1<<21, "twlgti"}, +{0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 4<<1, "twlle"}, +{0, OP_TOX_RA_SI, 3<<26 | 6<<21, "twllei"}, +{0, OP_TOX_RA_RB, 31<<26 | 2<<21 | 4<<1, "twllt"}, +{0, OP_TOX_RA_SI, 3<<26 | 2<<21, "twllti"}, +{0, OP_TOX_RA_RB, 31<<26 | 6<<21 | 4<<1, "twlng"}, +{0, OP_TOX_RA_SI, 3<<26 | 6<<21, "twlngi"}, +{0, OP_TOX_RA_RB, 31<<26 | 5<<21 | 4<<1, "twlnl"}, +{0, OP_TOX_RA_SI, 3<<26 | 5<<21, "twlnli"}, +{0, OP_TOX_RA_RB, 31<<26 | 16<<21 | 4<<1, "twlt"}, +{0, OP_TOX_RA_SI, 3<<26 | 16<<21, "twlti"}, +{0, OP_TOX_RA_RB, 31<<26 | 24<<21 | 4<<1, "twne"}, +{0, OP_TOX_RA_SI, 3<<26 | 24<<21, "twnei"}, +{0, OP_TOX_RA_RB, 31<<26 | 20<<21 | 4<<1, "twng"}, +{0, OP_TOX_RA_SI, 3<<26 | 20<<21, "twngi"}, +{0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 4<<1, "twnl"}, +{0, OP_TOX_RA_SI, 3<<26 | 12<<21, "twnli"}, +{0, OP_TOX_RA_RB, 31<<26 | 31<<21 | 4<<1, "twu"}, +{0, OP_TOX_RA_SI, 3<<26 | 31<<21, "twui"}, /* page 62 */ -0, OP_RA_RS_UI_CC, 28<<26, "andi", /* C compulsory */ -0, OP_RA_RS_UI_CC, 29<<26, "andis", /* C compulsory */ -0, OP_RA_RS_UI, 24<<26, "ori", -0, OP_RA_RS_UI, 25<<26, "oris", -0, OP_RA_RS_UI, 26<<26, "xori", -0, OP_RA_RS_UI, 27<<26, "xoris", -0, OP_RA_RS_RB_C, 31<<26 | 28<<1, "and", -0, OP_RA_RS_RB_C, 31<<26 | 444<<1, "or", -0, OP_RA_RS_RB_C, 31<<26 | 316<<1, "xor", -0, OP_RA_RS_RB_C, 31<<26 | 476<<1, "nand", -0, OP_RA_RS_RB_C, 31<<26 | 124<<1, "nor", -0, OP_RA_RS_RB_C, 31<<26 | 284<<1, "eqv", -0, OP_RA_RS_RB_C, 31<<26 | 60<<1, "andc", -0, OP_RA_RS_RB_C, 31<<26 | 412<<1, "orc", -0, OP_RA_RS_C, 31<<26 | 954<<1, "extsb", -0, OP_RA_RS_C, 31<<26 | 922<<1, "extsh", -0, OP_RA_RS_C, 31<<26 | 986<<1, "extsw", -0, OP_RA_RS_C, 31<<26 | 58<<1, "cntlzd", -0, OP_RA_RS_C, 31<<26 | 26<<1, "cntlzw", +{0, OP_RA_RS_UI_CC, 28<<26, "andi"}, /* C compulsory */ +{0, OP_RA_RS_UI_CC, 29<<26, "andis"}, /* C compulsory */ +{0, OP_RA_RS_UI, 24<<26, "ori"}, +{0, OP_RA_RS_UI, 25<<26, "oris"}, +{0, OP_RA_RS_UI, 26<<26, "xori"}, +{0, OP_RA_RS_UI, 27<<26, "xoris"}, +{0, OP_RA_RS_RB_C, 31<<26 | 28<<1, "and"}, +{0, OP_RA_RS_RB_C, 31<<26 | 444<<1, "or"}, +{0, OP_RA_RS_RB_C, 31<<26 | 316<<1, "xor"}, +{0, OP_RA_RS_RB_C, 31<<26 | 476<<1, "nand"}, +{0, OP_RA_RS_RB_C, 31<<26 | 124<<1, "nor"}, +{0, OP_RA_RS_RB_C, 31<<26 | 284<<1, "eqv"}, +{0, OP_RA_RS_RB_C, 31<<26 | 60<<1, "andc"}, +{0, OP_RA_RS_RB_C, 31<<26 | 412<<1, "orc"}, +{0, OP_RA_RS_C, 31<<26 | 954<<1, "extsb"}, +{0, OP_RA_RS_C, 31<<26 | 922<<1, "extsh"}, +{0, OP_RA_RS_C, 31<<26 | 986<<1, "extsw"}, +{0, OP_RA_RS_C, 31<<26 | 58<<1, "cntlzd"}, +{0, OP_RA_RS_C, 31<<26 | 26<<1, "cntlzw"}, /* extended m using logic (pages 153, 154) */ -0, OP_RA_RS_RA_C, 31<<26 | 444<<1, "mr", -0, OP, 24<<26, "nop", -0, OP_RA_RS_RA_C, 31<<26 | 124<<1, "not", +{0, OP_RA_RS_RA_C, 31<<26 | 444<<1, "mr"}, +{0, OP, 24<<26, "nop"}, +{0, OP_RA_RS_RA_C, 31<<26 | 124<<1, "not"}, /* page 69 */ -0, OP_RA_RS_SH6_MB6_C, 30<<26 | 0<<2, "rldicl", -0, OP_RA_RS_SH6_MB6_C, 30<<26 | 1<<2, "rldicr", -0, OP_RA_RS_SH6_MB6_C, 30<<26 | 2<<2, "rldic", -0, OP_RA_RS_SH5_MB5_ME5_C, 21<<26, "rlwinm", -0, OP_RA_RS_RB_MB6_C, 30<<26 | 8<<1, "rldcl", -0, OP_RA_RS_RB_MB6_C, 30<<26 | 9<<1, "rldcr", -0, OP_RA_RS_RB_MB5_ME5_C, 23<<26, "rlwnm", -0, OP_RA_RS_SH6_MB6_C, 30<<26 | 3<<2, "rldimi", -0, OP_RA_RS_SH5_MB5_ME5_C, 20<<26, "rlwimi", +{0, OP_RA_RS_SH6_MB6_C, 30<<26 | 0<<2, "rldicl"}, +{0, OP_RA_RS_SH6_MB6_C, 30<<26 | 1<<2, "rldicr"}, +{0, OP_RA_RS_SH6_MB6_C, 30<<26 | 2<<2, "rldic"}, +{0, OP_RA_RS_SH5_MB5_ME5_C, 21<<26, "rlwinm"}, +{0, OP_RA_RS_RB_MB6_C, 30<<26 | 8<<1, "rldcl"}, +{0, OP_RA_RS_RB_MB6_C, 30<<26 | 9<<1, "rldcr"}, +{0, OP_RA_RS_RB_MB5_ME5_C, 23<<26, "rlwnm"}, +{0, OP_RA_RS_SH6_MB6_C, 30<<26 | 3<<2, "rldimi"}, +{0, OP_RA_RS_SH5_MB5_ME5_C, 20<<26, "rlwimi"}, /* extended m for doubleword rotation (page 151) */ -0, OP_clrlsldi, 30<<26 | 2<<2, "clrlsldi", -0, OP_clrldi, 30<<26 | 0<<2, "clrldi", -0, OP_clrrdi, 30<<26 | 1<<2, "clrrdi", -0, OP_extldi, 30<<26 | 0<<2, "extldi", -0, OP_extrdi, 30<<26 | 1<<2, "extrdi", -0, OP_insrdi, 30<<26 | 3<<2, "insrdi", -0, OP_RA_RS_RB_C, 30<<26 | MB6(0) | 8<<1, "rotld", -0, OP_RA_RS_SH6_C, 30<<26 | MB6(0) | 0<<2, "rotldi", -0, OP_rotrdi, 30<<26 | 0<<2, "rotrdi", -0, OP_sldi, 30<<26 | 1<<2, "sldi", -0, OP_srdi, 30<<26 | 0<<2, "srdi", +{0, OP_clrlsldi, 30<<26 | 2<<2, "clrlsldi"}, +{0, OP_clrldi, 30<<26 | 0<<2, "clrldi"}, +{0, OP_clrrdi, 30<<26 | 1<<2, "clrrdi"}, +{0, OP_extldi, 30<<26 | 0<<2, "extldi"}, +{0, OP_extrdi, 30<<26 | 1<<2, "extrdi"}, +{0, OP_insrdi, 30<<26 | 3<<2, "insrdi"}, +{0, OP_RA_RS_RB_C, 30<<26 | MB6(0) | 8<<1, "rotld"}, +{0, OP_RA_RS_SH6_C, 30<<26 | MB6(0) | 0<<2, "rotldi"}, +{0, OP_rotrdi, 30<<26 | 0<<2, "rotrdi"}, +{0, OP_sldi, 30<<26 | 1<<2, "sldi"}, +{0, OP_srdi, 30<<26 | 0<<2, "srdi"}, /* extended m for word rotation (page 152) */ -0, OP_clrlslwi, 21<<26, "clrlslwi", -0, OP_clrlwi, 21<<26, "clrlwi", -0, OP_clrrwi, 21<<26, "clrrwi", -0, OP_extlwi, 21<<26, "extlwi", -0, OP_extrwi, 21<<26, "extrwi", -0, OP_inslwi, 20<<26, "inslwi", -0, OP_insrwi, 20<<26, "insrwi", -0, OP_RA_RS_RB_C, 23<<26 | 0<<6 | 31<<1, "rotlw", -0, OP_RA_RS_SH5_C, 21<<26 | 0<<6 | 31<<1, "rotlwi", -0, OP_rotrwi, 21<<26, "rotrwi", -0, OP_slwi, 21<<26, "slwi", -0, OP_srwi, 21<<26, "srwi", +{0, OP_clrlslwi, 21<<26, "clrlslwi"}, +{0, OP_clrlwi, 21<<26, "clrlwi"}, +{0, OP_clrrwi, 21<<26, "clrrwi"}, +{0, OP_extlwi, 21<<26, "extlwi"}, +{0, OP_extrwi, 21<<26, "extrwi"}, +{0, OP_inslwi, 20<<26, "inslwi"}, +{0, OP_insrwi, 20<<26, "insrwi"}, +{0, OP_RA_RS_RB_C, 23<<26 | 0<<6 | 31<<1, "rotlw"}, +{0, OP_RA_RS_SH5_C, 21<<26 | 0<<6 | 31<<1, "rotlwi"}, +{0, OP_rotrwi, 21<<26, "rotrwi"}, +{0, OP_slwi, 21<<26, "slwi"}, +{0, OP_srwi, 21<<26, "srwi"}, /* page 74 */ -0, OP_RA_RS_RB_C, 31<<26 | 27<<1, "sld", -0, OP_RA_RS_RB_C, 31<<26 | 24<<1, "slw", -0, OP_RA_RS_RB_C, 31<<26 | 539<<1, "srd", -0, OP_RA_RS_RB_C, 31<<26 | 536<<1, "srw", -0, OP_RA_RS_SH6_C, 31<<26 | 413<<2, "sradi", -0, OP_RA_RS_SH5_C, 31<<26 | 824<<1, "srawi", -0, OP_RA_RS_RB_C, 31<<26 | 794<<1, "srad", -0, OP_RA_RS_RB_C, 31<<26 | 792<<1, "sraw", +{0, OP_RA_RS_RB_C, 31<<26 | 27<<1, "sld"}, +{0, OP_RA_RS_RB_C, 31<<26 | 24<<1, "slw"}, +{0, OP_RA_RS_RB_C, 31<<26 | 539<<1, "srd"}, +{0, OP_RA_RS_RB_C, 31<<26 | 536<<1, "srw"}, +{0, OP_RA_RS_SH6_C, 31<<26 | 413<<2, "sradi"}, +{0, OP_RA_RS_SH5_C, 31<<26 | 824<<1, "srawi"}, +{0, OP_RA_RS_RB_C, 31<<26 | 794<<1, "srad"}, +{0, OP_RA_RS_RB_C, 31<<26 | 792<<1, "sraw"}, /* page 78 */ -0, OP_RS_SPR, 31<<26 | 467<<1, "mtspr", -0, OP_RT_SPR, 31<<26 | 339<<1, "mfspr", -0, OP_RS_FXM, 31<<26 | 0<<20 | 144<<1, "mtcrf", -0, OP_RT, 31<<26 | 0<<20 | 19<<1, "mfcr", +{0, OP_RS_SPR, 31<<26 | 467<<1, "mtspr"}, +{0, OP_RT_SPR, 31<<26 | 339<<1, "mfspr"}, +{0, OP_RS_FXM, 31<<26 | 0<<20 | 144<<1, "mtcrf"}, +{0, OP_RT, 31<<26 | 0<<20 | 19<<1, "mfcr"}, /* extended m for special purpose registers (page 153) */ -0, OP_RT, 31<<26 | 9<<16 | 0<<11 | 339<<1, "mfctr", -0, OP_RT, 31<<26 | 8<<16 | 0<<11 | 339<<1, "mflr", -0, OP_RT, 31<<26 | 1<<16 | 0<<11 | 339<<1, "mfxer", -0, OP_RS, 31<<26 | 9<<16 | 0<<11 | 467<<1, "mtctr", -0, OP_RS, 31<<26 | 8<<16 | 0<<11 | 467<<1, "mtlr", -0, OP_RS, 31<<26 | 1<<16 | 0<<11 | 467<<1, "mtxer", +{0, OP_RT, 31<<26 | 9<<16 | 0<<11 | 339<<1, "mfctr"}, +{0, OP_RT, 31<<26 | 8<<16 | 0<<11 | 339<<1, "mflr"}, +{0, OP_RT, 31<<26 | 1<<16 | 0<<11 | 339<<1, "mfxer"}, +{0, OP_RS, 31<<26 | 9<<16 | 0<<11 | 467<<1, "mtctr"}, +{0, OP_RS, 31<<26 | 8<<16 | 0<<11 | 467<<1, "mtlr"}, +{0, OP_RS, 31<<26 | 1<<16 | 0<<11 | 467<<1, "mtxer"}, /* extended m for condition register (page 154) */ -0, OP_RS, 31<<26 | 0<<20 | 255<<12 | 144<<1, "mtcr", +{0, OP_RS, 31<<26 | 0<<20 | 255<<12 | 144<<1, "mtcr"}, /* Floating point instructions (page 83) */ /* page 98 */ -0, OP_FRT_RA_D, 48<<26, "lfs", -0, OP_FRT_RA_RB, 31<<26 | 535<<1, "lfsx", -0, OP_FRT_RA_D, 49<<26, "lfsu", -0, OP_FRT_RA_RB, 31<<26 | 567<<1, "lfsux", -0, OP_FRT_RA_D, 50<<26, "lfd", -0, OP_FRT_RA_RB, 31<<26 | 599<<1, "lfdx", -0, OP_FRT_RA_D, 51<<26, "lfdu", -0, OP_FRT_RA_RB, 31<<26 | 631<<1, "lfdux", -0, OP_FRS_RA_D, 52<<26, "stfs", -0, OP_FRS_RA_RB, 31<<26 | 663<<1, "stfsx", -0, OP_FRS_RA_D, 53<<26, "stfsu", -0, OP_FRS_RA_RB, 31<<26 | 695<<1, "stfsux", -0, OP_FRS_RA_D, 54<<26, "stfd", -0, OP_FRS_RA_RB, 31<<26 | 727<<1, "stfdx", -0, OP_FRS_RA_D, 55<<26, "stfdu", -0, OP_FRS_RA_RB, 31<<26 | 759<<1, "stfdux", -0, OP_FRS_RA_RB, 31<<26 | 983<<1, "stfiwx", +{0, OP_FRT_RA_D, 48<<26, "lfs"}, +{0, OP_FRT_RA_RB, 31<<26 | 535<<1, "lfsx"}, +{0, OP_FRT_RA_D, 49<<26, "lfsu"}, +{0, OP_FRT_RA_RB, 31<<26 | 567<<1, "lfsux"}, +{0, OP_FRT_RA_D, 50<<26, "lfd"}, +{0, OP_FRT_RA_RB, 31<<26 | 599<<1, "lfdx"}, +{0, OP_FRT_RA_D, 51<<26, "lfdu"}, +{0, OP_FRT_RA_RB, 31<<26 | 631<<1, "lfdux"}, +{0, OP_FRS_RA_D, 52<<26, "stfs"}, +{0, OP_FRS_RA_RB, 31<<26 | 663<<1, "stfsx"}, +{0, OP_FRS_RA_D, 53<<26, "stfsu"}, +{0, OP_FRS_RA_RB, 31<<26 | 695<<1, "stfsux"}, +{0, OP_FRS_RA_D, 54<<26, "stfd"}, +{0, OP_FRS_RA_RB, 31<<26 | 727<<1, "stfdx"}, +{0, OP_FRS_RA_D, 55<<26, "stfdu"}, +{0, OP_FRS_RA_RB, 31<<26 | 759<<1, "stfdux"}, +{0, OP_FRS_RA_RB, 31<<26 | 983<<1, "stfiwx"}, /* page 104 */ -0, OP_FRT_FRB_C, 63<<26 | 72<<1, "fmr", -0, OP_FRT_FRB_C, 63<<26 | 40<<1, "fneg", -0, OP_FRT_FRB_C, 63<<26 | 264<<1, "fabs", -0, OP_FRT_FRB_C, 63<<26 | 136<<1, "fnabs", +{0, OP_FRT_FRB_C, 63<<26 | 72<<1, "fmr"}, +{0, OP_FRT_FRB_C, 63<<26 | 40<<1, "fneg"}, +{0, OP_FRT_FRB_C, 63<<26 | 264<<1, "fabs"}, +{0, OP_FRT_FRB_C, 63<<26 | 136<<1, "fnabs"}, -0, OP_FRT_FRA_FRB_C, 63<<26 | 21<<1, "fadd", -0, OP_FRT_FRA_FRB_C, 59<<26 | 21<<1, "fadds", -0, OP_FRT_FRA_FRB_C, 63<<26 | 20<<1, "fsub", -0, OP_FRT_FRA_FRB_C, 59<<26 | 20<<1, "fsubs", -0, OP_FRT_FRA_FRC_C, 63<<26 | 25<<1, "fmul", -0, OP_FRT_FRA_FRC_C, 59<<26 | 25<<1, "fmuls", -0, OP_FRT_FRA_FRB_C, 63<<26 | 18<<1, "fdiv", -0, OP_FRT_FRA_FRB_C, 59<<26 | 18<<1, "fdivs", +{0, OP_FRT_FRA_FRB_C, 63<<26 | 21<<1, "fadd"}, +{0, OP_FRT_FRA_FRB_C, 59<<26 | 21<<1, "fadds"}, +{0, OP_FRT_FRA_FRB_C, 63<<26 | 20<<1, "fsub"}, +{0, OP_FRT_FRA_FRB_C, 59<<26 | 20<<1, "fsubs"}, +{0, OP_FRT_FRA_FRC_C, 63<<26 | 25<<1, "fmul"}, +{0, OP_FRT_FRA_FRC_C, 59<<26 | 25<<1, "fmuls"}, +{0, OP_FRT_FRA_FRB_C, 63<<26 | 18<<1, "fdiv"}, +{0, OP_FRT_FRA_FRB_C, 59<<26 | 18<<1, "fdivs"}, -0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 29<<1, "fmadd", -0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 29<<1, "fmadds", -0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 28<<1, "fmsub", -0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 28<<1, "fmsubs", -0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 31<<1, "fnmadd", -0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 31<<1, "fnmadds", -0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 30<<1, "fnmsub", -0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 30<<1, "fnmsubs", +{0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 29<<1, "fmadd"}, +{0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 29<<1, "fmadds"}, +{0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 28<<1, "fmsub"}, +{0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 28<<1, "fmsubs"}, +{0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 31<<1, "fnmadd"}, +{0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 31<<1, "fnmadds"}, +{0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 30<<1, "fnmsub"}, +{0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 30<<1, "fnmsubs"}, /* page 109 */ -0, OP_FRT_FRB_C, 63<<26 | 12<<1, "frsp", -0, OP_FRT_FRB_C, 63<<26 | 814<<1, "fctid", -0, OP_FRT_FRB_C, 63<<26 | 815<<1, "fctidz", -0, OP_FRT_FRB_C, 63<<26 | 14<<1, "fctiw", -0, OP_FRT_FRB_C, 63<<26 | 15<<1, "fctiwz", -0, OP_FRT_FRB_C, 63<<26 | 846<<1, "fcfid", +{0, OP_FRT_FRB_C, 63<<26 | 12<<1, "frsp"}, +{0, OP_FRT_FRB_C, 63<<26 | 814<<1, "fctid"}, +{0, OP_FRT_FRB_C, 63<<26 | 815<<1, "fctidz"}, +{0, OP_FRT_FRB_C, 63<<26 | 14<<1, "fctiw"}, +{0, OP_FRT_FRB_C, 63<<26 | 15<<1, "fctiwz"}, +{0, OP_FRT_FRB_C, 63<<26 | 846<<1, "fcfid"}, -0, OP_BF_FRA_FRB, 63<<26 | 0<<1, "fcmpu", -0, OP_BF_FRA_FRB, 63<<26 | 32<<1, "fcmpo", +{0, OP_BF_FRA_FRB, 63<<26 | 0<<1, "fcmpu"}, +{0, OP_BF_FRA_FRB, 63<<26 | 32<<1, "fcmpo"}, -0, OP_FRT_C, 63<<26 | 583<<1, "mffs", -0, OP_BF_BFA, 63<<26 | 64<<1, "mcrfs", -0, OP_BF_U_C, 63<<26 | 134<<1, "mtfsfi", -0, OP_FLM_FRB_C, 63<<26 | 711<<1, "mtfsf", -0, OP_BT_C, 63<<26 | 70<<1, "mtfsb0", -0, OP_BT_C, 63<<26 | 38<<1, "mtfsb1", +{0, OP_FRT_C, 63<<26 | 583<<1, "mffs"}, +{0, OP_BF_BFA, 63<<26 | 64<<1, "mcrfs"}, +{0, OP_BF_U_C, 63<<26 | 134<<1, "mtfsfi"}, +{0, OP_FLM_FRB_C, 63<<26 | 711<<1, "mtfsf"}, +{0, OP_BT_C, 63<<26 | 70<<1, "mtfsb0"}, +{0, OP_BT_C, 63<<26 | 38<<1, "mtfsb1"}, -0, OP_FRT_FRB_C, 63<<26 | 22<<1, "fsqrt", -0, OP_FRT_FRB_C, 59<<26 | 22<<1, "fsqrts", -0, OP_FRT_FRB_C, 59<<26 | 24<<1, "fres", -0, OP_FRT_FRB_C, 63<<26 | 26<<1, "frsqrte", -0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 23<<1, "fsel", +{0, OP_FRT_FRB_C, 63<<26 | 22<<1, "fsqrt"}, +{0, OP_FRT_FRB_C, 59<<26 | 22<<1, "fsqrts"}, +{0, OP_FRT_FRB_C, 59<<26 | 24<<1, "fres"}, +{0, OP_FRT_FRB_C, 63<<26 | 26<<1, "frsqrte"}, +{0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 23<<1, "fsel"}, /* Storage control instructions (Book II, page 15) */ /* Book II, page 17 */ -0, OP_RA_RB, 31<<26 | 982<<1, "icbi", -0, OP_RA_RB_TH /* page 35 */, 31<<26 | 278<<1, "dcbt", -0, OP_RA_RB, 31<<26 | 246<<1, "dcbtst", -0, OP_RA_RB, 31<<26 | 1014<<1, "dcbz", -0, OP_RA_RB, 31<<26 | 54<<1, "dcbst", -0, OP_RA_RB, 31<<26 | 86<<1, "dcbf", -0, OP, 19<<26 | 150<<1, "isync", -0, OP_RT_RA_RB, 31<<26 | 20<<1, "lwarx", -0, OP_RT_RA_RB, 31<<26 | 84<<1, "ldarx", -0, OP_RS_RA_RB_CC, 31<<26 | 150<<1 | 1<<0, "stwcx", -0, OP_RS_RA_RB_CC, 31<<26 | 150<<1 | 1<<0, "stdcx", -0, OP_L, 31<<26 | 598<<1, "sync", -0, OP, 31<<26 | 1<<21 | 598<<1, "lwsync", -0, OP, 31<<26 | 2<<21 | 598<<1, "ptesync", -0, OP, 31<<26 | 854<<1, "eieio", +{0, OP_RA_RB, 31<<26 | 982<<1, "icbi"}, +{0, OP_RA_RB_TH /* page 35 */, 31<<26 | 278<<1, "dcbt"}, +{0, OP_RA_RB, 31<<26 | 246<<1, "dcbtst"}, +{0, OP_RA_RB, 31<<26 | 1014<<1, "dcbz"}, +{0, OP_RA_RB, 31<<26 | 54<<1, "dcbst"}, +{0, OP_RA_RB, 31<<26 | 86<<1, "dcbf"}, +{0, OP, 19<<26 | 150<<1, "isync"}, +{0, OP_RT_RA_RB, 31<<26 | 20<<1, "lwarx"}, +{0, OP_RT_RA_RB, 31<<26 | 84<<1, "ldarx"}, +{0, OP_RS_RA_RB_CC, 31<<26 | 150<<1 | 1<<0, "stwcx"}, +{0, OP_RS_RA_RB_CC, 31<<26 | 150<<1 | 1<<0, "stdcx"}, +{0, OP_L, 31<<26 | 598<<1, "sync"}, +{0, OP, 31<<26 | 1<<21 | 598<<1, "lwsync"}, +{0, OP, 31<<26 | 2<<21 | 598<<1, "ptesync"}, +{0, OP, 31<<26 | 854<<1, "eieio"}, /* Time base (Book II, page 30) */ -0, OP_RT_TBR, 31<<26 | 371<<1, "mftb", -0, OP_RT, 31<<26 | 8<<11 | 13<<16 | 371<<1, "mftbu", +{0, OP_RT_TBR, 31<<26 | 371<<1, "mftb"}, +{0, OP_RT, 31<<26 | 8<<11 | 13<<16 | 371<<1, "mftbu"}, /* External control (Book II, page 33) */ -0, OP_RT_RA_RB, 31<<26 | 310<<1, "eciwx", -0, OP_RS_RA_RB, 31<<26 | 438<<1, "ecowx", +{0, OP_RT_RA_RB, 31<<26 | 310<<1, "eciwx"}, +{0, OP_RS_RA_RB, 31<<26 | 438<<1, "ecowx"}, diff --git a/mach/proto/as/comm3.c b/mach/proto/as/comm3.c index 2a24a0878..2b3afaba5 100644 --- a/mach/proto/as/comm3.c +++ b/mach/proto/as/comm3.c @@ -23,30 +23,30 @@ struct outhead outhead = { #include "y.tab.h" item_t keytab[] = { - 0, EXTERN, 0, ".define", - 0, EXTERN, 0, ".extern", - 0, DOT, 0, ".", - 0, DATA, RELO1, ".data1", - 0, DATA, RELO2, ".data2", - 0, DATA, RELO4, ".data4", - 0, DATAF, 4, ".dataf4", - 0, DATAF, 8, ".dataf8", - 0, ASCII, 0, ".ascii", - 0, ASCII, 1, ".asciz", - 0, ALIGN, 0, ".align", - 0, ASSERT, 0, ".assert", - 0, SPACE, 0, ".space", - 0, COMMON, 0, ".comm", - 0, SECTION, 0, ".sect", - 0, BASE, 0, ".base", - 0, SYMB, 0, ".symb", - 0, SYMD, 0, ".symd", - 0, LINE, 0, ".line", - 0, FILe, 0, ".file", + {0, EXTERN, 0, ".define"}, + {0, EXTERN, 0, ".extern"}, + {0, DOT, 0, "."}, + {0, DATA, RELO1, ".data1"}, + {0, DATA, RELO2, ".data2"}, + {0, DATA, RELO4, ".data4"}, + {0, DATAF, 4, ".dataf4"}, + {0, DATAF, 8, ".dataf8"}, + {0, ASCII, 0, ".ascii"}, + {0, ASCII, 1, ".asciz"}, + {0, ALIGN, 0, ".align"}, + {0, ASSERT, 0, ".assert"}, + {0, SPACE, 0, ".space"}, + {0, COMMON, 0, ".comm"}, + {0, SECTION, 0, ".sect"}, + {0, BASE, 0, ".base"}, + {0, SYMB, 0, ".symb"}, + {0, SYMD, 0, ".symd"}, + {0, LINE, 0, ".line"}, + {0, FILe, 0, ".file"}, #ifdef LISTING - 0, LIST, 0, ".nolist", - 0, LIST, 1, ".list", + {0, LIST, 0, ".nolist"}, + {0, LIST, 1, ".list"}, #endif #include "mach3.c" - 0, 0, 0, 0 + {0, 0, 0, 0} }; diff --git a/mach/s2650/as/mach3.c b/mach/s2650/as/mach3.c index e34628b66..b8ba6df9f 100644 --- a/mach/s2650/as/mach3.c +++ b/mach/s2650/as/mach3.c @@ -7,88 +7,88 @@ /* * Signetics 2650 keywords */ -0, REG, R0, "r0", -0, REG, R1, "r1", -0, REG, R2, "r2", -0, REG, R3, "r3", -0, CC, 0, "eq", -0, CC, 0, "z", -0, CC, 1, "gt", -0, CC, 2, "lt", -0, CC, 3, "un", -0, INDE, 0x6000, "i", -0, ZERO, 0x0, "lodz", -0, ZERO, 0x80, "addz", -0, ZERO, 0xA0, "subz", -0, ZERO, 0x94, "dar", -0, ZEROX, 0x40, "andz", -0, ZERO, 0x60, "iorz", -0, ZERO, 0x20, "eorz", -0, ZERO, 0xE0, "comz", -0, ZERO, 0xF0, "wrtd", -0, ZERO, 0x70, "redd", -0, ZERO, 0xB0, "wrtc", -0, ZERO, 0x30, "redc", -0, ZERO, 0x50, "rrr", -0, ZERO, 0xD0, "rrl", -0, ZEROX, 0xC0, "strz", -0, IMMED, 0x04, "lodi", -0, IMMED, 0x84, "addi", -0, IMMED, 0xA4, "subi", -0, IMMED, 0x44, "andi", -0, IMMED, 0x64, "iori", -0, IMMED, 0x24, "eori", -0, IMMED, 0xE4, "comi", -0, IMMED, 0xD4, "wrte", -0, IMMED, 0x54, "rede", -0, IMMED, 0xF4, "tmi", -0, NOOP, 0x1E, "halt", -0, NOOP, 0xC0, "nop", -0, NOOP, 0x92, "lpsu", -0, NOOP, 0x93, "lpsl", -0, NOOP, 0x12, "spsu", -0, NOOP, 0x13, "spsl", -0, REL, 0x08, "lodr", -0, REL, 0xC8, "strr", -0, REL, 0x98, "addr", -0, REL, 0xA8, "subr", -0, REL, 0x48, "andr", -0, REL, 0x68, "iorr", -0, REL, 0x28, "eorr", -0, REL, 0xE8, "comr", -0, ABSO, 0x0C, "loda", -0, ABSO, 0xCC, "stra", -0, ABSO, 0x8C, "adda", -0, ABSO, 0xAC, "suba", -0, ABSO, 0x4C, "anda", -0, ABSO, 0x6C, "iora", -0, ABSO, 0x2C, "eora", -0, ABSO, 0xEC, "coma", -0, PSWM, 0x74, "cpsu", -0, PSWM, 0x75, "cpsl", -0, PSWM, 0x76, "ppsu", -0, PSWM, 0x77, "ppsl", -0, PSWM, 0xB4, "tpsu", -0, PSWM, 0xB5, "tpsl", -0, RET, 0x14, "retc", -0, RET, 0x34, "rete", -0, BRANCR, 0x18, "bctr", -0, BRANCRX, 0x98, "bcfr", -0, REL, 0x58, "brnr", -0, REL, 0xD8, "birr", -0, REL, 0xF8, "bdrr", -0, BRANCR, 0x38, "bstr", -0, BRANCRX, 0xB8, "bsfr", -0, REL, 0x78, "bsnr", -0, BRANCA, 0x1E, "bcta", -0, BRANCAX, 0x9E, "bcfa", -0, BRANRA, 0x5E, "brna", -0, BRANRA, 0xDE, "bira", -0, BRANRA, 0xFE, "bdra", -0, BRANCA, 0x3E, "bsta", -0, BRANCAX, 0xBE, "bsfa", -0, BRANRA, 0x7E, "bsna", -0, ZBRR, 0x9B, "zbrr", -0, ZBRR, 0xBB, "zbsr", -0, BXSA, 0x9F, "bxa", -0, BXSA, 0xBF, "bsxa", +{0, REG, R0, "r0"}, +{0, REG, R1, "r1"}, +{0, REG, R2, "r2"}, +{0, REG, R3, "r3"}, +{0, CC, 0, "eq"}, +{0, CC, 0, "z"}, +{0, CC, 1, "gt"}, +{0, CC, 2, "lt"}, +{0, CC, 3, "un"}, +{0, INDE, 0x6000, "i"}, +{0, ZERO, 0x0, "lodz"}, +{0, ZERO, 0x80, "addz"}, +{0, ZERO, 0xA0, "subz"}, +{0, ZERO, 0x94, "dar"}, +{0, ZEROX, 0x40, "andz"}, +{0, ZERO, 0x60, "iorz"}, +{0, ZERO, 0x20, "eorz"}, +{0, ZERO, 0xE0, "comz"}, +{0, ZERO, 0xF0, "wrtd"}, +{0, ZERO, 0x70, "redd"}, +{0, ZERO, 0xB0, "wrtc"}, +{0, ZERO, 0x30, "redc"}, +{0, ZERO, 0x50, "rrr"}, +{0, ZERO, 0xD0, "rrl"}, +{0, ZEROX, 0xC0, "strz"}, +{0, IMMED, 0x04, "lodi"}, +{0, IMMED, 0x84, "addi"}, +{0, IMMED, 0xA4, "subi"}, +{0, IMMED, 0x44, "andi"}, +{0, IMMED, 0x64, "iori"}, +{0, IMMED, 0x24, "eori"}, +{0, IMMED, 0xE4, "comi"}, +{0, IMMED, 0xD4, "wrte"}, +{0, IMMED, 0x54, "rede"}, +{0, IMMED, 0xF4, "tmi"}, +{0, NOOP, 0x1E, "halt"}, +{0, NOOP, 0xC0, "nop"}, +{0, NOOP, 0x92, "lpsu"}, +{0, NOOP, 0x93, "lpsl"}, +{0, NOOP, 0x12, "spsu"}, +{0, NOOP, 0x13, "spsl"}, +{0, REL, 0x08, "lodr"}, +{0, REL, 0xC8, "strr"}, +{0, REL, 0x98, "addr"}, +{0, REL, 0xA8, "subr"}, +{0, REL, 0x48, "andr"}, +{0, REL, 0x68, "iorr"}, +{0, REL, 0x28, "eorr"}, +{0, REL, 0xE8, "comr"}, +{0, ABSO, 0x0C, "loda"}, +{0, ABSO, 0xCC, "stra"}, +{0, ABSO, 0x8C, "adda"}, +{0, ABSO, 0xAC, "suba"}, +{0, ABSO, 0x4C, "anda"}, +{0, ABSO, 0x6C, "iora"}, +{0, ABSO, 0x2C, "eora"}, +{0, ABSO, 0xEC, "coma"}, +{0, PSWM, 0x74, "cpsu"}, +{0, PSWM, 0x75, "cpsl"}, +{0, PSWM, 0x76, "ppsu"}, +{0, PSWM, 0x77, "ppsl"}, +{0, PSWM, 0xB4, "tpsu"}, +{0, PSWM, 0xB5, "tpsl"}, +{0, RET, 0x14, "retc"}, +{0, RET, 0x34, "rete"}, +{0, BRANCR, 0x18, "bctr"}, +{0, BRANCRX, 0x98, "bcfr"}, +{0, REL, 0x58, "brnr"}, +{0, REL, 0xD8, "birr"}, +{0, REL, 0xF8, "bdrr"}, +{0, BRANCR, 0x38, "bstr"}, +{0, BRANCRX, 0xB8, "bsfr"}, +{0, REL, 0x78, "bsnr"}, +{0, BRANCA, 0x1E, "bcta"}, +{0, BRANCAX, 0x9E, "bcfa"}, +{0, BRANRA, 0x5E, "brna"}, +{0, BRANRA, 0xDE, "bira"}, +{0, BRANRA, 0xFE, "bdra"}, +{0, BRANCA, 0x3E, "bsta"}, +{0, BRANCAX, 0xBE, "bsfa"}, +{0, BRANRA, 0x7E, "bsna"}, +{0, ZBRR, 0x9B, "zbrr"}, +{0, ZBRR, 0xBB, "zbsr"}, +{0, BXSA, 0x9F, "bxa"}, +{0, BXSA, 0xBF, "bsxa"}, diff --git a/mach/vax4/as/mach3.c b/mach/vax4/as/mach3.c index 93bce6faa..30ae7f831 100644 --- a/mach/vax4/as/mach3.c +++ b/mach/vax4/as/mach3.c @@ -8,26 +8,26 @@ * VAX-11 keywords */ -0, REG, 0, "r0", -0, REG, 1, "r1", -0, REG, 2, "r2", -0, REG, 3, "r3", -0, REG, 4, "r4", -0, REG, 5, "r5", -0, REG, 6, "r6", -0, REG, 7, "r7", -0, REG, 8, "r8", -0, REG, 9, "r9", -0, REG, 10, "r10", -0, REG, 11, "r11", -0, REG, 12, "r12", -0, REG, 12, "ap", -0, REG, 13, "r13", -0, REG, 13, "fp", -0, REG, 14, "r14", -0, REG, 14, "sp", -0, REG, 15, "r15", -0, REG, 15, "pc", +{0, REG, 0, "r0"}, +{0, REG, 1, "r1"}, +{0, REG, 2, "r2"}, +{0, REG, 3, "r3"}, +{0, REG, 4, "r4"}, +{0, REG, 5, "r5"}, +{0, REG, 6, "r6"}, +{0, REG, 7, "r7"}, +{0, REG, 8, "r8"}, +{0, REG, 9, "r9"}, +{0, REG, 10, "r10"}, +{0, REG, 11, "r11"}, +{0, REG, 12, "r12"}, +{0, REG, 12, "ap"}, +{0, REG, 13, "r13"}, +{0, REG, 13, "fp"}, +{0, REG, 14, "r14"}, +{0, REG, 14, "sp"}, +{0, REG, 15, "r15"}, +{0, REG, 15, "pc"}, /* For immediate mode, we need the size as specified by the instruction. Ordinary operands are therefore encoded as _w, _b, and _l to indicate @@ -40,377 +40,377 @@ /* integer arithmetic and logical instructions */ -0, OP2_w_w, 0x58, "adawi", -0, OP2_b_b, 0x80, "addb2", -0, OP3_b_b_b, 0x81, "addb3", -0, OP2_w_w, 0xa0, "addw2", -0, OP3_w_w_w, 0xa1, "addw3", -0, OP2_l_l, 0xc0, "addl2", -0, OP3_l_l_l, 0xc1, "addl3", -0, OP2_l_l, 0xd8, "adwc", -0, OP3_b_l_l, 0x78, "ashl", -0, OP3_b_u_u, 0x79, "ashq", -0, OP2_b_b, 0x8a, "bicb2", -0, OP3_b_b_b, 0x8b, "bicb3", -0, OP2_w_w, 0xaa, "bicw2", -0, OP3_w_w_w, 0xab, "bicw3", -0, OP2_l_l, 0xca, "bicl2", -0, OP3_l_l_l, 0xcb, "bicl3", -0, OP2_b_b, 0x88, "bisb2", -0, OP3_b_b_b, 0x89, "bisb3", -0, OP2_w_w, 0xa8, "bisw2", -0, OP3_w_w_w, 0xa9, "bisw3", -0, OP2_l_l, 0xc8, "bisl2", -0, OP3_l_l_l, 0xc9, "bisl3", -0, OP2_b_b, 0x93, "bitb", -0, OP2_w_w, 0xb3, "bitw", -0, OP2_l_l, 0xd3, "bitl", -0, OP1_X, 0x94|(1L<<16), "clrb", -0, OP1_X, 0xb4|(2L<<16), "clrw", -0, OP1_X, 0xd4|(4L<<16), "clrl", -0, OP1_u, 0x7c, "clrq", -0, OP1_u, 0x7cfd, "clro", -0, OP2_b_b, 0x91, "cmpb", -0, OP2_w_w, 0xb1, "cmpw", -0, OP2_l_l, 0xd1, "cmpl", -0, OP2_b_w, 0x99, "cvtbw", -0, OP2_b_l, 0x98, "cvtbl", -0, OP2_w_b, 0x33, "cvtwb", -0, OP2_w_l, 0x32, "cvtwl", -0, OP2_l_b, 0xf6, "cvtlb", -0, OP2_l_w, 0xf7, "cvtlw", -0, OP1_X, 0x97|(1L<<16), "decb", -0, OP1_X, 0xb7|(2L<<16), "decw", -0, OP1_X, 0xd7|(4L<<16), "decl", -0, OP2_b_b, 0x86, "divb2", -0, OP3_b_b_b, 0x87, "divb3", -0, OP2_w_w, 0xa6, "divw2", -0, OP3_w_w_w, 0xa7, "divw3", -0, OP2_l_l, 0xc6, "divl2", -0, OP3_l_l_l, 0xc7, "divl3", -0, OP4_l_u_l_l, 0x7b, "ediv", -0, OP4_l_l_l_u, 0x7a, "emul", -0, OP1_X, 0x96|(1L<<16), "incb", -0, OP1_X, 0xb6|(2L<<16), "incw", -0, OP1_X, 0xd6|(4L<<16), "incl", -0, OP2_b_b, 0x92, "mcomb", -0, OP2_w_w, 0xb2, "mcomw", -0, OP2_l_l, 0xd2, "mcoml", -0, OP2_b_b, 0x8e, "mnegb", -0, OP2_w_w, 0xae, "mnegw", -0, OP2_l_l, 0xce, "mnegl", -0, OP2_b_b, 0x90, "movb", -0, OP2_w_w, 0xb0, "movw", -0, OP2_l_l, 0xd0, "movl", -0, OP2_u_u, 0x7d, "movq", -0, OP2_u_u, 0x7dfd, "movo", -0, OP2_b_w, 0x9b, "movzbw", -0, OP2_b_l, 0x9a, "movzbl", -0, OP2_w_l, 0x3c, "movzwl", -0, OP2_b_b, 0x84, "mulb2", -0, OP3_b_b_b, 0x85, "mulb3", -0, OP2_w_w, 0xa4, "mulw2", -0, OP3_w_w_w, 0xa5, "mulw3", -0, OP2_l_l, 0xc4, "mull2", -0, OP3_l_l_l, 0xc5, "mull3", -0, OP1_X, 0xdd|(4L<<16), "pushl", -0, OP3_b_l_l, 0x9c, "rotl", -0, OP2_l_l, 0xd9, "sbwc", -0, OP2_b_b, 0x82, "subb2", -0, OP3_b_b_b, 0x83, "subb3", -0, OP2_w_w, 0xa2, "subw2", -0, OP3_w_w_w, 0xa3, "subw3", -0, OP2_l_l, 0xc2, "subl2", -0, OP3_l_l_l, 0xc3, "subl3", -0, OP1_X, 0x95|(1L<<16), "tstb", -0, OP1_X, 0xb5|(2L<<16), "tstw", -0, OP1_X, 0xd5|(4L<<16), "tstl", -0, OP2_b_b, 0x8c, "xorb2", -0, OP3_b_b_b, 0x8d, "xorb3", -0, OP2_w_w, 0xac, "xorw2", -0, OP3_w_w_w, 0xad, "xorw3", -0, OP2_l_l, 0xcc, "xorl2", -0, OP3_l_l_l, 0xcd, "xorl3", +{0, OP2_w_w, 0x58, "adawi"}, +{0, OP2_b_b, 0x80, "addb2"}, +{0, OP3_b_b_b, 0x81, "addb3"}, +{0, OP2_w_w, 0xa0, "addw2"}, +{0, OP3_w_w_w, 0xa1, "addw3"}, +{0, OP2_l_l, 0xc0, "addl2"}, +{0, OP3_l_l_l, 0xc1, "addl3"}, +{0, OP2_l_l, 0xd8, "adwc"}, +{0, OP3_b_l_l, 0x78, "ashl"}, +{0, OP3_b_u_u, 0x79, "ashq"}, +{0, OP2_b_b, 0x8a, "bicb2"}, +{0, OP3_b_b_b, 0x8b, "bicb3"}, +{0, OP2_w_w, 0xaa, "bicw2"}, +{0, OP3_w_w_w, 0xab, "bicw3"}, +{0, OP2_l_l, 0xca, "bicl2"}, +{0, OP3_l_l_l, 0xcb, "bicl3"}, +{0, OP2_b_b, 0x88, "bisb2"}, +{0, OP3_b_b_b, 0x89, "bisb3"}, +{0, OP2_w_w, 0xa8, "bisw2"}, +{0, OP3_w_w_w, 0xa9, "bisw3"}, +{0, OP2_l_l, 0xc8, "bisl2"}, +{0, OP3_l_l_l, 0xc9, "bisl3"}, +{0, OP2_b_b, 0x93, "bitb"}, +{0, OP2_w_w, 0xb3, "bitw"}, +{0, OP2_l_l, 0xd3, "bitl"}, +{0, OP1_X, 0x94|(1L<<16), "clrb"}, +{0, OP1_X, 0xb4|(2L<<16), "clrw"}, +{0, OP1_X, 0xd4|(4L<<16), "clrl"}, +{0, OP1_u, 0x7c, "clrq"}, +{0, OP1_u, 0x7cfd, "clro"}, +{0, OP2_b_b, 0x91, "cmpb"}, +{0, OP2_w_w, 0xb1, "cmpw"}, +{0, OP2_l_l, 0xd1, "cmpl"}, +{0, OP2_b_w, 0x99, "cvtbw"}, +{0, OP2_b_l, 0x98, "cvtbl"}, +{0, OP2_w_b, 0x33, "cvtwb"}, +{0, OP2_w_l, 0x32, "cvtwl"}, +{0, OP2_l_b, 0xf6, "cvtlb"}, +{0, OP2_l_w, 0xf7, "cvtlw"}, +{0, OP1_X, 0x97|(1L<<16), "decb"}, +{0, OP1_X, 0xb7|(2L<<16), "decw"}, +{0, OP1_X, 0xd7|(4L<<16), "decl"}, +{0, OP2_b_b, 0x86, "divb2"}, +{0, OP3_b_b_b, 0x87, "divb3"}, +{0, OP2_w_w, 0xa6, "divw2"}, +{0, OP3_w_w_w, 0xa7, "divw3"}, +{0, OP2_l_l, 0xc6, "divl2"}, +{0, OP3_l_l_l, 0xc7, "divl3"}, +{0, OP4_l_u_l_l, 0x7b, "ediv"}, +{0, OP4_l_l_l_u, 0x7a, "emul"}, +{0, OP1_X, 0x96|(1L<<16), "incb"}, +{0, OP1_X, 0xb6|(2L<<16), "incw"}, +{0, OP1_X, 0xd6|(4L<<16), "incl"}, +{0, OP2_b_b, 0x92, "mcomb"}, +{0, OP2_w_w, 0xb2, "mcomw"}, +{0, OP2_l_l, 0xd2, "mcoml"}, +{0, OP2_b_b, 0x8e, "mnegb"}, +{0, OP2_w_w, 0xae, "mnegw"}, +{0, OP2_l_l, 0xce, "mnegl"}, +{0, OP2_b_b, 0x90, "movb"}, +{0, OP2_w_w, 0xb0, "movw"}, +{0, OP2_l_l, 0xd0, "movl"}, +{0, OP2_u_u, 0x7d, "movq"}, +{0, OP2_u_u, 0x7dfd, "movo"}, +{0, OP2_b_w, 0x9b, "movzbw"}, +{0, OP2_b_l, 0x9a, "movzbl"}, +{0, OP2_w_l, 0x3c, "movzwl"}, +{0, OP2_b_b, 0x84, "mulb2"}, +{0, OP3_b_b_b, 0x85, "mulb3"}, +{0, OP2_w_w, 0xa4, "mulw2"}, +{0, OP3_w_w_w, 0xa5, "mulw3"}, +{0, OP2_l_l, 0xc4, "mull2"}, +{0, OP3_l_l_l, 0xc5, "mull3"}, +{0, OP1_X, 0xdd|(4L<<16), "pushl"}, +{0, OP3_b_l_l, 0x9c, "rotl"}, +{0, OP2_l_l, 0xd9, "sbwc"}, +{0, OP2_b_b, 0x82, "subb2"}, +{0, OP3_b_b_b, 0x83, "subb3"}, +{0, OP2_w_w, 0xa2, "subw2"}, +{0, OP3_w_w_w, 0xa3, "subw3"}, +{0, OP2_l_l, 0xc2, "subl2"}, +{0, OP3_l_l_l, 0xc3, "subl3"}, +{0, OP1_X, 0x95|(1L<<16), "tstb"}, +{0, OP1_X, 0xb5|(2L<<16), "tstw"}, +{0, OP1_X, 0xd5|(4L<<16), "tstl"}, +{0, OP2_b_b, 0x8c, "xorb2"}, +{0, OP3_b_b_b, 0x8d, "xorb3"}, +{0, OP2_w_w, 0xac, "xorw2"}, +{0, OP3_w_w_w, 0xad, "xorw3"}, +{0, OP2_l_l, 0xcc, "xorl2"}, +{0, OP3_l_l_l, 0xcd, "xorl3"}, /* Address instructions */ -0, OP2_A_l, 0x9e, "movab", -0, OP2_A_l, 0x3e, "movaw", -0, OP2_A_l, 0xde, "moval", -0, OP2_A_l, 0xde, "movaf", -0, OP2_A_l, 0x7e, "movaq", -0, OP2_A_l, 0x7e, "movad", -0, OP2_A_l, 0x7e, "movag", -0, OP2_A_l, 0x7efd, "movah", -0, OP2_A_l, 0x7efd, "movao", -0, OP1_A, 0x9f, "pushab", -0, OP1_A, 0x3f, "pushaw", -0, OP1_A, 0xdf, "pushal", -0, OP1_A, 0xdf, "pushaf", -0, OP1_A, 0x7f, "pushaq", -0, OP1_A, 0x7f, "pushad", -0, OP1_A, 0x7f, "pushag", -0, OP1_A, 0x7ffd, "pushah", -0, OP1_A, 0x7ffd, "pushao", +{0, OP2_A_l, 0x9e, "movab"}, +{0, OP2_A_l, 0x3e, "movaw"}, +{0, OP2_A_l, 0xde, "moval"}, +{0, OP2_A_l, 0xde, "movaf"}, +{0, OP2_A_l, 0x7e, "movaq"}, +{0, OP2_A_l, 0x7e, "movad"}, +{0, OP2_A_l, 0x7e, "movag"}, +{0, OP2_A_l, 0x7efd, "movah"}, +{0, OP2_A_l, 0x7efd, "movao"}, +{0, OP1_A, 0x9f, "pushab"}, +{0, OP1_A, 0x3f, "pushaw"}, +{0, OP1_A, 0xdf, "pushal"}, +{0, OP1_A, 0xdf, "pushaf"}, +{0, OP1_A, 0x7f, "pushaq"}, +{0, OP1_A, 0x7f, "pushad"}, +{0, OP1_A, 0x7f, "pushag"}, +{0, OP1_A, 0x7ffd, "pushah"}, +{0, OP1_A, 0x7ffd, "pushao"}, /* Variable length bit-field instructions */ -0, OP4_l_b_V_l, 0xec, "cmpv", -0, OP4_l_b_V_l, 0xed, "cmpzv", -0, OP4_l_b_V_l, 0xee, "extv", -0, OP4_l_b_V_l, 0xef, "extzv", -0, OP4_l_b_V_l, 0xeb, "ffc", -0, OP4_l_b_V_l, 0xea, "ffs", -0, OP4_l_l_b_V, 0xf0, "insv", +{0, OP4_l_b_V_l, 0xec, "cmpv"}, +{0, OP4_l_b_V_l, 0xed, "cmpzv"}, +{0, OP4_l_b_V_l, 0xee, "extv"}, +{0, OP4_l_b_V_l, 0xef, "extzv"}, +{0, OP4_l_b_V_l, 0xeb, "ffc"}, +{0, OP4_l_b_V_l, 0xea, "ffs"}, +{0, OP4_l_l_b_V, 0xf0, "insv"}, /* Control instructions */ -0, OP4_b_b_b_Bw, 0x9d, "acbb", -0, OP4_w_w_w_Bw, 0x3d, "acbw", -0, OP4_l_l_l_Bw, 0xf1, "acbl", -0, OP4_u_u_u_Bw, 0x4f, "acbf", -0, OP4_u_u_u_Bw, 0x6f, "acbd", -0, OP4_u_u_u_Bw, 0x4ffd, "acbg", -0, OP4_u_u_u_Bw, 0x6ffd, "acbh", -0, OP3_l_l_Bb, 0xf3, "aobleq", -0, OP3_l_l_Bb, 0xf2, "aoblss", -0, OP1_BX, 0x14|(1L<<16), "bgtr", -0, OP1_BX, 0x15|(1L<<16), "bleq", -0, OP1_BX, 0x12|(1L<<16), "bneq", -0, OP1_BX, 0x12|(1L<<16), "bnequ", -0, OP1_BX, 0x13|(1L<<16), "beql", -0, OP1_BX, 0x13|(1L<<16), "beqlu", -0, OP1_BX, 0x18|(1L<<16), "bgeq", -0, OP1_BX, 0x19|(1L<<16), "blss", -0, OP1_BX, 0x1a|(1L<<16), "bgtru", -0, OP1_BX, 0x1b|(1L<<16), "blequ", -0, OP1_BX, 0x1c|(1L<<16), "bvc", -0, OP1_BX, 0x1d|(1L<<16), "bvs", -0, OP1_BX, 0x1e|(1L<<16), "bgequ", -0, OP1_BX, 0x1e|(1L<<16), "bcc", -0, OP1_BX, 0x1f|(1L<<16), "blssu", -0, OP1_BX, 0x1f|(1L<<16), "bcs", -0, OP3_l_V_Bb, 0xe0, "bbs", -0, OP3_l_V_Bb, 0xe1, "bbc", -0, OP3_l_V_Bb, 0xe2, "bbss", -0, OP3_l_V_Bb, 0xe3, "bbcs", -0, OP3_l_V_Bb, 0xe4, "bbsc", -0, OP3_l_V_Bb, 0xe5, "bbcc", -0, OP3_l_V_Bb, 0xe6, "bbssi", -0, OP3_l_V_Bb, 0xe7, "bbcci", -0, OP2_l_Bb, 0xe8, "blbs", -0, OP2_l_Bb, 0xe9, "blbc", -0, OP1_Be, 0x14, "jgtr", -0, OP1_Be, 0x15, "jleq", -0, OP1_Be, 0x12, "jneq", -0, OP1_Be, 0x12, "jnequ", -0, OP1_Be, 0x13, "jeql", -0, OP1_Be, 0x13, "jeqlu", -0, OP1_Be, 0x18, "jgeq", -0, OP1_Be, 0x19, "jlss", -0, OP1_Be, 0x1a, "jgtru", -0, OP1_Be, 0x1b, "jlequ", -0, OP1_Be, 0x1c, "jvc", -0, OP1_Be, 0x1d, "jvs", -0, OP1_Be, 0x1e, "jgequ", -0, OP1_Be, 0x1e, "jcc", -0, OP1_Be, 0x1f, "jlssu", -0, OP1_Be, 0x1f, "jcs", -0, OP2_l_Be, 0xe8, "jlbs", -0, OP2_l_Be, 0xe9, "jlbc", -0, OP3_l_V_Be, 0xe0, "jbs", -0, OP3_l_V_Be, 0xe1, "jbc", -0, OP3_l_V_Be, 0xe2, "jbss", -0, OP3_l_V_Be, 0xe3, "jbcs", -0, OP3_l_V_Be, 0xe4, "jbsc", -0, OP3_l_V_Be, 0xe5, "jbcc", -0, OP3_l_V_Be, 0xe6, "jbssi", -0, OP3_l_V_Be, 0xe7, "jbcci", -0, OP1_Bx, 0x11, "br", -0, OP1_BX, 0x11|(1L<<16), "brb", -0, OP1_BX, 0x31|(2L<<16), "brw", -0, OP1_Be, 0x11, "jbr", -0, OP1_Bx, 0x10, "bsb", -0, OP1_BX, 0x10|(1L<<16), "bsbb", -0, OP1_BX, 0x30|(2L<<16), "bsbw", -0, CASE_X_X_X, 0x8f|(1L<<16), "caseb", -0, CASE_X_X_X, 0xaf|(2L<<16), "casew", -0, CASE_X_X_X, 0xcf|(4L<<16), "casel", -0, OP1_A, 0x17, "jmp", -0, OP1_A, 0x16, "jsb", -0, OP0, 0x05, "rsb", -0, OP2_l_Bb, 0xf4, "sobgeq", -0, OP2_l_Bb, 0xf5, "sobgtr", +{0, OP4_b_b_b_Bw, 0x9d, "acbb"}, +{0, OP4_w_w_w_Bw, 0x3d, "acbw"}, +{0, OP4_l_l_l_Bw, 0xf1, "acbl"}, +{0, OP4_u_u_u_Bw, 0x4f, "acbf"}, +{0, OP4_u_u_u_Bw, 0x6f, "acbd"}, +{0, OP4_u_u_u_Bw, 0x4ffd, "acbg"}, +{0, OP4_u_u_u_Bw, 0x6ffd, "acbh"}, +{0, OP3_l_l_Bb, 0xf3, "aobleq"}, +{0, OP3_l_l_Bb, 0xf2, "aoblss"}, +{0, OP1_BX, 0x14|(1L<<16), "bgtr"}, +{0, OP1_BX, 0x15|(1L<<16), "bleq"}, +{0, OP1_BX, 0x12|(1L<<16), "bneq"}, +{0, OP1_BX, 0x12|(1L<<16), "bnequ"}, +{0, OP1_BX, 0x13|(1L<<16), "beql"}, +{0, OP1_BX, 0x13|(1L<<16), "beqlu"}, +{0, OP1_BX, 0x18|(1L<<16), "bgeq"}, +{0, OP1_BX, 0x19|(1L<<16), "blss"}, +{0, OP1_BX, 0x1a|(1L<<16), "bgtru"}, +{0, OP1_BX, 0x1b|(1L<<16), "blequ"}, +{0, OP1_BX, 0x1c|(1L<<16), "bvc"}, +{0, OP1_BX, 0x1d|(1L<<16), "bvs"}, +{0, OP1_BX, 0x1e|(1L<<16), "bgequ"}, +{0, OP1_BX, 0x1e|(1L<<16), "bcc"}, +{0, OP1_BX, 0x1f|(1L<<16), "blssu"}, +{0, OP1_BX, 0x1f|(1L<<16), "bcs"}, +{0, OP3_l_V_Bb, 0xe0, "bbs"}, +{0, OP3_l_V_Bb, 0xe1, "bbc"}, +{0, OP3_l_V_Bb, 0xe2, "bbss"}, +{0, OP3_l_V_Bb, 0xe3, "bbcs"}, +{0, OP3_l_V_Bb, 0xe4, "bbsc"}, +{0, OP3_l_V_Bb, 0xe5, "bbcc"}, +{0, OP3_l_V_Bb, 0xe6, "bbssi"}, +{0, OP3_l_V_Bb, 0xe7, "bbcci"}, +{0, OP2_l_Bb, 0xe8, "blbs"}, +{0, OP2_l_Bb, 0xe9, "blbc"}, +{0, OP1_Be, 0x14, "jgtr"}, +{0, OP1_Be, 0x15, "jleq"}, +{0, OP1_Be, 0x12, "jneq"}, +{0, OP1_Be, 0x12, "jnequ"}, +{0, OP1_Be, 0x13, "jeql"}, +{0, OP1_Be, 0x13, "jeqlu"}, +{0, OP1_Be, 0x18, "jgeq"}, +{0, OP1_Be, 0x19, "jlss"}, +{0, OP1_Be, 0x1a, "jgtru"}, +{0, OP1_Be, 0x1b, "jlequ"}, +{0, OP1_Be, 0x1c, "jvc"}, +{0, OP1_Be, 0x1d, "jvs"}, +{0, OP1_Be, 0x1e, "jgequ"}, +{0, OP1_Be, 0x1e, "jcc"}, +{0, OP1_Be, 0x1f, "jlssu"}, +{0, OP1_Be, 0x1f, "jcs"}, +{0, OP2_l_Be, 0xe8, "jlbs"}, +{0, OP2_l_Be, 0xe9, "jlbc"}, +{0, OP3_l_V_Be, 0xe0, "jbs"}, +{0, OP3_l_V_Be, 0xe1, "jbc"}, +{0, OP3_l_V_Be, 0xe2, "jbss"}, +{0, OP3_l_V_Be, 0xe3, "jbcs"}, +{0, OP3_l_V_Be, 0xe4, "jbsc"}, +{0, OP3_l_V_Be, 0xe5, "jbcc"}, +{0, OP3_l_V_Be, 0xe6, "jbssi"}, +{0, OP3_l_V_Be, 0xe7, "jbcci"}, +{0, OP1_Bx, 0x11, "br"}, +{0, OP1_BX, 0x11|(1L<<16), "brb"}, +{0, OP1_BX, 0x31|(2L<<16), "brw"}, +{0, OP1_Be, 0x11, "jbr"}, +{0, OP1_Bx, 0x10, "bsb"}, +{0, OP1_BX, 0x10|(1L<<16), "bsbb"}, +{0, OP1_BX, 0x30|(2L<<16), "bsbw"}, +{0, CASE_X_X_X, 0x8f|(1L<<16), "caseb"}, +{0, CASE_X_X_X, 0xaf|(2L<<16), "casew"}, +{0, CASE_X_X_X, 0xcf|(4L<<16), "casel"}, +{0, OP1_A, 0x17, "jmp"}, +{0, OP1_A, 0x16, "jsb"}, +{0, OP0, 0x05, "rsb"}, +{0, OP2_l_Bb, 0xf4, "sobgeq"}, +{0, OP2_l_Bb, 0xf5, "sobgtr"}, /* Procedure call instructions */ -0, OP2_A_A, 0xfa, "callg", -0, OP2_l_A, 0xfb, "calls", -0, OP0, 0x04, "ret", +{0, OP2_A_A, 0xfa, "callg"}, +{0, OP2_l_A, 0xfb, "calls"}, +{0, OP0, 0x04, "ret"}, /* Miscellaneous instructions */ -0, OP1_X, 0xb9|(2L<<16), "bicpsw", -0, OP1_X, 0xb8|(2L<<16), "bispsw", -0, OP0, 0x03, "bpt", -0, OP0, 0x00, "halt", -0, OP6_l_l_l_l_l_l,0x0a, "index", -0, OP1_X, 0xdc|(4L<<16), "movpsl", -0, OP0, 0x01, "nop", -0, OP1_X, 0xba|(2L<<16), "popr", -0, OP1_X, 0xbb|(2L<<16), "pushr", -0, OP0, 0xfc, "xfc", +{0, OP1_X, 0xb9|(2L<<16), "bicpsw"}, +{0, OP1_X, 0xb8|(2L<<16), "bispsw"}, +{0, OP0, 0x03, "bpt"}, +{0, OP0, 0x00, "halt"}, +{0, OP6_l_l_l_l_l_l,0x0a, "index"}, +{0, OP1_X, 0xdc|(4L<<16), "movpsl"}, +{0, OP0, 0x01, "nop"}, +{0, OP1_X, 0xba|(2L<<16), "popr"}, +{0, OP1_X, 0xbb|(2L<<16), "pushr"}, +{0, OP0, 0xfc, "xfc"}, /* Queue instructions */ -0, OP2_A_A, 0x5c, "insqhi", -0, OP2_A_A, 0x5d, "insqti", -0, OP2_A_A, 0x0e, "insque", -0, OP2_A_l, 0x5e, "remqhi", -0, OP2_A_l, 0x5f, "remqti", -0, OP2_A_l, 0x0f, "remque", +{0, OP2_A_A, 0x5c, "insqhi"}, +{0, OP2_A_A, 0x5d, "insqti"}, +{0, OP2_A_A, 0x0e, "insque"}, +{0, OP2_A_l, 0x5e, "remqhi"}, +{0, OP2_A_l, 0x5f, "remqti"}, +{0, OP2_A_l, 0x0f, "remque"}, /* Floating point instructions */ -0, OP2_u_u, 0x40, "addf2", -0, OP3_u_u_u, 0x41, "addf3", -0, OP2_u_u, 0x60, "addd2", -0, OP3_u_u_u, 0x61, "addd3", -0, OP2_u_u, 0x40fd, "addg2", -0, OP3_u_u_u, 0x41fd, "addg3", -0, OP2_u_u, 0x60fd, "addh2", -0, OP3_u_u_u, 0x61fd, "addh3", -0, OP1_u, 0xd4, "clrf", -0, OP1_u, 0x7c, "clrd", -0, OP1_u, 0x7c, "clrg", -0, OP1_u, 0x7cfd, "clrh", -0, OP2_u_u, 0x51, "cmpf", -0, OP2_u_u, 0x71, "cmpd", -0, OP2_u_u, 0x51fd, "cmpg", -0, OP2_u_u, 0x71fd, "cmph", -0, OP2_b_u, 0x4c, "cvtbf", -0, OP2_b_u, 0x6c, "cvtbd", -0, OP2_b_u, 0x4cfd, "cvtbg", -0, OP2_b_u, 0x6cfd, "cvtbh", -0, OP2_w_u, 0x4d, "cvtwf", -0, OP2_w_u, 0x6d, "cvtwd", -0, OP2_w_u, 0x4dfd, "cvtwg", -0, OP2_w_u, 0x6dfd, "cvtwh", -0, OP2_l_u, 0x4e, "cvtlf", -0, OP2_l_u, 0x6e, "cvtld", -0, OP2_l_u, 0x4efd, "cvtlg", -0, OP2_l_u, 0x6efd, "cvtlh", -0, OP2_u_b, 0x48, "cvtfb", -0, OP2_u_b, 0x68, "cvtdb", -0, OP2_u_b, 0x48fd, "cvtgb", -0, OP2_u_b, 0x68fd, "cvthb", -0, OP2_u_w, 0x49, "cvtfw", -0, OP2_u_w, 0x69, "cvtdw", -0, OP2_u_w, 0x49fd, "cvtgw", -0, OP2_u_w, 0x69fd, "cvthw", -0, OP2_u_l, 0x4a, "cvtfl", -0, OP2_u_l, 0x6a, "cvtdl", -0, OP2_u_l, 0x4afd, "cvtgl", -0, OP2_u_l, 0x6afd, "cvthl", -0, OP2_u_l, 0x4b, "cvtrfl", -0, OP2_u_l, 0x6b, "cvtrdl", -0, OP2_u_l, 0x4bfd, "cvtrgl", -0, OP2_u_l, 0x6bfd, "cvtrhl", -0, OP2_u_u, 0x56, "cvtfd", -0, OP2_u_u, 0x99fd, "cvtfg", -0, OP2_u_u, 0x98fd, "cvtfh", -0, OP2_u_u, 0x76, "cvtdf", -0, OP2_u_u, 0x32fd, "cvtdh", -0, OP2_u_u, 0x33fd, "cvtgf", -0, OP2_u_u, 0x56fd, "cvtgh", -0, OP2_u_u, 0xf6fd, "cvthf", -0, OP2_u_u, 0xf7fd, "cvthd", -0, OP2_u_u, 0x76fd, "cvthg", -0, OP2_u_u, 0x46, "divf2", -0, OP3_u_u_u, 0x47, "divf3", -0, OP2_u_u, 0x66, "divd2", -0, OP3_u_u_u, 0x67, "divd3", -0, OP2_u_u, 0x46fd, "divg2", -0, OP3_u_u_u, 0x47fd, "divg3", -0, OP2_u_u, 0x66fd, "divh2", -0, OP3_u_u_u, 0x67fd, "divh3", -0, OP5_u_b_u_l_u, 0x54, "emodf", -0, OP5_u_b_u_l_u, 0x74, "emodd", -0, OP5_u_w_u_l_u, 0x54fd, "emodg", -0, OP5_u_w_u_l_u, 0x74fd, "emodh", -0, OP2_u_u, 0x52, "mnegf", -0, OP2_u_u, 0x72, "mnegd", -0, OP2_u_u, 0x52fd, "mnegg", -0, OP2_u_u, 0x72fd, "mnegh", -0, OP2_u_u, 0x50, "movf", -0, OP2_u_u, 0x70, "movd", -0, OP2_u_u, 0x50fd, "movg", -0, OP2_u_u, 0x70fd, "movh", -0, OP2_u_u, 0x44, "mulf2", -0, OP3_u_u_u, 0x45, "mulf3", -0, OP2_u_u, 0x64, "muld2", -0, OP3_u_u_u, 0x65, "muld3", -0, OP2_u_u, 0x44fd, "mulg2", -0, OP3_u_u_u, 0x45fd, "mulg3", -0, OP2_u_u, 0x64fd, "mulh2", -0, OP3_u_u_u, 0x65fd, "mulh3", -0, OP3_u_w_A, 0x55, "polyf", -0, OP3_u_w_A, 0x75, "polyd", -0, OP3_u_w_A, 0x55fd, "polyg", -0, OP3_u_w_A, 0x75fd, "polyh", -0, OP2_u_u, 0x42, "subf2", -0, OP3_u_u_u, 0x43, "subf3", -0, OP2_u_u, 0x62, "subd2", -0, OP3_u_u_u, 0x63, "subd3", -0, OP2_u_u, 0x42fd, "subg2", -0, OP3_u_u_u, 0x43fd, "subg3", -0, OP2_u_u, 0x62fd, "subh2", -0, OP3_u_u_u, 0x63fd, "subh3", -0, OP1_u, 0x53, "tstf", -0, OP1_u, 0x73, "tstd", -0, OP1_u, 0x53fd, "tstg", -0, OP1_u, 0x73fd, "tsth", +{0, OP2_u_u, 0x40, "addf2"}, +{0, OP3_u_u_u, 0x41, "addf3"}, +{0, OP2_u_u, 0x60, "addd2"}, +{0, OP3_u_u_u, 0x61, "addd3"}, +{0, OP2_u_u, 0x40fd, "addg2"}, +{0, OP3_u_u_u, 0x41fd, "addg3"}, +{0, OP2_u_u, 0x60fd, "addh2"}, +{0, OP3_u_u_u, 0x61fd, "addh3"}, +{0, OP1_u, 0xd4, "clrf"}, +{0, OP1_u, 0x7c, "clrd"}, +{0, OP1_u, 0x7c, "clrg"}, +{0, OP1_u, 0x7cfd, "clrh"}, +{0, OP2_u_u, 0x51, "cmpf"}, +{0, OP2_u_u, 0x71, "cmpd"}, +{0, OP2_u_u, 0x51fd, "cmpg"}, +{0, OP2_u_u, 0x71fd, "cmph"}, +{0, OP2_b_u, 0x4c, "cvtbf"}, +{0, OP2_b_u, 0x6c, "cvtbd"}, +{0, OP2_b_u, 0x4cfd, "cvtbg"}, +{0, OP2_b_u, 0x6cfd, "cvtbh"}, +{0, OP2_w_u, 0x4d, "cvtwf"}, +{0, OP2_w_u, 0x6d, "cvtwd"}, +{0, OP2_w_u, 0x4dfd, "cvtwg"}, +{0, OP2_w_u, 0x6dfd, "cvtwh"}, +{0, OP2_l_u, 0x4e, "cvtlf"}, +{0, OP2_l_u, 0x6e, "cvtld"}, +{0, OP2_l_u, 0x4efd, "cvtlg"}, +{0, OP2_l_u, 0x6efd, "cvtlh"}, +{0, OP2_u_b, 0x48, "cvtfb"}, +{0, OP2_u_b, 0x68, "cvtdb"}, +{0, OP2_u_b, 0x48fd, "cvtgb"}, +{0, OP2_u_b, 0x68fd, "cvthb"}, +{0, OP2_u_w, 0x49, "cvtfw"}, +{0, OP2_u_w, 0x69, "cvtdw"}, +{0, OP2_u_w, 0x49fd, "cvtgw"}, +{0, OP2_u_w, 0x69fd, "cvthw"}, +{0, OP2_u_l, 0x4a, "cvtfl"}, +{0, OP2_u_l, 0x6a, "cvtdl"}, +{0, OP2_u_l, 0x4afd, "cvtgl"}, +{0, OP2_u_l, 0x6afd, "cvthl"}, +{0, OP2_u_l, 0x4b, "cvtrfl"}, +{0, OP2_u_l, 0x6b, "cvtrdl"}, +{0, OP2_u_l, 0x4bfd, "cvtrgl"}, +{0, OP2_u_l, 0x6bfd, "cvtrhl"}, +{0, OP2_u_u, 0x56, "cvtfd"}, +{0, OP2_u_u, 0x99fd, "cvtfg"}, +{0, OP2_u_u, 0x98fd, "cvtfh"}, +{0, OP2_u_u, 0x76, "cvtdf"}, +{0, OP2_u_u, 0x32fd, "cvtdh"}, +{0, OP2_u_u, 0x33fd, "cvtgf"}, +{0, OP2_u_u, 0x56fd, "cvtgh"}, +{0, OP2_u_u, 0xf6fd, "cvthf"}, +{0, OP2_u_u, 0xf7fd, "cvthd"}, +{0, OP2_u_u, 0x76fd, "cvthg"}, +{0, OP2_u_u, 0x46, "divf2"}, +{0, OP3_u_u_u, 0x47, "divf3"}, +{0, OP2_u_u, 0x66, "divd2"}, +{0, OP3_u_u_u, 0x67, "divd3"}, +{0, OP2_u_u, 0x46fd, "divg2"}, +{0, OP3_u_u_u, 0x47fd, "divg3"}, +{0, OP2_u_u, 0x66fd, "divh2"}, +{0, OP3_u_u_u, 0x67fd, "divh3"}, +{0, OP5_u_b_u_l_u, 0x54, "emodf"}, +{0, OP5_u_b_u_l_u, 0x74, "emodd"}, +{0, OP5_u_w_u_l_u, 0x54fd, "emodg"}, +{0, OP5_u_w_u_l_u, 0x74fd, "emodh"}, +{0, OP2_u_u, 0x52, "mnegf"}, +{0, OP2_u_u, 0x72, "mnegd"}, +{0, OP2_u_u, 0x52fd, "mnegg"}, +{0, OP2_u_u, 0x72fd, "mnegh"}, +{0, OP2_u_u, 0x50, "movf"}, +{0, OP2_u_u, 0x70, "movd"}, +{0, OP2_u_u, 0x50fd, "movg"}, +{0, OP2_u_u, 0x70fd, "movh"}, +{0, OP2_u_u, 0x44, "mulf2"}, +{0, OP3_u_u_u, 0x45, "mulf3"}, +{0, OP2_u_u, 0x64, "muld2"}, +{0, OP3_u_u_u, 0x65, "muld3"}, +{0, OP2_u_u, 0x44fd, "mulg2"}, +{0, OP3_u_u_u, 0x45fd, "mulg3"}, +{0, OP2_u_u, 0x64fd, "mulh2"}, +{0, OP3_u_u_u, 0x65fd, "mulh3"}, +{0, OP3_u_w_A, 0x55, "polyf"}, +{0, OP3_u_w_A, 0x75, "polyd"}, +{0, OP3_u_w_A, 0x55fd, "polyg"}, +{0, OP3_u_w_A, 0x75fd, "polyh"}, +{0, OP2_u_u, 0x42, "subf2"}, +{0, OP3_u_u_u, 0x43, "subf3"}, +{0, OP2_u_u, 0x62, "subd2"}, +{0, OP3_u_u_u, 0x63, "subd3"}, +{0, OP2_u_u, 0x42fd, "subg2"}, +{0, OP3_u_u_u, 0x43fd, "subg3"}, +{0, OP2_u_u, 0x62fd, "subh2"}, +{0, OP3_u_u_u, 0x63fd, "subh3"}, +{0, OP1_u, 0x53, "tstf"}, +{0, OP1_u, 0x73, "tstd"}, +{0, OP1_u, 0x53fd, "tstg"}, +{0, OP1_u, 0x73fd, "tsth"}, /* Character string instructions */ -0, OP3_w_A_A, 0x29, "cmpc3", -0, OP5_w_A_b_w_A, 0x2d, "cmpc5", -0, OP3_b_w_A, 0x3a, "locc", -0, OP4_w_A_w_A, 0x39, "matchc", -0, OP3_w_A_A, 0x28, "movc3", -0, OP5_w_A_b_w_A, 0x2c, "movc5", -0, OP6_w_A_b_A_w_A,0x2e, "movtc", -0, OP6_w_A_b_A_w_A,0x2f, "movtuc", -0, OP4_w_A_A_b, 0x2a, "scanc", -0, OP3_b_w_A, 0x3b, "skpc", -0, OP4_w_A_A_b, 0x2b, "spanc", +{0, OP3_w_A_A, 0x29, "cmpc3"}, +{0, OP5_w_A_b_w_A, 0x2d, "cmpc5"}, +{0, OP3_b_w_A, 0x3a, "locc"}, +{0, OP4_w_A_w_A, 0x39, "matchc"}, +{0, OP3_w_A_A, 0x28, "movc3"}, +{0, OP5_w_A_b_w_A, 0x2c, "movc5"}, +{0, OP6_w_A_b_A_w_A,0x2e, "movtc"}, +{0, OP6_w_A_b_A_w_A,0x2f, "movtuc"}, +{0, OP4_w_A_A_b, 0x2a, "scanc"}, +{0, OP3_b_w_A, 0x3b, "skpc"}, +{0, OP4_w_A_A_b, 0x2b, "spanc"}, /* Cyclic redundancy check instructions */ -0, OP4_A_l_w_A, 0x0b, "crc", +{0, OP4_A_l_w_A, 0x0b, "crc"}, /* Decimal string instructions */ -0, OP4_w_A_w_A, 0x20, "addp4", -0, OP6_w_A_w_A_w_A,0x21, "addp6", -0, OP6_b_w_A_b_w_A,0xf8, "ashp", -0, OP3_w_A_A, 0x35, "cmpp3", -0, OP4_w_A_w_A, 0x37, "cmpp4", -0, OP3_l_w_A, 0xf9, "cvtlp", -0, OP3_w_A_l, 0x36, "cvtpl", -0, OP4_w_A_w_A, 0x08, "cvtps", -0, OP5_w_A_A_w_A, 0x24, "cvtpt", -0, OP4_w_A_w_A, 0x09, "cvtsp", -0, OP5_w_A_A_w_A, 0x26, "cvttp", -0, OP6_w_A_w_A_w_A,0x27, "divp", -0, OP3_w_A_A, 0x34, "movp", -0, OP6_w_A_w_A_w_A,0x25, "mulp", -0, OP4_w_A_w_A, 0x22, "subp4", -0, OP6_w_A_w_A_w_A,0x23, "subp6", +{0, OP4_w_A_w_A, 0x20, "addp4"}, +{0, OP6_w_A_w_A_w_A,0x21, "addp6"}, +{0, OP6_b_w_A_b_w_A,0xf8, "ashp"}, +{0, OP3_w_A_A, 0x35, "cmpp3"}, +{0, OP4_w_A_w_A, 0x37, "cmpp4"}, +{0, OP3_l_w_A, 0xf9, "cvtlp"}, +{0, OP3_w_A_l, 0x36, "cvtpl"}, +{0, OP4_w_A_w_A, 0x08, "cvtps"}, +{0, OP5_w_A_A_w_A, 0x24, "cvtpt"}, +{0, OP4_w_A_w_A, 0x09, "cvtsp"}, +{0, OP5_w_A_A_w_A, 0x26, "cvttp"}, +{0, OP6_w_A_w_A_w_A,0x27, "divp"}, +{0, OP3_w_A_A, 0x34, "movp"}, +{0, OP6_w_A_w_A_w_A,0x25, "mulp"}, +{0, OP4_w_A_w_A, 0x22, "subp4"}, +{0, OP6_w_A_w_A_w_A,0x23, "subp6"}, /* Edit instruction */ -0, OP4_w_A_A_A, 0x38, "editpc", +{0, OP4_w_A_A_A, 0x38, "editpc"}, /* Other VAX-11 instructions */ @@ -419,19 +419,19 @@ to the VAX-11 Architecture Reference Manual, Revision 6.1, 1982, the access type is b, which means that the operand is a branch displacement. */ -0, OP1_BX, 0xfeff|(2L<<16),"bugw", -0, OP1_BX, 0xfdff|(4L<<16),"bugl", +{0, OP1_BX, 0xfeff|(2L<<16),"bugw"}, +{0, OP1_BX, 0xfdff|(4L<<16),"bugl"}, -0, OP3_b_w_A, 0x0c, "prober", -0, OP3_b_w_A, 0x0d, "probew", +{0, OP3_b_w_A, 0x0c, "prober"}, +{0, OP3_b_w_A, 0x0d, "probew"}, -0, OP0, 0x02, "rei", -0, OP1_X, 0xbc|(2L<<16), "chmk", -0, OP1_X, 0xbd|(2L<<16), "chme", -0, OP1_X, 0xbe|(2L<<16), "chms", -0, OP1_X, 0xbf|(2L<<16), "chmu", +{0, OP0, 0x02, "rei"}, +{0, OP1_X, 0xbc|(2L<<16), "chmk"}, +{0, OP1_X, 0xbd|(2L<<16), "chme"}, +{0, OP1_X, 0xbe|(2L<<16), "chms"}, +{0, OP1_X, 0xbf|(2L<<16), "chmu"}, -0, OP0, 0x06, "ldpctx", -0, OP0, 0x07, "svpctx", -0, OP2_l_l, 0xda, "mtpr", -0, OP2_l_l, 0xdb, "mfpr", +{0, OP0, 0x06, "ldpctx"}, +{0, OP0, 0x07, "svpctx"}, +{0, OP2_l_l, 0xda, "mtpr"}, +{0, OP2_l_l, 0xdb, "mfpr"}, diff --git a/mach/vc4/as/mach3.c b/mach/vc4/as/mach3.c index 4ca73f4ed..b7b8d4792 100644 --- a/mach/vc4/as/mach3.c +++ b/mach/vc4/as/mach3.c @@ -7,147 +7,147 @@ /* Integer registers */ -0, GPR, 0, "r0", -0, GPR, 1, "r1", -0, GPR, 2, "r2", -0, GPR, 3, "r3", -0, GPR, 4, "r4", -0, GPR, 5, "r5", +{0, GPR, 0, "r0"}, +{0, GPR, 1, "r1"}, +{0, GPR, 2, "r2"}, +{0, GPR, 3, "r3"}, +{0, GPR, 4, "r4"}, +{0, GPR, 5, "r5"}, -0, GPR, 6, "r6", -0, GPR, 7, "r7", -0, GPR, 8, "r8", -0, GPR, 9, "r9", -0, GPR, 10, "r10", -0, GPR, 11, "r11", -0, GPR, 12, "r12", -0, GPR, 13, "r13", -0, GPR, 14, "r14", -0, GPR, 15, "r15", -0, GPR, 16, "r16", -0, GPR, 17, "r17", -0, GPR, 18, "r18", -0, GPR, 19, "r19", -0, GPR, 20, "r20", -0, GPR, 21, "r21", -0, GPR, 22, "r22", -0, GPR, 23, "r23", -0, GPR, 24, "r24", -0, GPR, 24, "fp", +{0, GPR, 6, "r6"}, +{0, GPR, 7, "r7"}, +{0, GPR, 8, "r8"}, +{0, GPR, 9, "r9"}, +{0, GPR, 10, "r10"}, +{0, GPR, 11, "r11"}, +{0, GPR, 12, "r12"}, +{0, GPR, 13, "r13"}, +{0, GPR, 14, "r14"}, +{0, GPR, 15, "r15"}, +{0, GPR, 16, "r16"}, +{0, GPR, 17, "r17"}, +{0, GPR, 18, "r18"}, +{0, GPR, 19, "r19"}, +{0, GPR, 20, "r20"}, +{0, GPR, 21, "r21"}, +{0, GPR, 22, "r22"}, +{0, GPR, 23, "r23"}, +{0, GPR, 24, "r24"}, +{0, GPR, 24, "fp"}, -0, GPR, 25, "r25", -0, GPR, 25, "sp", -0, GPR, 26, "r26", -0, GPR, 26, "lr", -0, GPR, 27, "r27", -0, GPR, 28, "r28", -0, GPR, 29, "r29", -0, GPR, 30, "r30", -0, GPR, 30, "sr", -0, GPR, 31, "r31", -0, GPR, 31, "pc", +{0, GPR, 25, "r25"}, +{0, GPR, 25, "sp"}, +{0, GPR, 26, "r26"}, +{0, GPR, 26, "lr"}, +{0, GPR, 27, "r27"}, +{0, GPR, 28, "r28"}, +{0, GPR, 29, "r29"}, +{0, GPR, 30, "r30"}, +{0, GPR, 30, "sr"}, +{0, GPR, 31, "r31"}, +{0, GPR, 31, "pc"}, /* Condition codes */ -0, CC, 0, ".eq", -0, CC, 1, ".ne", -0, CC, 2, ".cs", -0, CC, 2, ".lo", -0, CC, 3, ".cc", -0, CC, 3, ".hs", -0, CC, 4, ".mi", -0, CC, 5, ".pl", -0, CC, 6, ".vs", -0, CC, 7, ".vc", -0, CC, 8, ".hi", -0, CC, 9, ".ls", -0, CC, 10, ".ge", -0, CC, 11, ".lt", -0, CC, 12, ".gt", -0, CC, 13, ".le", -0, CC, 15, ".f", +{0, CC, 0, ".eq"}, +{0, CC, 1, ".ne"}, +{0, CC, 2, ".cs"}, +{0, CC, 2, ".lo"}, +{0, CC, 3, ".cc"}, +{0, CC, 3, ".hs"}, +{0, CC, 4, ".mi"}, +{0, CC, 5, ".pl"}, +{0, CC, 6, ".vs"}, +{0, CC, 7, ".vc"}, +{0, CC, 8, ".hi"}, +{0, CC, 9, ".ls"}, +{0, CC, 10, ".ge"}, +{0, CC, 11, ".lt"}, +{0, CC, 12, ".gt"}, +{0, CC, 13, ".le"}, +{0, CC, 15, ".f"}, /* Special instructions */ -0, OP, B16(00000000,00000001), "nop", -0, OP, B16(00000000,00001010), "rti", +{0, OP, B16(00000000,00000001), "nop"}, +{0, OP, B16(00000000,00001010), "rti"}, -0, OP_BRANCH, 0, "b", -0, OP_BRANCHLINK, 0, "bl", -0, OP_ADDCMPB, 0, "addcmpb", +{0, OP_BRANCH, 0, "b"}, +{0, OP_BRANCHLINK, 0, "bl"}, +{0, OP_ADDCMPB, 0, "addcmpb"}, -0, OP_ONELREG, B16(00000000,10000000), "tbb", -0, OP_ONELREG, B16(00000000,10100000), "tbs", +{0, OP_ONELREG, B16(00000000,10000000), "tbb"}, +{0, OP_ONELREG, B16(00000000,10100000), "tbs"}, -0, OP_ALU, B8(00000000), "mov", -0, OP_ALU, B8(00000001), "cmn", -0, OP_ALU, B8(00000010), "add", -0, OP_ALU, B8(00000011), "bic", -0, OP_ALU, B8(00000100), "mul", -0, OP_ALU, B8(00000101), "eor", -0, OP_ALU, B8(00000110), "sub", -0, OP_ALU, B8(00000111), "and", -0, OP_ALU, B8(00001000), "mvn", -0, OP_ALU, B8(00001001), "ror", -0, OP_ALU, B8(00001010), "cmp", -0, OP_ALU, B8(00001011), "rsb", -0, OP_ALU, B8(00001100), "btst", -0, OP_ALU, B8(00001101), "or", -0, OP_ALU, B8(00001110), "extu", -0, OP_ALU, B8(00001111), "max", -0, OP_ALU, B8(00010000), "bset", -0, OP_ALU, B8(00010001), "min", -0, OP_ALU, B8(00010010), "bclr", -0, OP_ALU, B8(00010011), "adds2", -0, OP_ALU, B8(00010100), "bchg", -0, OP_ALU, B8(00010101), "adds4", -0, OP_ALU, B8(00010110), "adds8", -0, OP_ALU, B8(00010111), "adds16", -0, OP_ALU, B8(00011000), "exts", -0, OP_ALU, B8(00011001), "neg", -0, OP_ALU, B8(00011010), "lsr", -0, OP_ALU, B8(00011011), "log2", -0, OP_ALU, B8(00011100), "lsl", -0, OP_ALU, B8(00011101), "brev", -0, OP_ALU, B8(00011110), "asr", -0, OP_ALU, B8(00011111), "abs", +{0, OP_ALU, B8(00000000), "mov"}, +{0, OP_ALU, B8(00000001), "cmn"}, +{0, OP_ALU, B8(00000010), "add"}, +{0, OP_ALU, B8(00000011), "bic"}, +{0, OP_ALU, B8(00000100), "mul"}, +{0, OP_ALU, B8(00000101), "eor"}, +{0, OP_ALU, B8(00000110), "sub"}, +{0, OP_ALU, B8(00000111), "and"}, +{0, OP_ALU, B8(00001000), "mvn"}, +{0, OP_ALU, B8(00001001), "ror"}, +{0, OP_ALU, B8(00001010), "cmp"}, +{0, OP_ALU, B8(00001011), "rsb"}, +{0, OP_ALU, B8(00001100), "btst"}, +{0, OP_ALU, B8(00001101), "or"}, +{0, OP_ALU, B8(00001110), "extu"}, +{0, OP_ALU, B8(00001111), "max"}, +{0, OP_ALU, B8(00010000), "bset"}, +{0, OP_ALU, B8(00010001), "min"}, +{0, OP_ALU, B8(00010010), "bclr"}, +{0, OP_ALU, B8(00010011), "adds2"}, +{0, OP_ALU, B8(00010100), "bchg"}, +{0, OP_ALU, B8(00010101), "adds4"}, +{0, OP_ALU, B8(00010110), "adds8"}, +{0, OP_ALU, B8(00010111), "adds16"}, +{0, OP_ALU, B8(00011000), "exts"}, +{0, OP_ALU, B8(00011001), "neg"}, +{0, OP_ALU, B8(00011010), "lsr"}, +{0, OP_ALU, B8(00011011), "log2"}, +{0, OP_ALU, B8(00011100), "lsl"}, +{0, OP_ALU, B8(00011101), "brev"}, +{0, OP_ALU, B8(00011110), "asr"}, +{0, OP_ALU, B8(00011111), "abs"}, -0, OP_MISC, B16(11001000,00000000), "fadd", -0, OP_MISC, B16(11001000,00100000), "fsub", -0, OP_MISC, B16(11001000,01000000), "fmul", -0, OP_MISC, B16(11001000,01100000), "fdiv", -0, OP_MISC, B16(11001000,10000000), "fcmp", -0, OP_MISC, B16(11001000,10100000), "fabs", -0, OP_MISC, B16(11001000,11000000), "frsb", -0, OP_MISC, B16(11001000,11100000), "fmax", -0, OP_MISC, B16(11001001,00000000), "frcp", -0, OP_MISC, B16(11001001,00100000), "frsqrt", -0, OP_MISC, B16(11001001,01000000), "fnmul", -0, OP_MISC, B16(11001001,01100000), "fmin", -0, OP_MISC, B16(11001001,10000000), "fld1", -0, OP_MISC, B16(11001001,10100000), "fld0", -0, OP_MISC, B16(11001001,11000000), "log2", -0, OP_MISC, B16(11001001,11100000), "exp2", -0, OP_MISC, B16(11000101,11100000), "adds256", +{0, OP_MISC, B16(11001000,00000000), "fadd"}, +{0, OP_MISC, B16(11001000,00100000), "fsub"}, +{0, OP_MISC, B16(11001000,01000000), "fmul"}, +{0, OP_MISC, B16(11001000,01100000), "fdiv"}, +{0, OP_MISC, B16(11001000,10000000), "fcmp"}, +{0, OP_MISC, B16(11001000,10100000), "fabs"}, +{0, OP_MISC, B16(11001000,11000000), "frsb"}, +{0, OP_MISC, B16(11001000,11100000), "fmax"}, +{0, OP_MISC, B16(11001001,00000000), "frcp"}, +{0, OP_MISC, B16(11001001,00100000), "frsqrt"}, +{0, OP_MISC, B16(11001001,01000000), "fnmul"}, +{0, OP_MISC, B16(11001001,01100000), "fmin"}, +{0, OP_MISC, B16(11001001,10000000), "fld1"}, +{0, OP_MISC, B16(11001001,10100000), "fld0"}, +{0, OP_MISC, B16(11001001,11000000), "log2"}, +{0, OP_MISC, B16(11001001,11100000), "exp2"}, +{0, OP_MISC, B16(11000101,11100000), "adds256"}, -0, OP_FLTCNV, B16(11001010,00000000), "ftrunc", -0, OP_FLTCNV, B16(11001010,00100000), "floor", -0, OP_FLTCNV, B16(11001010,01000000), "flts", -0, OP_FLTCNV, B16(11001010,01100000), "fltu", +{0, OP_FLTCNV, B16(11001010,00000000), "ftrunc"}, +{0, OP_FLTCNV, B16(11001010,00100000), "floor"}, +{0, OP_FLTCNV, B16(11001010,01000000), "flts"}, +{0, OP_FLTCNV, B16(11001010,01100000), "fltu"}, -0, OP_MISCL, B16(11000100,10000000), "divs", -0, OP_MISCL, B16(11000100,11100000), "divu", +{0, OP_MISCL, B16(11000100,10000000), "divs"}, +{0, OP_MISCL, B16(11000100,11100000), "divu"}, -0, OP_STACK, B16(00000010,10000000), "push", -0, OP_STACK, B16(00000010,00000000), "pop", +{0, OP_STACK, B16(00000010,10000000), "push"}, +{0, OP_STACK, B16(00000010,00000000), "pop"}, -0, OP_MEM, B8(00000000), "ld", -0, OP_MEM, B8(00000001), "st", -0, OP_MEM, B8(00000010), "ldh", -0, OP_MEM, B8(00000011), "sth", -0, OP_MEM, B8(00000100), "ldb", -0, OP_MEM, B8(00000101), "stb", -0, OP_MEM, B8(00000110), "ldhs", -0, OP_MEM, B8(00000111), "sths", +{0, OP_MEM, B8(00000000), "ld"}, +{0, OP_MEM, B8(00000001), "st"}, +{0, OP_MEM, B8(00000010), "ldh"}, +{0, OP_MEM, B8(00000011), "sth"}, +{0, OP_MEM, B8(00000100), "ldb"}, +{0, OP_MEM, B8(00000101), "stb"}, +{0, OP_MEM, B8(00000110), "ldhs"}, +{0, OP_MEM, B8(00000111), "sths"}, -0, OP_LEA, 0, "lea", +{0, OP_LEA, 0, "lea"}, diff --git a/mach/z80/as/mach3.c b/mach/z80/as/mach3.c index 528b36655..063a9fce6 100644 --- a/mach/z80/as/mach3.c +++ b/mach/z80/as/mach3.c @@ -8,95 +8,95 @@ * Zilog Z80 keywords */ -0, R8, B, "b", -0, R8, C, "c", -0, R8, D, "d", -0, R8, E, "e", -0, R8, H, "h", -0, R8, L, "l", -0, R8, F, "f", -0, R8, A, "a", -0, R8, I, "i", -0, R8, R, "r", -0, R16, BC, "bc", -0, R16, DE, "de", -0, R16, HL, "hl", -0, R16, SP, "sp", -0, R16, AF, "af", -0, R16, AF2, "af2", -0, R16, IX, "ix", -0, R16, IY, "iy", -0, CC, 0, "nz", -0, CC, 1, "z", -0, CC, 2, "nc", -0, CC, 4, "po", -0, CC, 5, "pe", -0, CC, 6, "p", -0, CC, 7, "m", -0, LDOP, 0, "ld", -0, PSHPOP, 0305, "push", -0, PSHPOP, 0301, "pop", -0, EXOP, 0343, "ex", -0, NOOPOP, 0331, "exx", -0, E_ED, 0240, "ldi", -0, E_ED, 0260, "ldir", -0, E_ED, 0250, "ldd", -0, E_ED, 0270, "lddr", -0, E_ED, 0241, "cpi", -0, E_ED, 0261, "cpir", -0, E_ED, 0251, "cpd", -0, E_ED, 0271, "cpdr", -0, ADDOP, 0200, "add", -0, ADCSBC, 0210, "adc", -0, ADCSBC, 0230, "sbc", -0, ARI8, 0220, "sub", -0, ARI8, 0240, "and", -0, ARI8, 0260, "or", -0, ARI8, 0250, "xor", -0, ARI8, 0270, "cp", -0, INCDEC, 04, "inc", -0, INCDEC, 05, "dec", -0, NOOPOP, 047, "daa", -0, NOOPOP, 057, "cpl", -0, E_ED, 0104, "neg", -0, NOOPOP, 077, "ccf", -0, NOOPOP, 067, "scf", -0, NOOPOP, 0, "nop", -0, NOOPOP, 0166, "halt", -0, NOOPOP, 0363, "di", -0, NOOPOP, 0373, "ei", -0, IMOP, 0106, "im", -0, NOOPOP, 07, "rlca", -0, NOOPOP, 027, "rla", -0, NOOPOP, 017, "rrca", -0, NOOPOP, 037, "rra", -0, ROTATE, 0, "rlc", -0, ROTATE, 020, "rl", -0, ROTATE, 010, "rrc", -0, ROTATE, 030, "rr", -0, ROTATE, 040, "sla", -0, ROTATE, 050, "sra", -0, ROTATE, 070, "srl", -0, E_ED, 0157, "rld", -0, E_ED, 0147, "rrd", -0, BITS, 0100, "bit", -0, BITS, 0200, "res", -0, BITS, 0300, "set", -0, JP, 0303, "jp", -0, JR, 030, "jr", -0, DJNZ, 020, "djnz", -0, CALL, 0315, "call", -0, RET, 0311, "ret", -0, E_ED, 0115, "reti", -0, E_ED, 0105, "retn", -0, RST, 0307, "rst", -0, IN, 0333, "in", -0, E_ED, 0242, "ini", -0, E_ED, 0262, "inir", -0, E_ED, 0252, "ind", -0, E_ED, 0272, "indr", -0, OUT, 0323, "out", -0, E_ED, 0243, "outi", -0, E_ED, 0263, "otir", -0, E_ED, 0253, "outd", -0, E_ED, 0273, "otdr", +{0, R8, B, "b"}, +{0, R8, C, "c"}, +{0, R8, D, "d"}, +{0, R8, E, "e"}, +{0, R8, H, "h"}, +{0, R8, L, "l"}, +{0, R8, F, "f"}, +{0, R8, A, "a"}, +{0, R8, I, "i"}, +{0, R8, R, "r"}, +{0, R16, BC, "bc"}, +{0, R16, DE, "de"}, +{0, R16, HL, "hl"}, +{0, R16, SP, "sp"}, +{0, R16, AF, "af"}, +{0, R16, AF2, "af2"}, +{0, R16, IX, "ix"}, +{0, R16, IY, "iy"}, +{0, CC, 0, "nz"}, +{0, CC, 1, "z"}, +{0, CC, 2, "nc"}, +{0, CC, 4, "po"}, +{0, CC, 5, "pe"}, +{0, CC, 6, "p"}, +{0, CC, 7, "m"}, +{0, LDOP, 0, "ld"}, +{0, PSHPOP, 0305, "push"}, +{0, PSHPOP, 0301, "pop"}, +{0, EXOP, 0343, "ex"}, +{0, NOOPOP, 0331, "exx"}, +{0, E_ED, 0240, "ldi"}, +{0, E_ED, 0260, "ldir"}, +{0, E_ED, 0250, "ldd"}, +{0, E_ED, 0270, "lddr"}, +{0, E_ED, 0241, "cpi"}, +{0, E_ED, 0261, "cpir"}, +{0, E_ED, 0251, "cpd"}, +{0, E_ED, 0271, "cpdr"}, +{0, ADDOP, 0200, "add"}, +{0, ADCSBC, 0210, "adc"}, +{0, ADCSBC, 0230, "sbc"}, +{0, ARI8, 0220, "sub"}, +{0, ARI8, 0240, "and"}, +{0, ARI8, 0260, "or"}, +{0, ARI8, 0250, "xor"}, +{0, ARI8, 0270, "cp"}, +{0, INCDEC, 04, "inc"}, +{0, INCDEC, 05, "dec"}, +{0, NOOPOP, 047, "daa"}, +{0, NOOPOP, 057, "cpl"}, +{0, E_ED, 0104, "neg"}, +{0, NOOPOP, 077, "ccf"}, +{0, NOOPOP, 067, "scf"}, +{0, NOOPOP, 0, "nop"}, +{0, NOOPOP, 0166, "halt"}, +{0, NOOPOP, 0363, "di"}, +{0, NOOPOP, 0373, "ei"}, +{0, IMOP, 0106, "im"}, +{0, NOOPOP, 07, "rlca"}, +{0, NOOPOP, 027, "rla"}, +{0, NOOPOP, 017, "rrca"}, +{0, NOOPOP, 037, "rra"}, +{0, ROTATE, 0, "rlc"}, +{0, ROTATE, 020, "rl"}, +{0, ROTATE, 010, "rrc"}, +{0, ROTATE, 030, "rr"}, +{0, ROTATE, 040, "sla"}, +{0, ROTATE, 050, "sra"}, +{0, ROTATE, 070, "srl"}, +{0, E_ED, 0157, "rld"}, +{0, E_ED, 0147, "rrd"}, +{0, BITS, 0100, "bit"}, +{0, BITS, 0200, "res"}, +{0, BITS, 0300, "set"}, +{0, JP, 0303, "jp"}, +{0, JR, 030, "jr"}, +{0, DJNZ, 020, "djnz"}, +{0, CALL, 0315, "call"}, +{0, RET, 0311, "ret"}, +{0, E_ED, 0115, "reti"}, +{0, E_ED, 0105, "retn"}, +{0, RST, 0307, "rst"}, +{0, IN, 0333, "in"}, +{0, E_ED, 0242, "ini"}, +{0, E_ED, 0262, "inir"}, +{0, E_ED, 0252, "ind"}, +{0, E_ED, 0272, "indr"}, +{0, OUT, 0323, "out"}, +{0, E_ED, 0243, "outi"}, +{0, E_ED, 0263, "otir"}, +{0, E_ED, 0253, "outd"}, +{0, E_ED, 0273, "otdr"}, diff --git a/mach/z8000/as/mach3.c b/mach/z8000/as/mach3.c index bba4a7ba9..34cac9a54 100644 --- a/mach/z8000/as/mach3.c +++ b/mach/z8000/as/mach3.c @@ -7,157 +7,157 @@ /* ** Zilog z8000 keywords */ -0, R8, 8, "RL0", -0, R8, 0, "RH0", -0, R8, 9, "RL1", -0, R8, 1, "RH1", -0, R8, 10, "RL2", -0, R8, 2, "RH2", -0, R8, 11, "RL3", -0, R8, 3, "RH3", -0, R8, 12, "RL4", -0, R8, 4, "RH4", -0, R8, 13, "RL5", -0, R8, 5, "RH5", -0, R8, 14, "RL6", -0, R8, 6, "RH6", -0, R8, 15, "RL7", -0, R8, 7, "RH7", +{0, R8, 8, "RL0"}, +{0, R8, 0, "RH0"}, +{0, R8, 9, "RL1"}, +{0, R8, 1, "RH1"}, +{0, R8, 10, "RL2"}, +{0, R8, 2, "RH2"}, +{0, R8, 11, "RL3"}, +{0, R8, 3, "RH3"}, +{0, R8, 12, "RL4"}, +{0, R8, 4, "RH4"}, +{0, R8, 13, "RL5"}, +{0, R8, 5, "RH5"}, +{0, R8, 14, "RL6"}, +{0, R8, 6, "RH6"}, +{0, R8, 15, "RL7"}, +{0, R8, 7, "RH7"}, /* Special format for some byte-registers. Not really available on ** the z8000 but designed to ease writing a z8000-backend-table. ** LR[0..7] are equivalent with RL[0..7]. */ -0, R8, 8, "LR0", -0, R8, 9, "LR1", -0, R8, 10, "LR2", -0, R8, 11, "LR3", -0, R8, 12, "LR4", -0, R8, 13, "LR5", -0, R8, 14, "LR6", -0, R8, 15, "LR7", -0, R16, 0, "R0", -0, R16, 1, "R1", -0, R16, 2, "R2", -0, R16, 3, "R3", -0, R16, 4, "R4", -0, R16, 5, "R5", -0, R16, 6, "R6", -0, R16, 7, "R7", -0, R16, 8, "R8", -0, R16, 9, "R9", -0, R16, 10, "R10", -0, R16, 11, "R11", -0, R16, 12, "R12", -0, R16, 13, "R13", -0, R16, 14, "R14", -0, R16, 15, "R15", -0, R32, 0, "RR0", -0, R32, 2, "RR2", -0, R32, 4, "RR4", -0, R32, 6, "RR6", -0, R32, 8, "RR8", -0, R32, 10, "RR10", -0, R32, 12, "RR12", -0, R32, 14, "RR14", -0, R64, 0, "RQ0", -0, R64, 4, "RQ4", -0, R64, 8, "RQ8", -0, R64, 12, "RQ12", -0, CC, 14, "NZ", -0, CC, 15, "NC", -0, CC, 13, "PL", -0, CC, 5, "MI", -0, CC, 14, "NE", -0, CC, 6, "EQ", -0, CC, 4, "OV", -0, CC, 12, "NOV", -0, CC, 4, "PE", -0, CC, 12, "PO", -0, CC, 9, "GE", -0, CC, 1, "LT", -0, CC, 10, "GT", -0, CC, 2, "LE", -0, CC, 15, "UGE", -0, CC, 7, "ULT", -0, CC, 11, "UGT", -0, CC, 3, "ULE", -0, FLAG, 0x80, "C", -0, FLAG, 0x40, "Z", -0, FLAG, 0x20, "S", -0, FLAG, 0x10, "P", -0, FLAG, 0x10, "V", -0, INTCB, 2, "VI", -0, INTCB, 1, "NVI", -0, CTLRFLAGS, 1, "FLAGS", -0, CTLR, 2, "FCW", -0, CTLR, 3, "REFRESH", -0, CTLR, 4, "PSAPSEG", -0, CTLR, 5, "PSAPOFF", -0, CTLR, 6, "NSPSEG", -0, CTLR, 7, "NSPOFF", -0, CTLR, 5, "PSAP", -0, CTLR, 7, "NSP", +{0, R8, 8, "LR0"}, +{0, R8, 9, "LR1"}, +{0, R8, 10, "LR2"}, +{0, R8, 11, "LR3"}, +{0, R8, 12, "LR4"}, +{0, R8, 13, "LR5"}, +{0, R8, 14, "LR6"}, +{0, R8, 15, "LR7"}, +{0, R16, 0, "R0"}, +{0, R16, 1, "R1"}, +{0, R16, 2, "R2"}, +{0, R16, 3, "R3"}, +{0, R16, 4, "R4"}, +{0, R16, 5, "R5"}, +{0, R16, 6, "R6"}, +{0, R16, 7, "R7"}, +{0, R16, 8, "R8"}, +{0, R16, 9, "R9"}, +{0, R16, 10, "R10"}, +{0, R16, 11, "R11"}, +{0, R16, 12, "R12"}, +{0, R16, 13, "R13"}, +{0, R16, 14, "R14"}, +{0, R16, 15, "R15"}, +{0, R32, 0, "RR0"}, +{0, R32, 2, "RR2"}, +{0, R32, 4, "RR4"}, +{0, R32, 6, "RR6"}, +{0, R32, 8, "RR8"}, +{0, R32, 10, "RR10"}, +{0, R32, 12, "RR12"}, +{0, R32, 14, "RR14"}, +{0, R64, 0, "RQ0"}, +{0, R64, 4, "RQ4"}, +{0, R64, 8, "RQ8"}, +{0, R64, 12, "RQ12"}, +{0, CC, 14, "NZ"}, +{0, CC, 15, "NC"}, +{0, CC, 13, "PL"}, +{0, CC, 5, "MI"}, +{0, CC, 14, "NE"}, +{0, CC, 6, "EQ"}, +{0, CC, 4, "OV"}, +{0, CC, 12, "NOV"}, +{0, CC, 4, "PE"}, +{0, CC, 12, "PO"}, +{0, CC, 9, "GE"}, +{0, CC, 1, "LT"}, +{0, CC, 10, "GT"}, +{0, CC, 2, "LE"}, +{0, CC, 15, "UGE"}, +{0, CC, 7, "ULT"}, +{0, CC, 11, "UGT"}, +{0, CC, 3, "ULE"}, +{0, FLAG, 0x80, "C"}, +{0, FLAG, 0x40, "Z"}, +{0, FLAG, 0x20, "S"}, +{0, FLAG, 0x10, "P"}, +{0, FLAG, 0x10, "V"}, +{0, INTCB, 2, "VI"}, +{0, INTCB, 1, "NVI"}, +{0, CTLRFLAGS, 1, "FLAGS"}, +{0, CTLR, 2, "FCW"}, +{0, CTLR, 3, "REFRESH"}, +{0, CTLR, 4, "PSAPSEG"}, +{0, CTLR, 5, "PSAPOFF"}, +{0, CTLR, 6, "NSPSEG"}, +{0, CTLR, 7, "NSPOFF"}, +{0, CTLR, 5, "PSAP"}, +{0, CTLR, 7, "NSP"}, /* TYPE_11a23 */ -0, F1_1F2_3, 0x1F00, "call", -0, F1_1F2_3, 0x3900, "ldps", +{0, F1_1F2_3, 0x1F00, "call"}, +{0, F1_1F2_3, 0x3900, "ldps"}, /* TYPE_11b23 */ -0, F1_1F2_3, 0x0D08, "clr", -0, F1_1F2_3, 0x0C08, "clrb", -0, F1_1F2_3, 0x0D00, "com", -0, F1_1F2_3, 0x0C00, "comb", -0, F1_1F2_3, 0x0D02, "neg", -0, F1_1F2_3, 0x0C02, "negb", -0, F1_1F2_3, 0x0D04, "test", -0, F1_1F2_3, 0x0C04, "testb", -0, F1_1F2_3, 0x1C08, "testl", -0, F1_1F2_3, 0x0D06, "tset", -0, F1_1F2_3, 0x0C06, "tsetb", +{0, F1_1F2_3, 0x0D08, "clr"}, +{0, F1_1F2_3, 0x0C08, "clrb"}, +{0, F1_1F2_3, 0x0D00, "com"}, +{0, F1_1F2_3, 0x0C00, "comb"}, +{0, F1_1F2_3, 0x0D02, "neg"}, +{0, F1_1F2_3, 0x0C02, "negb"}, +{0, F1_1F2_3, 0x0D04, "test"}, +{0, F1_1F2_3, 0x0C04, "testb"}, +{0, F1_1F2_3, 0x1C08, "testl"}, +{0, F1_1F2_3, 0x0D06, "tset"}, +{0, F1_1F2_3, 0x0C06, "tsetb"}, -0, F1_1a, 0xB000, "dab", -0, F1_1a, 0xB10A, "exts", -0, F1_1a, 0xB100, "extsb", -0, F1_1a, 0xB107, "extsl", +{0, F1_1a, 0xB000, "dab"}, +{0, F1_1a, 0xB10A, "exts"}, +{0, F1_1a, 0xB100, "extsb"}, +{0, F1_1a, 0xB107, "extsl"}, -0, F1_1b, 0xB300, "rl", -0, F1_1b, 0xB200, "rlb", -0, F1_1b, 0xB308, "rlc", -0, F1_1b, 0xB208, "rlcb", -0, F1_1b, 0xB304, "rr", -0, F1_1b, 0xB204, "rrb", -0, F1_1b, 0xB30C, "rrc", -0, F1_1b, 0xB20C, "rrcb", +{0, F1_1b, 0xB300, "rl"}, +{0, F1_1b, 0xB200, "rlb"}, +{0, F1_1b, 0xB308, "rlc"}, +{0, F1_1b, 0xB208, "rlcb"}, +{0, F1_1b, 0xB304, "rr"}, +{0, F1_1b, 0xB204, "rrb"}, +{0, F1_1b, 0xB30C, "rrc"}, +{0, F1_1b, 0xB20C, "rrcb"}, /* TYPE_12 */ -0, F1_2, 0x2B00, "dec", -0, F1_2, 0x2A00, "decb", -0, F1_2, 0x2900, "inc", -0, F1_2, 0x2800, "incb", -0, LDK, 0xBD00, "ldk", +{0, F1_2, 0x2B00, "dec"}, +{0, F1_2, 0x2A00, "decb"}, +{0, F1_2, 0x2900, "inc"}, +{0, F1_2, 0x2800, "incb"}, +{0, LDK, 0xBD00, "ldk"}, /* TYPE_1263 */ -0, F1_2F6_3, 0x2700, "bit", -0, F1_2F6_3, 0x2600, "bitb", -0, F1_2F6_3, 0x2300, "res", -0, F1_2F6_3, 0x2200, "resb", -0, F1_2F6_3, 0x2500, "set", -0, F1_2F6_3, 0x2400, "setb", +{0, F1_2F6_3, 0x2700, "bit"}, +{0, F1_2F6_3, 0x2600, "bitb"}, +{0, F1_2F6_3, 0x2300, "res"}, +{0, F1_2F6_3, 0x2200, "resb"}, +{0, F1_2F6_3, 0x2500, "set"}, +{0, F1_2F6_3, 0x2400, "setb"}, /* TYPE_jp */ -0, JP, 0x1E00, "jp", +{0, JP, 0x1E00, "jp"}, -0, TCC, 0xAF00, "tcc", -0, TCC, 0xAE00, "tccb", +{0, TCC, 0xAF00, "tcc"}, +{0, TCC, 0xAE00, "tccb"}, /* TYPE_21a */ -0, F2_1, 0x2D00, "ex", -0, F2_1, 0x2C00, "exb", +{0, F2_1, 0x2D00, "ex"}, +{0, F2_1, 0x2C00, "exb"}, /* TYPE_21b */ -0, F2_1, 0x3500, "adc", -0, F2_1, 0x3400, "adcb", -0, F2_1, 0x3E00, "rldb", -0, F2_1, 0x3C00, "rrdb", -0, F2_1, 0x3700, "sbc", -0, F2_1, 0x3600, "sbcb", +{0, F2_1, 0x3500, "adc"}, +{0, F2_1, 0x3400, "adcb"}, +{0, F2_1, 0x3E00, "rldb"}, +{0, F2_1, 0x3C00, "rrdb"}, +{0, F2_1, 0x3700, "sbc"}, +{0, F2_1, 0x3600, "sbcb"}, /* TYPE_2151. ** Depending on their operands the cp-instructions might ** have an opcode of 0x201 more then listed below. This is @@ -165,160 +165,160 @@ ** The difference in opcode between byte-,word- and long- ** instructions of the F2_1F5_1 group is as follows: ** If bit 8 is on it is a word instruction; If it is not a - ** word instruction and bit 12 is on it is a long instruction, + ** word instruction and bit 12 is on it is a long instruction}, ** else it is a byte instruction. This information is used ** when one of the operands is of type IM. */ -0, F2_1F5_1, 0x0100, "add", -0, F2_1F5_1, 0x0000, "addb", -0, F2_1F5_1, 0x1600, "addl", -0, F2_1F5_1, 0x0700, "and", -0, F2_1F5_1, 0x0600, "andb", -0, F2_1F5_1, 0x1B00, "div", -0, F2_1F5_1, 0x1A00, "divl", -0, F2_1F5_1, 0x1900, "mult", -0, F2_1F5_1, 0x1800, "multl", -0, F2_1F5_1, 0x0500, "or", -0, F2_1F5_1, 0x0400, "orb", -0, F2_1F5_1, 0x0300, "sub", -0, F2_1F5_1, 0x0200, "subb", -0, F2_1F5_1, 0x1200, "subl", -0, F2_1F5_1, 0x0900, "xor", -0, F2_1F5_1, 0x0800, "xorb", -0, F2_1F5_1, 0x0B00, "cp", -0, F2_1F5_1, 0x0A00, "cpb", -0, F2_1F5_1, 0x1000, "cpl", +{0, F2_1F5_1, 0x0100, "add"}, +{0, F2_1F5_1, 0x0000, "addb"}, +{0, F2_1F5_1, 0x1600, "addl"}, +{0, F2_1F5_1, 0x0700, "and"}, +{0, F2_1F5_1, 0x0600, "andb"}, +{0, F2_1F5_1, 0x1B00, "div"}, +{0, F2_1F5_1, 0x1A00, "divl"}, +{0, F2_1F5_1, 0x1900, "mult"}, +{0, F2_1F5_1, 0x1800, "multl"}, +{0, F2_1F5_1, 0x0500, "or"}, +{0, F2_1F5_1, 0x0400, "orb"}, +{0, F2_1F5_1, 0x0300, "sub"}, +{0, F2_1F5_1, 0x0200, "subb"}, +{0, F2_1F5_1, 0x1200, "subl"}, +{0, F2_1F5_1, 0x0900, "xor"}, +{0, F2_1F5_1, 0x0800, "xorb"}, +{0, F2_1F5_1, 0x0B00, "cp"}, +{0, F2_1F5_1, 0x0A00, "cpb"}, +{0, F2_1F5_1, 0x1000, "cpl"}, -0, LDA, 0, "lda", +{0, LDA, 0, "lda"}, /* TYPE_pop */ -0, POP, 0x1700, "pop", -0, POP, 0x1500, "popl", +{0, POP, 0x1700, "pop"}, +{0, POP, 0x1500, "popl"}, /* TYPE_push */ -0, PUSH, 0x1300, "push", -0, PUSH, 0x1100, "pushl", +{0, PUSH, 0x1300, "push"}, +{0, PUSH, 0x1100, "pushl"}, /* TYPE_ld */ -0, LD, 0x0100, "ld", -0, LD, 0, "ldb", -0, LDL, 0, "ldl", +{0, LD, 0x0100, "ld"}, +{0, LD, 0, "ldb"}, +{0, LDL, 0, "ldl"}, -0, DJNZ, 0xF080, "djnz", -0, DJNZ, 0xF000, "dbjnz", -0, JR, 0xE000, "jr", -0, CALR, 0xD000, "calr", +{0, DJNZ, 0xF080, "djnz"}, +{0, DJNZ, 0xF000, "dbjnz"}, +{0, JR, 0xE000, "jr"}, +{0, CALR, 0xD000, "calr"}, /* Depending on their operands the LDR-instructions might ** have an opcode of 0x200 more then listed below. This is ** or-ed in at the appropriate place. */ -0, LDR, 0x3100, "ldr", -0, LDR, 0x3000, "ldrb", -0, LDR, 0x3500, "ldrl", +{0, LDR, 0x3100, "ldr"}, +{0, LDR, 0x3000, "ldrb"}, +{0, LDR, 0x3500, "ldrl"}, -0, LDAR, 0x3400, "ldar", +{0, LDAR, 0x3400, "ldar"}, -0, F5_1L, 0xB309, "sla", -0, F5_1L, 0xB209, "slab", -0, F5_1L, 0xB30D, "slal", -0, F5_1L, 0xB301, "sll", -0, F5_1L, 0xB201, "sllb", -0, F5_1L, 0xB305, "slll", -0, F5_1R, 0xB309, "sra", -0, F5_1R, 0xB209, "srab", -0, F5_1R, 0xB30D, "sral", -0, F5_1R, 0xB301, "srl", -0, F5_1R, 0xB201, "srlb", -0, F5_1R, 0xB305, "srll", +{0, F5_1L, 0xB309, "sla"}, +{0, F5_1L, 0xB209, "slab"}, +{0, F5_1L, 0xB30D, "slal"}, +{0, F5_1L, 0xB301, "sll"}, +{0, F5_1L, 0xB201, "sllb"}, +{0, F5_1L, 0xB305, "slll"}, +{0, F5_1R, 0xB309, "sra"}, +{0, F5_1R, 0xB209, "srab"}, +{0, F5_1R, 0xB30D, "sral"}, +{0, F5_1R, 0xB301, "srl"}, +{0, F5_1R, 0xB201, "srlb"}, +{0, F5_1R, 0xB305, "srll"}, /* Depending on its operands the LDM-instruction might have ** an opcode of 8 more then listed below. This is added at the ** appropriate place. ** TYPE_ldm */ -0, LDM, 0x1C01, "ldm", +{0, LDM, 0x1C01, "ldm"}, /* For the F6.4 instructions below the yylval-column contains ** the opcode for the instruction. However the third hexa-digit ** should be 0; But this is the opcode which must be put into ** the second word of the instruction! */ -0, F6_4, 0x3B88, "ind", -0, F6_4, 0x3A88, "indb", -0, F6_4, 0x3B08, "indr", -0, F6_4, 0x3A08, "indrb", -0, F6_4, 0x3B80, "ini", -0, F6_4, 0x3A80, "inib", -0, F6_4, 0x3B00, "inir", -0, F6_4, 0x3A00, "inirb", -0, F6_4, 0xBB89, "ldd", -0, F6_4, 0xBA89, "lddb", -0, F6_4, 0xBB09, "lddr", -0, F6_4, 0xBA09, "lddrb", -0, F6_4, 0xBB81, "ldi", -0, F6_4, 0xBA81, "ldib", -0, F6_4, 0xBB01, "ldir", -0, F6_4, 0xBA01, "ldirb", -0, F6_4, 0x3B0A, "otdr", -0, F6_4, 0x3A0A, "otdrb", -0, F6_4, 0x3B02, "otir", -0, F6_4, 0x3A02, "otirb", -0, F6_4, 0x3B8A, "outd", -0, F6_4, 0x3A8A, "outdb", -0, F6_4, 0x3B82, "outi", -0, F6_4, 0x3A82, "outib", -0, F6_4, 0x3B89, "sind", -0, F6_4, 0x3A89, "sindb", -0, F6_4, 0x3B09, "sindr", -0, F6_4, 0x3A09, "sindrb", -0, F6_4, 0x3B81, "sini", -0, F6_4, 0x3A81, "sinib", -0, F6_4, 0x3B01, "sinir", -0, F6_4, 0x3A01, "sinirb", -0, F6_4, 0x3B0B, "sotdr", -0, F6_4, 0x3A0B, "sotdrb", -0, F6_4, 0x3B03, "sotir", -0, F6_4, 0x3A03, "sotirb", -0, F6_4, 0x3B8B, "soutd", -0, F6_4, 0x3A8B, "soutdb", -0, F6_4, 0x3B83, "souti", -0, F6_4, 0x3A83, "soutib", -0, F6_4, 0xB808, "trdb", -0, F6_4, 0xB80C, "trdrb", -0, F6_4, 0xB800, "trib", -0, F6_4, 0xB804, "trirb", -0, F6_4, 0xB80A, "trtdb", -0, F6_4, 0xB8EE, "trtdrb", -0, F6_4, 0xB802, "trtib", -0, F6_4, 0xB8E6, "trtirb", +{0, F6_4, 0x3B88, "ind"}, +{0, F6_4, 0x3A88, "indb"}, +{0, F6_4, 0x3B08, "indr"}, +{0, F6_4, 0x3A08, "indrb"}, +{0, F6_4, 0x3B80, "ini"}, +{0, F6_4, 0x3A80, "inib"}, +{0, F6_4, 0x3B00, "inir"}, +{0, F6_4, 0x3A00, "inirb"}, +{0, F6_4, 0xBB89, "ldd"}, +{0, F6_4, 0xBA89, "lddb"}, +{0, F6_4, 0xBB09, "lddr"}, +{0, F6_4, 0xBA09, "lddrb"}, +{0, F6_4, 0xBB81, "ldi"}, +{0, F6_4, 0xBA81, "ldib"}, +{0, F6_4, 0xBB01, "ldir"}, +{0, F6_4, 0xBA01, "ldirb"}, +{0, F6_4, 0x3B0A, "otdr"}, +{0, F6_4, 0x3A0A, "otdrb"}, +{0, F6_4, 0x3B02, "otir"}, +{0, F6_4, 0x3A02, "otirb"}, +{0, F6_4, 0x3B8A, "outd"}, +{0, F6_4, 0x3A8A, "outdb"}, +{0, F6_4, 0x3B82, "outi"}, +{0, F6_4, 0x3A82, "outib"}, +{0, F6_4, 0x3B89, "sind"}, +{0, F6_4, 0x3A89, "sindb"}, +{0, F6_4, 0x3B09, "sindr"}, +{0, F6_4, 0x3A09, "sindrb"}, +{0, F6_4, 0x3B81, "sini"}, +{0, F6_4, 0x3A81, "sinib"}, +{0, F6_4, 0x3B01, "sinir"}, +{0, F6_4, 0x3A01, "sinirb"}, +{0, F6_4, 0x3B0B, "sotdr"}, +{0, F6_4, 0x3A0B, "sotdrb"}, +{0, F6_4, 0x3B03, "sotir"}, +{0, F6_4, 0x3A03, "sotirb"}, +{0, F6_4, 0x3B8B, "soutd"}, +{0, F6_4, 0x3A8B, "soutdb"}, +{0, F6_4, 0x3B83, "souti"}, +{0, F6_4, 0x3A83, "soutib"}, +{0, F6_4, 0xB808, "trdb"}, +{0, F6_4, 0xB80C, "trdrb"}, +{0, F6_4, 0xB800, "trib"}, +{0, F6_4, 0xB804, "trirb"}, +{0, F6_4, 0xB80A, "trtdb"}, +{0, F6_4, 0xB8EE, "trtdrb"}, +{0, F6_4, 0xB802, "trtib"}, +{0, F6_4, 0xB8E6, "trtirb"}, /* From the F6.5 instructions below the last eight ('string'- ** instructions) want an 'ir' as operand; The others want a 'r'. ** In the opcode for the string-instructions bit 1 is on, which ** indicates the difference. */ -0, F6_5, 0xBB08, "cpd", -0, F6_5, 0xBA08, "cpdb", -0, F6_5, 0xBB0C, "cpdr", -0, F6_5, 0xBA0C, "cpdrb", -0, F6_5, 0xBB00, "cpi", -0, F6_5, 0xBA00, "cpib", -0, F6_5, 0xBB04, "cpir", -0, F6_5, 0xBA04, "cpirb", -0, F6_5, 0xBB0A, "cpsd", -0, F6_5, 0xBA0A, "cpsdb", -0, F6_5, 0xBB0E, "cpsdr", -0, F6_5, 0xBA0E, "cpsdrb", -0, F6_5, 0xBB02, "cpsi", -0, F6_5, 0xBA02, "cpsib", -0, F6_5, 0xBB06, "cpsir", -0, F6_5, 0xBA06, "cpsirb", +{0, F6_5, 0xBB08, "cpd"}, +{0, F6_5, 0xBA08, "cpdb"}, +{0, F6_5, 0xBB0C, "cpdr"}, +{0, F6_5, 0xBA0C, "cpdrb"}, +{0, F6_5, 0xBB00, "cpi"}, +{0, F6_5, 0xBA00, "cpib"}, +{0, F6_5, 0xBB04, "cpir"}, +{0, F6_5, 0xBA04, "cpirb"}, +{0, F6_5, 0xBB0A, "cpsd"}, +{0, F6_5, 0xBA0A, "cpsdb"}, +{0, F6_5, 0xBB0E, "cpsdr"}, +{0, F6_5, 0xBA0E, "cpsdrb"}, +{0, F6_5, 0xBB02, "cpsi"}, +{0, F6_5, 0xBA02, "cpsib"}, +{0, F6_5, 0xBB06, "cpsir"}, +{0, F6_5, 0xBA06, "cpsirb"}, -0, F6_6, 0xB30B, "sda", -0, F6_6, 0xB20B, "sdab", -0, F6_6, 0xB30F, "sdal", -0, F6_6, 0xB303, "sdl", -0, F6_6, 0xB203, "sdlb", -0, F6_6, 0xB307, "sdll", +{0, F6_6, 0xB30B, "sda"}, +{0, F6_6, 0xB20B, "sdab"}, +{0, F6_6, 0xB30F, "sdal"}, +{0, F6_6, 0xB303, "sdl"}, +{0, F6_6, 0xB203, "sdlb"}, +{0, F6_6, 0xB307, "sdll"}, /* The instructions in\b and out\b have two different opcodes ** depending on their operands (...). Therefore the opcodes @@ -332,38 +332,38 @@ ** as operand. In their opcode bit 0 is on, which indicates ** the difference with the other instructions of this group. */ -0, IN, 0x3100, "in", -0, IN, 0x3000, "inb", -0, IN, 0x3B05, "sin", -0, IN, 0x3A05, "sinb", -0, OUT, 0x3100, "out", -0, OUT, 0x3000, "outb", -0, OUT, 0x3B07, "sout", -0, OUT, 0x3A07, "soutb", +{0, IN, 0x3100, "in"}, +{0, IN, 0x3000, "inb"}, +{0, IN, 0x3B05, "sin"}, +{0, IN, 0x3A05, "sinb"}, +{0, OUT, 0x3100, "out"}, +{0, OUT, 0x3000, "outb"}, +{0, OUT, 0x3B07, "sout"}, +{0, OUT, 0x3A07, "soutb"}, /* Depending on their operands the LDCTL-instructions might ** have an opcode of 8 more then listed below. This is or-ed ** in at the appropriate place. */ -0, LDCTL, 0x7D00, "ldctl", -0, LDCTLB, 0x8C00, "ldctlb", -0, MREQ, 0x7B0D, "mreq", +{0, LDCTL, 0x7D00, "ldctl"}, +{0, LDCTLB, 0x8C00, "ldctlb"}, +{0, MREQ, 0x7B0D, "mreq"}, -0, F9_1, 0x8D05, "comflg", -0, F9_1, 0x8D03, "resflg", -0, F9_1, 0x8D01, "setflg", +{0, F9_1, 0x8D05, "comflg"}, +{0, F9_1, 0x8D03, "resflg"}, +{0, F9_1, 0x8D01, "setflg"}, -0, F9_2, 0x7C00, "di", -0, F9_2, 0x7C04, "ei", +{0, F9_2, 0x7C00, "di"}, +{0, F9_2, 0x7C04, "ei"}, -0, F9_3, 0x7A00, "halt", -0, F9_3, 0x7B00, "iret", -0, F9_3, 0x7B0A, "mbit", -0, F9_3, 0x7B09, "mres", -0, F9_3, 0x7B08, "mset", -0, F9_3, 0x8D07, "nop", +{0, F9_3, 0x7A00, "halt"}, +{0, F9_3, 0x7B00, "iret"}, +{0, F9_3, 0x7B0A, "mbit"}, +{0, F9_3, 0x7B09, "mres"}, +{0, F9_3, 0x7B08, "mset"}, +{0, F9_3, 0x8D07, "nop"}, /* Rest of the opcode-0x200 is or-ed in at the appropriate place */ -0, RET, 0x9E00, "ret", -0, SC, 0x7F00, "sc", +{0, RET, 0x9E00, "ret"}, +{0, SC, 0x7F00, "sc"},