fix: sometimes the index mode was used in the wrong way

This commit is contained in:
ceriel 1987-07-08 16:36:45 +00:00
parent 466637933a
commit 9d66bc3258

View file

@ -180,6 +180,8 @@ adispldefind8 = {REGISTER ireg,reg; STRING ind;} 4 cost=(3,13)
TOKENEXPRESSIONS:
CONST = CONST1 + CONST2 + CONST4
ind2 = extind2 + displind2 + extdefind2 + displdefind2
ind4 = extind4 + displind4 + extdefind4 + displdefind4
Xsource1 = regdef1 + displ1 + displdef1 +
EXTERNAL1 + reldef1 + CONST1 + LOCAL1
+ displind1 + extdefind1 + displdefind1
@ -188,15 +190,13 @@ source1 = Xsource1
+ reginc1 + regdec1
#endif REGVARS
Xsource2 = regdef2 + displ2 + displdef2 +
EXTERNAL2 + reldef2 + CONST2 + LOCAL2
+ extind2 + displind2 + extdefind2 + displdefind2
EXTERNAL2 + reldef2 + CONST2 + LOCAL2 + ind2
source2 = Xsource2
#ifdef REGVARS
+ reginc2 + regdec2
#endif REGVARS
Xsource4 = REG + regdef4 + displ4 + displdef4 + LocaLBase +
EXTERNAL4 + reldef4 + CONST + DOUBLE + LOCAL4 + FCONST4
+ extind4 + displind4 + extdefind4 + displdefind4
EXTERNAL4 + reldef4 + CONST + DOUBLE + LOCAL4 + FCONST4 + ind4
source4 = Xsource4
#ifdef REGVARS
+ RREG + reginc4 + regdec4
@ -211,16 +211,14 @@ source8 = Xsource8
#ifdef REGVARS
+ reginc8 + regdec8
#endif REGVARS
source1or2 = source1 + source2
source1or2or4 = source1or2 + source4
source2or4 = source2 + source4
source1or2 = source1 + source2 - ind2
source1or2or4 = source1or2 + source4 - (ind2 + ind4)
source2or4 = source2 + source4 - ind4
nonexist1 = adispl + ADDR_EXTERNAL + ADDR_LOCAL
aextind = aextind2 + aextind4 + aextind8
adisplind = adisplind1 + adisplind2 + adisplind4 + adisplind8
aextdefind = aextdefind1 + aextdefind2 + aextdefind4 + aextdefind8
adispldefind = adispldefind1 + adispldefind2 + adispldefind4 + adispldefind8
ind2 = extind2 + displind2 + extdefind2 + displdefind2
ind4 = extind4 + displind4 + extdefind4 + displdefind4
aind1 = adisplind1 + aextdefind1 + adispldefind1
aind2 = aextind2 + adisplind2 + aextdefind2 + adispldefind2
aind4 = aextind4 + adisplind4 + aextdefind4 + adispldefind4
@ -258,7 +256,7 @@ reg8 = QREG
#endif REGVARS
sreg4 = REG * SCRATCH
sreg8 = QREG * SCRATCH
bigsource4 = source1or2or4 + nonexist
bigsource4 = source1or2or4 + nonexist + ind2 + ind4
bigsource8 = source8
all = bigsource4 + bigsource8
scr = ALL - (EXTERNALS + LOCALS + ADDR_LOCAL + ADDR_EXTERNAL + CONST
@ -1023,57 +1021,57 @@ ngi !defined($1) | source4 |
remove(ALL)
move(%[1],R0)
"jsb\t.ngi" | | |
sli $1==4 | source1or2or4 source1or2or4 |
sli $1==4 | source1or2or4 source4 |
allocate(%[1],%[2],REG)
"ashl\t%[1],%[2],%[a]"
setcc(%[a]) | %[a] | | (4,4)+%[1]+%[2]
#ifdef REGVARS
sli stl $1==4 && inreg($2)==2
| source4 source4 |
| source1or2or4 source4 |
remove(regvar($2))
"ashl\t%[1],%[2],%(regvar($2)%)"
erase(regvar($2))
setcc(regvar($2)) | | |
#endif REGVARS
sli stl $1==4 && $2<0
| source4 source4 |
| source1or2or4 source4 |
remove(displaced)
remove(LOCALS,(%[num] <= $2+3 && %[num]+%[size] > $2))
"ashl\t%[1],%[2],$2(fp)"
setcc({LOCAL4,LB,$2,4}) | | |
sli stl $1==4 && $2>=0
| source4 source4 |
| source1or2or4 source4 |
remove(displaced)
remove(LOCALS,(%[num] <= $2+3 && %[num]+%[size] > $2))
"ashl\t%[1],%[2],$2(ap)"
setcc({LOCAL4,AP,$2,4}) | | |
#ifdef REGVARS
sli sil $1==4 && inreg($2)==2
| source4 source4 |
| source1or2or4 source4 |
REMEXTANDLOC
"ashl\t%[1],%[2],(%(regvar($2)%))"
setcc({regdef4,regvar($2)}) | | |
sli lol stf $1==4 && inreg($2)==2
| source4 source4 |
| source1or2or4 source4 |
REMEXTANDLOC
"ashl\t%[1],%[2],$3(%(regvar($2)%))"
setcc({displ4,regvar($2),tostring($3)}) | | |
#endif REGVARS
sli sil $1==4 && $2<0
| source4 source4 |
| source1or2or4 source4 |
REMEXTANDLOC
"ashl\t%[1],%[2],*$2(fp)"
setcc({displdef4,LB,tostring($2)}) | | |
sli sil $1==4 && $2>=0
| source4 source4 |
| source1or2or4 source4 |
REMEXTANDLOC
"ashl\t%[1],%[2],*$2(ap)"
setcc({displdef4,AP,tostring($2)}) | | |
sli ste $1==4 | source4 source4 |
sli ste $1==4 | source1or2or4 source4 |
remove(externals)
"ashl\t%[1],%[2],$2"
setcc({EXTERNAL4,$2}) | | | (8,10)+%[1]+%[2]
sli !defined($1) | source4 |
sli !defined($1) | source1or2or4 |
remove(ALL)
move(%[1],R0)
"jsb\t.sli"
@ -1770,12 +1768,12 @@ adp dup sil adp $1==(0-$4) && $2==4
adp dup loe sti adp $1==(0-$5) && $2==4 && $4==4
| reg4 | | %[1] %[1] | adp $1 loe $3 sti 4 |
dup adp lol sti $1==4 && $4==4
| bigsource4 |
| bigsource4-regch4 |
allocate(REG=%[1])
| %[a] %[1] {CONST4,$2}
| adi 4 lol $3 sti 4 |
dup adp loe sti $1==4 && $4==4
| bigsource4 |
| bigsource4-regch4 |
allocate(REG=%[1])
| %[a] %[1] {CONST4,$2}
| adi 4 loe $3 sti 4 |
@ -2111,10 +2109,6 @@ cuu | STACK |
ciu | | | | cuu |
cui | STACK |
"jsb\t.cui" | | |
loc loc cii $1==1 && $2==2 | source1or2or4 |
allocate(%[1],REG)
"cvtbw\t%[1],%[a]"
setcc(%[a]) | %[a] | |
#ifdef REGVARS
loc loc cii stl $1==1 && $2==4 && inreg($4)==2
| source1or2or4 |
@ -3222,7 +3216,7 @@ tlt | source4 |
#endif
erase(%[a])
setcc(%[a]) | %[a] | |
... | NC source1or2 | | {CONST1,0} | |
... | NC source1or2-regch4 | | {CONST1,0} | |
tlt and $2==4 | source4 sreg4 |
test(%[1])
#ifdef LOCLABS
@ -3292,7 +3286,7 @@ tge | source4 |
#endif
erase(%[a])
setcc(%[a]) | %[a] | |
... | NC source1or2 | | {CONST1,1} | |
... | NC source1or2-regch4 | | {CONST1,1} | |
tge and $2==4 | source4 sreg4 |
test(%[1])
#ifdef LOCLABS
@ -4418,8 +4412,8 @@ dus !defined($1) | source4 |
move(%[1],R0)
"jsb\t.dus"
erase(R0) | | |
exg $1==4 | bigsource4-source4+Xsource4 bigsource4-source4+Xsource4 | | %[1] %[2] | |
exg $1==8 | bigsource8-source8+Xsource8 bigsource8-source8+Xsource8 | | %[1] %[2] | |
exg $1==4 | bigsource4-regch4 bigsource4-regch4 | | %[1] %[2] | |
exg $1==8 | bigsource8-regch8 bigsource8-regch8 | | %[1] %[2] | |
exg defined($1) | STACK |
move({CONST4,$1},R0)
"jsb\t.exg"