Enable the Hall check again, and get powerpc to pass it.
Upon enabling the check, mach/powerpc/ncg/table fails to build as ncgg
gives many errors of "Previous rule impossible on empty stack". David
Given reported this problem in 2013:
https://sourceforge.net/p/tack/mailman/message/30814694/
Commit c93cb69 commented out the error in util/ncgg/cgg.y to disable
the Hall check. This commit enables it again. In ncgg, the Hall
check is checking that a rule is possible with an empty fake stack.
It would be possible if ncg can coerce the values from the real stack
to the fake stack. The powerpc table defined coercions from STACK to
{FS, %a} and {FD, %a}, but the Hall check didn't understand the
coercions and rejected each rule "with FS" or "with FD".
This commit removes the FS and FD tokens and adds a new group of FSREG
registers for single-precision floats, while keeping FREG registers
for double precision. The registers overlap, with each FSREG
containing one FREG, because it is the same register in PowerPC
hardware. FS tokens become FSREG registers and FD tokens become FREG
registers. The Hall check understands the coercions from STACK to
FSREG and FREG. The idea to define separate but overlapping registers
comes from the PDP-11 table (mach/pdp/ncg/table).
This commit also removes F0 from the FREG group. This is my attempt
to keep F0 off the fake stack, because one of the stacking rules uses
F0 as a scratch register (FSCRATCH).
This commit is contained in:
George Koehler
parent
9ec2918e14
commit
9db305b338
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@ -44,6 +44,7 @@ PROPERTIES
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REG /* any allocatable GPR */
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FPR /* any FPR */
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FREG /* any allocatable FPR */
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FSREG /* any allocatable single-precision FPR */
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SPR /* any SPR */
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CR /* any CR */
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@ -127,7 +128,40 @@ REGISTERS
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F3("f3") : FPR, FREG, FPR3.
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F2("f2") : FPR, FREG, FPR2.
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F1("f1") : FPR, FREG, FPR1.
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F0("f0") : FPR, FREG, FPR0.
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F0("f0") : FPR, FPR0.
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FS31("f31")=F31 : FSREG.
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FS30("f30")=F30 : FSREG.
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FS29("f29")=F29 : FSREG.
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FS28("f28")=F28 : FSREG.
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FS27("f27")=F27 : FSREG.
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FS26("f26")=F26 : FSREG.
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FS25("f25")=F25 : FSREG.
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FS24("f24")=F24 : FSREG.
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FS23("f23")=F23 : FSREG.
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FS22("f22")=F22 : FSREG.
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FS21("f21")=F21 : FSREG.
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FS20("f20")=F20 : FSREG.
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FS19("f19")=F19 : FSREG.
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FS18("f18")=F18 : FSREG.
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FS17("f17")=F17 : FSREG.
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FS16("f16")=F16 : FSREG.
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FS15("f15")=F15 : FSREG.
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FS14("f14")=F14 : FSREG.
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FS13("f13")=F13 : FSREG.
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FS12("f12")=F12 : FSREG.
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FS11("f11")=F11 : FSREG.
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FS10("f10")=F10 : FSREG.
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FS9("f9")=F9 : FSREG.
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FS8("f8")=F8 : FSREG.
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FS7("f7")=F7 : FSREG.
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FS6("f6")=F6 : FSREG.
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FS5("f5")=F5 : FSREG.
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FS4("f4")=F4 : FSREG.
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FS3("f3")=F3 : FSREG.
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FS2("f2")=F2 : FSREG.
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FS1("f1")=F1 : FSREG.
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/* FS0("f0")=F0 */
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LR("lr") : SPR.
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CTR("ctr") : SPR.
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@ -190,11 +224,6 @@ TOKENS
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XOR_RR = { GPR reg1; GPR reg2; } 4.
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XOR_RC = { GPR reg; INT val; } 4.
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/* Floats */
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FD = { FPR reg; } 8 reg.
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FS = { FPR reg; } 4 reg.
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/* Comments */
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LABELI = { ADDR msg; INT num; } 4 msg " " num.
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@ -250,27 +279,29 @@ INSTRUCTIONS
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eqv GPRI:wo, GPRI:ro, GPRI:ro.
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extsb GPRI:wo, GPRI:ro.
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extsh GPRI:wo, GPRI:ro.
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fadd FD:wo, FD:ro, FD:ro.
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fadds FS:wo, FS:ro, FS:ro.
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fcmpo CR:wo, FD:ro, FD:ro.
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fdiv FD:wo, FD:ro, FD:ro.
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fdivs FS:wo, FS:ro, FS:ro.
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fneg FS+FD:wo, FS+FD:ro.
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fmul FD:wo, FD:ro, FD:ro.
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fmuls FS:wo, FS:ro, FS:ro.
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frsp FS:wo, FD:ro.
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fsub FD:wo, FD:ro, FD:ro.
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fsubs FS:wo, FS:ro, FS:ro.
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fmr FS+FD:wo, FS+FD:ro.
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fadd FREG:wo, FREG:ro, FREG:ro.
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fadds FSREG:wo, FSREG:ro, FSREG:ro.
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fcmpo CR:wo, FPR:ro, FPR:ro.
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fdiv FREG:wo, FREG:ro, FREG:ro.
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fdivs FSREG:wo, FSREG:ro, FSREG:ro.
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fneg FREG:wo, FREG:ro.
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fneg FSREG:wo, FSREG:ro.
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fmul FREG:wo, FREG:ro, FREG:ro.
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fmuls FSREG:wo, FSREG:ro, FSREG:ro.
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frsp FSREG:wo, FREG:ro.
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fsub FREG:wo, FREG:ro, FREG:ro.
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fsubs FSREG:wo, FSREG:ro, FSREG:ro.
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fmr FPR:wo, FPR:ro.
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fmr FSREG:wo, FSREG:ro.
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la GPRI:wo, LABEL:ro.
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lbzx GPRI:wo, GPR:ro, GPR:ro.
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lbz GPRI:wo, GPRINDIRECT+GPRINDIRECTLO:ro.
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lfd FD:wo, GPRINDIRECT+GPRINDIRECTLO:ro.
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lfdu FD:wo, GPRINDIRECT+GPRINDIRECTLO:ro.
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lfdx FD:wo, GPR:ro, GPR:ro.
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lfs FS:wo, GPRINDIRECT+GPRINDIRECTLO:ro.
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lfsu FS:wo, GPRINDIRECT+GPRINDIRECTLO:rw.
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lfsx FS:wo, GPR:ro, GPR:ro.
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lfd FPR:wo, GPRINDIRECT+GPRINDIRECTLO:ro.
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lfdu FPR:wo, GPRINDIRECT+GPRINDIRECTLO:ro.
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lfdx FPR:wo, GPR:ro, GPR:ro.
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lfs FSREG:wo, GPRINDIRECT+GPRINDIRECTLO:ro.
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lfsu FSREG:wo, GPRINDIRECT+GPRINDIRECTLO:rw.
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lfsx FSREG:wo, GPR:ro, GPR:ro.
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lhzx GPRI:wo, GPR:ro, GPR:ro.
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lhax GPRI:wo, GPR:ro, GPR:ro.
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lha GPRI:wo, GPRINDIRECT+GPRINDIRECTLO:ro.
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@ -297,12 +328,12 @@ INSTRUCTIONS
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srw GPRI:wo, GPRI:ro, GPRI:ro.
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stb GPRI:ro, GPRINDIRECT+GPRINDIRECTLO:rw.
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stbx GPRI:ro, GPR:ro, GPR:ro.
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stfd FD:ro, GPRINDIRECT+GPRINDIRECTLO:rw.
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stfdu FD:ro, GPRINDIRECT+GPRINDIRECTLO:rw.
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stfdx FD:ro, GPR:ro, GPR:ro.
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stfs FS:ro, GPRINDIRECT+GPRINDIRECTLO:rw.
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stfsu FS:ro, GPRINDIRECT+GPRINDIRECTLO:rw.
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stfsx FS:ro, GPR:ro, GPR:ro.
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stfd FPR:ro, GPRINDIRECT+GPRINDIRECTLO:rw.
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stfdu FPR:ro, GPRINDIRECT+GPRINDIRECTLO:rw.
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stfdx FPR:ro, GPR:ro, GPR:ro.
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stfs FSREG:ro, GPRINDIRECT+GPRINDIRECTLO:rw.
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stfsu FSREG:ro, GPRINDIRECT+GPRINDIRECTLO:rw.
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stfsx FSREG:ro, GPR:ro, GPR:ro.
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sth GPRI:ro, GPRINDIRECT+GPRINDIRECTLO:rw.
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sthx GPRI:ro, GPR:ro, GPR:ro.
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stw GPRI:ro, GPRINDIRECT+GPRINDIRECTLO:rw.
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@ -474,25 +505,25 @@ MOVES
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move {LABEL, %1.adr}, SCRATCH
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lwz %2, {GPRINDIRECT, SCRATCH, 0}
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from IND_RC_W smalls(%off) to FS
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from IND_RC_W smalls(%off) to FSREG
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gen
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COMMENT("move IND_RC_W->FS small")
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COMMENT("move IND_RC_W->FSREG small")
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lfs %2, {GPRINDIRECT, %1.reg, %1.off}
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from IND_RC_W to FS
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from IND_RC_W to FSREG
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gen
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COMMENT("move IND_RC_W->FS large")
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COMMENT("move IND_RC_W->FSREG large")
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addis SCRATCH, %1.reg, {CONST, his(%1.off)}
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lfs %2, {GPRINDIRECT, SCRATCH, los(%1.off)}
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from IND_RR_W to FS
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from IND_RR_W to FSREG
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gen
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COMMENT("move IND_RR_W->FS")
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COMMENT("move IND_RR_W->FSREG")
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lfsx %2, %1.reg1, %1.reg2
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from IND_LABEL_W to FS
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from IND_LABEL_W to FSREG
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gen
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COMMENT("move IND_LABEL_W->FS")
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COMMENT("move IND_LABEL_W->FSREG")
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move {LABEL, %1.adr}, SCRATCH
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lfs %2, {GPRINDIRECT, SCRATCH, 0}
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@ -520,73 +551,73 @@ MOVES
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move {LABEL, %2.adr}, SCRATCH
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stw %1, {GPRINDIRECT, SCRATCH, 0}
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from FS to IND_RC_W smalls(%off)
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from FSREG to IND_RC_W smalls(%off)
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gen
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COMMENT("move FS->IND_RC_W small")
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COMMENT("move FSREG->IND_RC_W small")
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stfs %1, {GPRINDIRECT, %2.reg, %2.off}
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from FS to IND_RC_W
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from FSREG to IND_RC_W
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gen
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COMMENT("move FS->IND_RC_W large")
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COMMENT("move FSREG->IND_RC_W large")
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addis SCRATCH, %2.reg, {CONST, his(%2.off)}
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stfs %1, {GPRINDIRECT, SCRATCH, los(%2.off)}
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from FS to IND_RR_W
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from FSREG to IND_RR_W
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gen
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COMMENT("move FS->IND_RR_W")
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COMMENT("move FSREG->IND_RR_W")
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stfsx %1, %2.reg1, %2.reg2
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from FS to IND_LABEL_W
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from FSREG to IND_LABEL_W
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gen
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COMMENT("move FS->IND_LABEL_D")
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COMMENT("move FSREG->IND_LABEL_D")
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move {LABEL, %2.adr}, SCRATCH
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stfs %1, {GPRINDIRECT, SCRATCH, 0}
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/* Read double */
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from IND_RC_D smalls(%off) to FD
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from IND_RC_D smalls(%off) to FPR
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gen
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COMMENT("move IND_RC_D->FD small")
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COMMENT("move IND_RC_D->FPR small")
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lfd %2, {GPRINDIRECT, %1.reg, %1.off}
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from IND_RC_D to FD
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from IND_RC_D to FPR
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gen
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COMMENT("move IND_RC_D->FD large")
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COMMENT("move IND_RC_D->FPR large")
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addis SCRATCH, %1.reg, {CONST, his(%1.off)}
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lfd %2, {GPRINDIRECT, SCRATCH, los(%1.off)}
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from IND_RR_D to FD
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from IND_RR_D to FPR
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gen
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COMMENT("move IND_RR_D->FD")
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COMMENT("move IND_RR_D->FPR")
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lfdx %2, %1.reg1, %1.reg2
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from IND_LABEL_D to FD
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from IND_LABEL_D to FPR
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gen
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COMMENT("move IND_LABEL_D->FD")
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COMMENT("move IND_LABEL_D->FPR")
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move {LABEL, %1.adr}, SCRATCH
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lfd %2, {GPRINDIRECT, SCRATCH, 0}
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/* Write double */
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from FD to IND_RC_D smalls(%off)
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from FPR to IND_RC_D smalls(%off)
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gen
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COMMENT("move FD->IND_RC_D small")
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COMMENT("move FPR->IND_RC_D small")
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stfd %1, {GPRINDIRECT, %2.reg, %2.off}
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from FD to IND_RC_D
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from FPR to IND_RC_D
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gen
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COMMENT("move FD->IND_RC_D large")
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COMMENT("move FPR->IND_RC_D large")
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addis SCRATCH, %2.reg, {CONST, his(%2.off)}
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stfd %1, {GPRINDIRECT, SCRATCH, los(%2.off)}
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from FD to IND_RR_D
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from FPR to IND_RR_D
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gen
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COMMENT("move FD->IND_RR_W")
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COMMENT("move FPR->IND_RR_W")
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stfdx %1, %2.reg1, %2.reg2
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from FD to IND_LABEL_D
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from FPR to IND_LABEL_D
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gen
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COMMENT("move FD->IND_LABEL_D")
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COMMENT("move FPR->IND_LABEL_D")
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move {LABEL, %2.adr}, SCRATCH
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stfd %1, {GPRINDIRECT, SCRATCH, 0}
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@ -628,7 +659,7 @@ MOVES
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from TRISTATE_FF to CR0
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gen
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COMMENT("move TRISTATE_FF->CR0")
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fcmpo %2, {FD, %1.reg1}, {FD, %1.reg2}
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fcmpo %2, %1.reg1, %1.reg2
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from GPR to CR0
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gen
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@ -766,17 +797,17 @@ STACKINGRULES
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from IND_ALL_D to STACK
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gen
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move %1, {FD, FSCRATCH}
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stfdu {FD, FSCRATCH}, {GPRINDIRECT, SP, 0-8}
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move %1, FSCRATCH
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stfdu FSCRATCH, {GPRINDIRECT, SP, 0-8}
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from FD to STACK
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from FPR to STACK
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gen
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COMMENT("stack FD")
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COMMENT("stack FPR")
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stfdu %1, {GPRINDIRECT, SP, 0-8}
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from FS to STACK
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from FSREG to STACK
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gen
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COMMENT("stack FS")
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COMMENT("stack FSREG")
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stfsu %1, {GPRINDIRECT, SP, 0-4}
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from TOKEN to STACK
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@ -836,33 +867,33 @@ COERCIONS
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move %1, {GPRE, %a}
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yields %a
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from FS
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uses FREG
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from FSREG
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uses FSREG
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gen
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fmr {FS, %a}, %1
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yields {FS, %a}
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fmr %a, %1
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yields %a
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from FD
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uses FREG
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from FPR
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uses FPR
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gen
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fmr {FD, %a}, %1
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yields {FD, %a}
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fmr %a, %1
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yields %a
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from STACK
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uses FREG
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gen
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COMMENT("coerce STACK->FD")
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lfd {FD, %a}, {GPRINDIRECT, SP, 0}
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COMMENT("coerce STACK->FREG")
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lfd %a, {GPRINDIRECT, SP, 0}
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addi SP, SP, {CONST, 8}
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yields {FD, %a}
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yields %a
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from STACK
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uses FREG
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uses FSREG
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gen
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COMMENT("coerce STACK->FS")
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lfs {FS, %a}, {GPRINDIRECT, SP, 0}
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COMMENT("coerce STACK->FSREG")
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lfs %a, {GPRINDIRECT, SP, 0}
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addi SP, SP, {CONST, 4}
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yields {FS, %a}
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yields %a
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from IND_ALL_W
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uses REG
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|
@ -871,16 +902,16 @@ COERCIONS
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yields %a
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from IND_ALL_W
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uses FREG
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uses FSREG
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gen
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move %1, {FS, %a}
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yields {FS, %a}
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move %1, %a
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yields %a
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from IND_ALL_D
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uses FREG
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gen
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move %1, {FD, %a}
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yields {FD, %a}
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move %1, %a
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yields %a
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||||
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|
@ -1242,27 +1273,27 @@ PATTERNS
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move %2.reg, {IND_RC_H, %1.reg, %1.off}
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pat sti $1==INT32 /* Store word indirect */
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with GPR GPR+FS
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with GPR GPR+FSREG
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gen
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move %2, {IND_RC_W, %1, 0}
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with SUM_RR GPR+FS
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with SUM_RR GPR+FSREG
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gen
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move %2, {IND_RR_W, %1.reg1, %1.reg2}
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with SUM_RC GPR+FS
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with SUM_RC GPR+FSREG
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gen
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move %2, {IND_RC_W, %1.reg, %1.off}
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with LABEL GPR+FS
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with LABEL GPR+FSREG
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gen
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move %2, {IND_LABEL_W, %1.adr}
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||||
|
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pat sti $1==INT64 /* Store double-word indirect */
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with GPR FD
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with GPR FREG
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||||
gen
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move %2, {IND_RC_D, %1, 0}
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with SUM_RR FD
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with SUM_RR FREG
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gen
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move %2, {IND_RR_D, %1.reg1, %1.reg2}
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with SUM_RC FD
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with SUM_RC FREG
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gen
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move %2, {IND_RC_D, %1.reg, %1.off}
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with GPR GPR GPR
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|
|
@ -1273,7 +1304,7 @@ PATTERNS
|
|||
gen
|
||||
move %2, {IND_RC_W, %1.reg, %1.off}
|
||||
move %3, {IND_RC_W, %1.reg, %1.off+4}
|
||||
with LABEL FD
|
||||
with LABEL FREG
|
||||
gen
|
||||
move %2, {IND_LABEL_D, %1.adr}
|
||||
|
||||
|
|
@ -2004,47 +2035,47 @@ PATTERNS
|
|||
loe ".fs_00000000"
|
||||
|
||||
pat adf $1==INT32 /* Add single */
|
||||
with FS FS
|
||||
uses reusing %1, FREG
|
||||
with FSREG FSREG
|
||||
uses reusing %1, FSREG
|
||||
gen
|
||||
fadds {FS, %a}, %2, %1
|
||||
yields {FS, %a}
|
||||
fadds %a, %2, %1
|
||||
yields %a
|
||||
|
||||
pat sbf $1==INT32 /* Subtract single */
|
||||
with FS FS
|
||||
uses reusing %1, FREG
|
||||
with FSREG FSREG
|
||||
uses reusing %1, FSREG
|
||||
gen
|
||||
fsubs {FS, %a}, %2, %1
|
||||
yields {FS, %a}
|
||||
fsubs %a, %2, %1
|
||||
yields %a
|
||||
|
||||
pat mlf $1==INT32 /* Multiply single */
|
||||
with FS FS
|
||||
uses reusing %1, FREG
|
||||
with FSREG FSREG
|
||||
uses reusing %1, FSREG
|
||||
gen
|
||||
fmuls {FS, %a}, %2, %1
|
||||
yields {FS, %a}
|
||||
fmuls %a, %2, %1
|
||||
yields %a
|
||||
|
||||
pat dvf $1==INT32 /* Divide single */
|
||||
with FS FS
|
||||
uses reusing %1, FREG
|
||||
with FSREG FSREG
|
||||
uses reusing %1, FSREG
|
||||
gen
|
||||
fdivs {FS, %a}, %2, %1
|
||||
yields {FS, %a}
|
||||
fdivs %a, %2, %1
|
||||
yields %a
|
||||
|
||||
pat ngf $1==INT32 /* Negate single */
|
||||
with FS
|
||||
uses reusing %1, FREG
|
||||
with FSREG
|
||||
uses reusing %1, FSREG
|
||||
gen
|
||||
fneg {FS, %a}, %1
|
||||
yields {FS, %a}
|
||||
fneg %a, %1
|
||||
yields %a
|
||||
|
||||
pat cmf $1==INT32 /* Compare single */
|
||||
with FS FS
|
||||
yields {TRISTATE_FF, %2.reg, %1.reg}
|
||||
with FSREG FSREG
|
||||
yields {TRISTATE_FF, %2.1, %1.1}
|
||||
|
||||
pat loc loc cff $1==INT32 && $2==INT64 /* Convert single to double */
|
||||
with FS
|
||||
yields {FD, %1.reg}
|
||||
with FSREG
|
||||
yields %1.1
|
||||
|
||||
pat loc loc cfu $1==INT32 && $2==INT32 /* Convert single to unsigned int */
|
||||
with STACK
|
||||
|
|
@ -2078,50 +2109,50 @@ PATTERNS
|
|||
lde ".fd_00000000"
|
||||
|
||||
pat adf $1==INT64 /* Add double */
|
||||
with FD FD
|
||||
with FREG FREG
|
||||
uses FREG
|
||||
gen
|
||||
fadd {FD, %a}, %2, %1
|
||||
yields {FD, %a}
|
||||
fadd %a, %2, %1
|
||||
yields %a
|
||||
|
||||
pat sbf $1==INT64 /* Subtract double */
|
||||
with FD FD
|
||||
with FREG FREG
|
||||
uses FREG
|
||||
gen
|
||||
fsub {FD, %a}, %2, %1
|
||||
yields {FD, %a}
|
||||
fsub %a, %2, %1
|
||||
yields %a
|
||||
|
||||
pat mlf $1==INT64 /* Multiply double */
|
||||
with FD FD
|
||||
with FREG FREG
|
||||
uses reusing %1, FREG
|
||||
gen
|
||||
fmul {FD, %a}, %2, %1
|
||||
yields {FD, %a}
|
||||
fmul %a, %2, %1
|
||||
yields %a
|
||||
|
||||
pat dvf $1==INT64 /* Divide double */
|
||||
with FD FD
|
||||
with FREG FREG
|
||||
uses reusing %1, FREG
|
||||
gen
|
||||
fdiv {FD, %a}, %2, %1
|
||||
yields {FD, %a}
|
||||
fdiv %a, %2, %1
|
||||
yields %a
|
||||
|
||||
pat ngf $1==INT64 /* Negate double */
|
||||
with FD
|
||||
with FREG
|
||||
uses reusing %1, FREG
|
||||
gen
|
||||
fneg {FD, %a}, %1
|
||||
yields {FD, %a}
|
||||
fneg %a, %1
|
||||
yields %a
|
||||
|
||||
pat cmf $1==INT64 /* Compare double */
|
||||
with FD FD
|
||||
yields {TRISTATE_FF, %2.reg, %1.reg}
|
||||
with FREG FREG
|
||||
yields {TRISTATE_FF, %2, %1}
|
||||
|
||||
pat loc loc cff $1==INT64 && $2==INT32 /* Convert double to single */
|
||||
with FD
|
||||
uses reusing %1, FREG
|
||||
with FREG
|
||||
uses reusing %1, FSREG
|
||||
gen
|
||||
frsp {FS, %a}, %1
|
||||
yields {FS, %a}
|
||||
frsp %a, %1
|
||||
yields %a
|
||||
|
||||
pat loc loc cfu $1==INT64 && $2==INT32 /* Convert double to unsigned int */
|
||||
with STACK
|
||||
|
|
@ -2145,7 +2176,7 @@ PATTERNS
|
|||
bl {LABEL, ".cuf8"}
|
||||
|
||||
pat fef $1==INT64 /* Split double */
|
||||
with FD
|
||||
with FREG
|
||||
gen
|
||||
addi SP, SP, {CONST, 0-8}
|
||||
stfd %1, {GPRINDIRECT, SP, 0}
|
||||
|
|
|
|||
|
|
@ -635,8 +635,8 @@ coderule
|
|||
maxempatlen=empatlen;
|
||||
}
|
||||
patterns
|
||||
{ /* if (!saferulefound)
|
||||
error("Previous rule impossible on empty stack"); */
|
||||
{ if (!saferulefound)
|
||||
error("Previous rule impossible on empty stack");
|
||||
outpatterns();
|
||||
}
|
||||
| PROC IDENT example
|
||||
|
|
|
|||
Loading…
Reference in a new issue