Remove REG_PAIR.
I added REG_PAIR incfbc537
to speed up the register allocator, because ncg was taking about 2 seconds on each sti 8. I defined only 4 such pairs, so allocating REG_PAIR was much faster than allocating REG REG. After my last commitc5bb3be
, allocation of REG REG is fast, and REG_PAIR seems unnecessary.
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c5bb3be495
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@ -32,7 +32,6 @@ PROPERTIES
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GPR /* any GPR */
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REG /* any allocatable GPR */
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REG_PAIR(8) /* speed hack for sti 8 */
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FPR(8) /* any FPR */
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FREG(8) /* any allocatable FPR */
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FSREG /* any allocatable single-precision FPR */
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@ -54,12 +53,6 @@ REGISTERS
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fp, sp, r0 : GPR.
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/* speed hack for sti 8 */
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PAIR_R9_R10=r9+r10 : REG_PAIR.
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PAIR_R7_R8=r7+r8 : REG_PAIR.
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PAIR_R5_R6=r5+r6 : REG_PAIR.
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PAIR_R3_R4=r3+r4 : REG_PAIR.
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/* f31 to f14 are reserved for regvar. */
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f13, f12, f11, f10, f9, f8
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@ -580,12 +573,6 @@ STACKINGRULES
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COMMENT("stack REG")
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stwu %1, {IND_RC_W, sp, 0-4}
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from REG_PAIR to STACK
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gen
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COMMENT("stack REG_PAIR")
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stwu %1.2, {IND_RC_W, sp, 0-4}
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stwu %1.1, {IND_RC_W, sp, 0-4}
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from ANY_BHW-REG to STACK
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gen
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COMMENT("stack ANY_BHW-REG")
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@ -627,15 +614,6 @@ COERCIONS
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addi sp, sp, {CONST, 4}
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yields %a
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from STACK
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uses REG_PAIR
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gen
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COMMENT("coerce STACK->REG_PAIR")
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lwz %a.1, {IND_RC_W, sp, 0}
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lwz %a.2, {IND_RC_W, sp, 4}
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addi sp, sp, {CONST, 8}
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yields %a
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from FSREG
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uses FSREG
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gen
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@ -671,9 +649,9 @@ COERCIONS
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yields %a
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/*
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* from IND_RC_D to REG_PAIR is not possible, because
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* from IND_RC_D to REG REG is not possible, because
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* %1.off+4 might overflow a signed 16-bit integer in
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* move {IND_RC_W, %1.val, %1.off+4}, %a.2
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* move {IND_RC_W, %1.val, %1.off+4}, %a
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*/
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from IND_ALL_D
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@ -1035,38 +1013,31 @@ PATTERNS
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with SUM_RR FREG
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kills MEMORY
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gen move %2, {IND_RR_D, %1.reg1, %1.reg2}
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/*
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* This pattern would be too slow:
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* with REG REG REG
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* ncg can't handle that many registers, and would
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* take about 2 seconds on each sti 8. So we use
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* REG_PAIR as a speed hack for sti 8.
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*/
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with REG REG_PAIR
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with REG REG REG
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kills MEMORY
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gen
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move %2.1, {IND_RC_W, %1, 0}
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move %2.2, {IND_RC_W, %1, 4}
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move %2, {IND_RC_W, %1, 0}
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move %3, {IND_RC_W, %1, 4}
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/*
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* Next 2 patterns exist because there is no coercion
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* from IND_ALL_D to REG_PAIR.
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* from IND_ALL_D to REG REG.
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*/
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with REG IND_RC_D
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kills MEMORY
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uses REG={SUM_RC, %2.reg, %2.off}, REG_PAIR
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uses REG={SUM_RC, %2.reg, %2.off}, REG, REG
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gen
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move {IND_RC_W, %a, 0}, %b.1
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move {IND_RC_W, %a, 4}, %b.2
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move %b.1, {IND_RC_W, %1, 0}
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move %b.2, {IND_RC_W, %1, 4}
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move {IND_RC_W, %a, 0}, %b
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move {IND_RC_W, %a, 4}, %c
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move %b, {IND_RC_W, %1, 0}
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move %c, {IND_RC_W, %1, 4}
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with REG IND_RR_D
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kills MEMORY
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uses REG={SUM_RR, %2.reg1, %2.reg2}, REG_PAIR
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uses REG={SUM_RR, %2.reg1, %2.reg2}, REG, REG
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gen
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move {IND_RC_W, %a, 0}, %b.1
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move {IND_RC_W, %a, 4}, %b.2
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move %b.1, {IND_RC_W, %1, 0}
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move %b.2, {IND_RC_W, %1, 4}
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move {IND_RC_W, %a, 0}, %b
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move {IND_RC_W, %a, 4}, %c
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move %b, {IND_RC_W, %1, 0}
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move %c, {IND_RC_W, %1, 4}
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pat sti /* Store arbitrary size */
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leaving
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