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Add more rules for single-precision reg_float.

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The result of single-precision fadds, fsubs, and such can go into a
register variable, like we already do with double precision.  This
avoids an extra fmr from a temporary register to the regvar.
This commit is contained in:
George Koehler 2017-10-17 17:53:03 -04:00
parent 47bd0ef7a7
commit ac2b0710c8
1 changed files with 23 additions and 8 deletions
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31
mach/powerpc/ncg/table
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@ -260,21 +260,21 @@ INSTRUCTIONS
extsb GPR:wo, GPR:ro. extsb GPR:wo, GPR:ro.
extsh GPR:wo, GPR:ro. extsh GPR:wo, GPR:ro.
fadd FREG+DLOCAL:wo, FREG:ro, FREG:ro cost(4, 5). fadd FREG+DLOCAL:wo, FREG:ro, FREG:ro cost(4, 5).
fadds FSREG:wo, FSREG:ro, FSREG:ro cost(4, 5). fadds FSREG+LOCAL:wo, FSREG:ro, FSREG:ro cost(4, 5).
fcmpo CR:wo, FREG:ro, FREG:ro cost(4, 5). fcmpo CR:wo, FREG:ro, FREG:ro cost(4, 5).
fcmpo CR:wo, FSREG:ro, FSREG:ro cost(4, 5). fcmpo CR:wo, FSREG:ro, FSREG:ro cost(4, 5).
fctiwz FREG:wo, FREG:ro. fctiwz FREG:wo, FREG:ro.
fdiv FREG+DLOCAL:wo, FREG:ro, FREG:ro cost(4, 35). fdiv FREG+DLOCAL:wo, FREG:ro, FREG:ro cost(4, 35).
fdivs FSREG:wo, FSREG:ro, FSREG:ro cost(4, 21). fdivs FSREG+LOCAL:wo, FSREG:ro, FSREG:ro cost(4, 21).
fmr FPR:wo, FPR:ro cost(4, 5). fmr FPR:wo, FPR:ro cost(4, 5).
fmr FSREG:wo, FSREG:ro cost(4, 5). fmr FSREG:wo, FSREG:ro cost(4, 5).
fmul FREG+DLOCAL:wo, FREG:ro, FREG:ro cost(4, 5). fmul FREG+DLOCAL:wo, FREG:ro, FREG:ro cost(4, 5).
fmuls FSREG:wo, FSREG:ro, FSREG:ro cost(4, 5). fmuls FSREG+LOCAL:wo, FSREG:ro, FSREG:ro cost(4, 5).
fneg FREG+DLOCAL:wo, FREG:ro cost(4, 5). fneg FREG+DLOCAL:wo, FREG:ro cost(4, 5).
fneg FSREG:wo, FSREG:ro cost(4, 5). fneg FSREG+LOCAL:wo, FSREG:ro cost(4, 5).
frsp FSREG:wo, FREG:ro cost(4, 5). frsp FSREG:wo, FREG:ro cost(4, 5).
fsub FREG+DLOCAL:wo, FREG:ro, FREG:ro cost(4, 5). fsub FREG+DLOCAL:wo, FREG:ro, FREG:ro cost(4, 5).
fsubs FSREG:wo, FSREG:ro, FSREG:ro cost(4, 5). fsubs FSREG+LOCAL:wo, FSREG:ro, FSREG:ro cost(4, 5).
lbz GPR:wo, IND_RC_B+IND_RL_B:ro cost(4, 3). lbz GPR:wo, IND_RC_B+IND_RL_B:ro cost(4, 3).
lbzx GPR:wo, GPR:ro, GPR:ro cost(4, 3). lbzx GPR:wo, GPR:ro, GPR:ro cost(4, 3).
lfd FPR+DLOCAL:wo, IND_RC_D+IND_RL_D:ro cost(4, 5). lfd FPR+DLOCAL:wo, IND_RC_D+IND_RL_D:ro cost(4, 5).
@ -2082,26 +2082,35 @@ PATTERNS
leaving leaving
loe ".fs_00000000" loe ".fs_00000000"
pat adf $1==INT32 /* Add single */ pat adf $1==4 /* Add single */
with FSREG FSREG with FSREG FSREG
uses reusing %1, FSREG uses reusing %1, FSREG
gen gen
fadds %a, %2, %1 fadds %a, %2, %1
yields %a yields %a
pat adf stl $1==4 && inreg($2)==reg_float
with FSREG FSREG
gen fadds {LOCAL, $2}, %2, %1
pat sbf $1==INT32 /* Subtract single */ pat sbf $1==4 /* Subtract single */
with FSREG FSREG with FSREG FSREG
uses reusing %1, FSREG uses reusing %1, FSREG
gen gen
fsubs %a, %2, %1 fsubs %a, %2, %1
yields %a yields %a
pat sbf stl $1==4 && inreg($2)==reg_float
with FSREG FSREG
gen fsubs {LOCAL, $2}, %2, %1
pat mlf $1==INT32 /* Multiply single */ pat mlf $1==4 /* Multiply single */
with FSREG FSREG with FSREG FSREG
uses reusing %1, FSREG uses reusing %1, FSREG
gen gen
fmuls %a, %2, %1 fmuls %a, %2, %1
yields %a yields %a
pat mlf stl $1==4 && inreg($2)==reg_float
with FSREG FSREG
gen fmuls {LOCAL, $2}, %2, %1
pat dvf $1==INT32 /* Divide single */ pat dvf $1==INT32 /* Divide single */
with FSREG FSREG with FSREG FSREG
@ -2109,6 +2118,9 @@ PATTERNS
gen gen
fdivs %a, %2, %1 fdivs %a, %2, %1
yields %a yields %a
pat dvf stl $1==4 && inreg($2)==reg_float
with FSREG FSREG
gen fdivs {LOCAL, $2}, %2, %1
pat ngf $1==INT32 /* Negate single */ pat ngf $1==INT32 /* Negate single */
with FSREG with FSREG
@ -2116,6 +2128,9 @@ PATTERNS
gen gen
fneg %a, %1 fneg %a, %1
yields %a yields %a
pat ngf stl $1==4 && inreg($2)==reg_float
with FSREG
gen fneg {LOCAL, $2}, %1
pat cmf $1==INT32 /* Compare single */ pat cmf $1==INT32 /* Compare single */
with FSREG FSREG with FSREG FSREG