Rename ANY_BHW to INT_W; add FLOAT_W, FLOAT_D.
INT_W, the integer set, continues to exclude FSREG, because we can't easily move FSREG to GPR. ANY4 becomes ISET+FLOAT_W and ANY8 becomes FLOAT_D.
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@ -65,7 +65,7 @@ REGISTERS
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f0 : FPR.
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f1, f2, f3, f4, f5, f6, f7, f8, f9, f10, f11, f12, f13
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: FPR, FREG.
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: FPR, FREG.
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f14, f15, f16, f17, f18, f19, f20, f21, f22, f23, f24, f25,
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f26, f27, f28, f29, f30, f31
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@ -202,24 +202,23 @@ SETS
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IND_RC_H_S + IND_RL_H_S + IND_RR_H_S.
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IND_ALL_W = IND_RC_W + IND_RL_W + IND_RR_W.
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IND_ALL_D = IND_RC_D + IND_RL_D + IND_RR_D.
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IND_ALL_BHW = IND_ALL_B + IND_ALL_H + IND_ALL_W.
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/* anything killed by sti (store indirect) */
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MEMORY = IND_ALL_BHW + IND_ALL_D.
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MEMORY = IND_ALL_B + IND_ALL_H + IND_ALL_W + IND_ALL_D.
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/* any stack token that we can easily move to GPR */
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ANY_BHW = REG + CONST_STACK + SEX_B + SEX_H +
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/* any integer from stack that we can easily move to GPR */
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INT_W = REG + CONST_STACK + SEX_B + SEX_H +
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SUM_RIS + SUM_RC + SUM_RL + SUM_RR +
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SUB_RR + NEG_R + MUL_RR + DIV_RR + DIV_RR_U +
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IND_ALL_BHW +
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IND_ALL_B + IND_ALL_H + IND_ALL_W +
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NOT_R + AND_RIS + AND_RC + AND_RR + ANDC_RR +
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OR_RIS + OR_RC + OR_RR + ORC_RR +
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XOR_RIS + XOR_RC + XOR_RR + NAND_RR + NOR_RR + EQV_RR +
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XEQ + XNE + XGT + XGE + XLT + XLE.
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/* any register or token of each size */
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ANY4 = ANY_BHW + FSREG.
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ANY8 = IND_ALL_D + FREG.
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FLOAT_D = FREG + IND_ALL_D.
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FLOAT_W = FSREG + IND_ALL_W.
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INSTRUCTIONS
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@ -634,13 +633,13 @@ MOVES
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our moves to GPR to set register variables. We define no moves to
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LOCAL, so we avoid confusion between GPR and FSREG in LOCAL. */
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from ANY_BHW to GPR_EXPR
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from INT_W to GPR_EXPR
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gen move %1, %2.reg
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from FPR+IND_ALL_D to FPR_EXPR
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from FLOAT_D to FPR_EXPR
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gen move %1, %2.reg
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from FSREG+IND_ALL_W to FSREG_EXPR
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from FLOAT_W to FSREG_EXPR
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gen move %1, %2.reg
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@ -664,15 +663,15 @@ STACKINGRULES
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COMMENT("stack REG")
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stwu %1, {IND_RC_W, sp, 0-4}
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from ANY_BHW-REG to STACK
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from INT_W-REG to STACK
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gen
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COMMENT("stack ANY_BHW-REG")
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COMMENT("stack INT_W-REG")
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move %1, RSCRATCH
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stwu RSCRATCH, {IND_RC_W, sp, 0-4}
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from IND_ALL_D to STACK
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from FLOAT_D-FREG to STACK
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gen
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COMMENT("stack IND_ALL_D")
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COMMENT("stack FLOAT_D-FREG")
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move %1, FSCRATCH
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stfdu FSCRATCH, {IND_RC_D, sp, 0-8}
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@ -724,10 +723,10 @@ COERCIONS
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addi sp, sp, {C, 4}
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yields %a
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from ANY_BHW
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from INT_W
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uses REG
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gen
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COMMENT("coerce ANY_BHW->REG")
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COMMENT("coerce INT_W->REG")
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move %1, %a
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yields %a
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@ -741,17 +740,17 @@ COERCIONS
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* but %1.off+4 might overflow a signed 16-bit integer.
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*/
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from FREG+IND_ALL_D
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from FLOAT_D
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uses FREG
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gen
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COMMENT("coerce FREG+IND_ALL_D->FREG")
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COMMENT("coerce FLOAT_D->FREG")
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move %1, %a
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yields %a
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from FSREG+IND_ALL_W
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from FLOAT_W
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uses FSREG
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gen
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COMMENT("coerce FSREG+IND_ALL_W->FREG")
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COMMENT("coerce FLOAT_W->FREG")
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move %1, %a
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yields %a
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@ -784,7 +783,7 @@ PATTERNS
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*/
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pat asp $1==4 /* Adjust stack by constant */
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with exact ANY4
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with exact INT_W+FLOAT_W
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/* drop %1 */
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with STACK
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gen addi sp, sp, {C, 4}
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@ -836,7 +835,7 @@ PATTERNS
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bdnz {LABEL, "1b"}
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pat exg $1==4 /* Exchange top two words */
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with ANY4 ANY4
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with INT_W+FLOAT_W INT_W+FLOAT_W
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yields %1 %2
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pat exg defined($1) /* Exchange other size */
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@ -911,7 +910,7 @@ PATTERNS
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/* Store word to local */
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pat stl inreg($1)==reg_any
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with exact ANY_BHW
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with exact INT_W
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/* ncg fails to infer that regvar($1) is dead! */
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kills regvar($1)
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gen move %1, {GPR_EXPR, regvar($1)}
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