Add instructions like "lwarx". Extend manual.
Add more page numbers from PowerPC version 2.01. Remove "xnop" not in 2.01, add "mtcr" from 2.01. Add "lwarx" and the other instructions from Book II. I did not try all the newly added instructions, but these seem to work: dcbt, dcbtst, icibi, isync, lwarx, stwcx., mftb, mftbu In man/powerpc_as.6 (not installed), add a summary of the registers and addressing modes (like in i386_as.6), describe short forms, update description of hi16/ha16, add CAVEATS about instructions that some processors can't run.
This commit is contained in:
George Koehler
parent
b1b737ed6c
commit
b1badf1851
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@ -47,11 +47,15 @@
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%token <y_word> OP_FRT_FRB_C
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%token <y_word> OP_FRT_RA_D
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%token <y_word> OP_FRT_RA_RB
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%token <y_word> OP_L
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%token <y_word> OP_LEV
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%token <y_word> OP_LIA
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%token <y_word> OP_LIL
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%token <y_word> OP_LI32
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%token <y_word> OP_RA_RB
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%token <y_word> OP_RA_RB_TH
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%token <y_word> OP_RA_RS_C
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%token <y_word> OP_RA_RS_RA_C
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%token <y_word> OP_RA_RS_RB_C
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%token <y_word> OP_RA_RS_RB_MB5_ME5_C
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%token <y_word> OP_RA_RS_RB_MB6_C
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@ -61,14 +65,14 @@
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%token <y_word> OP_RA_RS_SH6_MB6_C
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%token <y_word> OP_RA_RS_UI
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%token <y_word> OP_RA_RS_UI_CC
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%token <y_word> OP_RS
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%token <y_word> OP_RS_FXM
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%token <y_word> OP_RS_RA
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%token <y_word> OP_RS_RA_D
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%token <y_word> OP_RS_RA_DS
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%token <y_word> OP_RS_RA_NB
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%token <y_word> OP_RS_RA_RB
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%token <y_word> OP_RS_RA_RB_C
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%token <y_word> OP_RS_RA_RA_C
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%token <y_word> OP_RS_RA_RB_CC
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%token <y_word> OP_RS_RB
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%token <y_word> OP_RS_SPR
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%token <y_word> OP_RS_SR
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@ -104,4 +108,5 @@
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%type <y_word> c
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%type <y_word> e16 negate16 u8 u7 u6 u5 u4 u2 u1
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%type <y_word> opt_bh cr_opt nb ds bda bdl lia lil spr_num
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%type <y_word> opt_bh cr_opt nb ds bda bdl lia lil
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%type <y_word> spr_num tbr_num opt_tbr
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@ -103,6 +103,10 @@
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0, OP_HA, 0, "ha16",
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0, OP_LO, 0, "lo16",
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/* The next page numbers are from PowerPC User Instruction Set
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* Architecture, Book I, Version 2.01.
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*/
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/* Branch processor instructions (page 20) */
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0, OP_LIL, 18<<26 | 0<<1 | 0<<0, "b",
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@ -128,7 +132,7 @@
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0, OP_BT_BA_BB, 19<<26 | 417<<1, "crorc",
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0, OP_BF_BFA, 19<<26 | 0<<1, "mcrf",
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/* extended mnemonics for bc, bcctr, bclr */
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/* extended mnemonics for bc, bcctr, bclr (page 144) */
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0, OP_BH, 19<<26 | 20<<21 | 528<<1 | 0<<0, "bctr",
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0, OP_BH, 19<<26 | 20<<21 | 528<<1 | 1<<0, "bctrl",
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0, OP_BDL, 16<<26 | 16<<21 | 0<<1 | 0<<0, "bdnz",
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@ -186,7 +190,7 @@
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0, OP_BI_BH, 19<<26 | 12<<21 | 16<<1 | 0<<0, "btlr",
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0, OP_BI_BH, 19<<26 | 12<<21 | 16<<1 | 1<<0, "btlrl",
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/* extended m with condition in BI */
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/* extended m with condition in BI (page 146) */
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0, OP_BICR_BDL, 16<<26 | 12<<21 | 2<<16 | 0<<1 | 0<<0, "beq",
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0, OP_BICR_BDA, 16<<26 | 12<<21 | 2<<16 | 1<<1 | 0<<0, "beqa",
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0, OP_BICR_BH, 19<<26 | 12<<21 | 2<<16 | 528<<1 | 0<<0, "beqctr",
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@ -284,7 +288,7 @@
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0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 0<<0, "bunlr",
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0, OP_BICR_BH, 19<<26 | 12<<21 | 3<<16 | 16<<1 | 1<<0, "bunlrl",
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/* extended m for cr logic */
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/* extended m for cr logic (page 147) */
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0, OP_BT_BT_BT, 19<<26 | 289<<1, "crset",
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0, OP_BT_BT_BT, 19<<26 | 193<<1, "crclr",
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0, OP_BT_BA_BA, 19<<26 | 449<<1, "crmove",
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@ -377,12 +381,12 @@
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0, OP_RT_RA_C, 31<<26 | 0<<10 | 104<<1, "neg",
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0, OP_RT_RA_C, 31<<26 | 1<<10 | 104<<1, "nego",
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/* extended m for addition */
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/* extended m for addition (pages 153, 154) */
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0, OP_RT_RA_D, 14<<26, "la",
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0, OP_RT_SI, 14<<26 | 0<<16, "li",
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0, OP_RT_SI, 15<<26 | 0<<16, "lis",
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/* extended m for subtraction */
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/* extended m for subtraction (pages 147, 148) */
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0, OP_RT_RB_RA_C, 31<<26 | 0<<10 | 40<<1, "sub",
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0, OP_RT_RB_RA_C, 31<<26 | 1<<10 | 40<<1, "subo",
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0, OP_RT_RB_RA_C, 31<<26 | 0<<10 | 8<<1, "subc",
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@ -418,7 +422,7 @@
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0, OP_BF_L_RA_UI, 10<<26, "cmpli",
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0, OP_BF_L_RA_RB, 31<<26 | 32<<1, "cmpl",
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/* extended m for comparison */
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/* extended m for comparison (page 149) */
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0, OP_BF_RA_SI, 11<<26 | 1<<21, "cmpdi",
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0, OP_BF_RA_RB, 31<<26 | 1<<21 | 0<<1, "cmpd",
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0, OP_BF_RA_UI, 10<<26 | 1<<21, "cmpldi",
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@ -434,7 +438,7 @@
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0, OP_TO_RA_RB, 31<<26 | 68<<1, "td",
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0, OP_TO_RA_RB, 31<<26 | 4<<1, "tw",
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/* extended m for traps */
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/* extended m for traps (page 150) */
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0, OP_TOX_RA_RB, 31<<26 | 4<<21 | 68<<1, "tdeq",
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0, OP_TOX_RA_SI, 2<<26 | 4<<21, "tdeqi",
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0, OP_TOX_RA_RB, 31<<26 | 12<<21 | 68<<1, "tdge",
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@ -518,11 +522,10 @@
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0, OP_RA_RS_C, 31<<26 | 58<<1, "cntlzd",
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0, OP_RA_RS_C, 31<<26 | 26<<1, "cntlzw",
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/* extended m using logic */
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0, OP_RS_RA_RA_C, 31<<26 | 444<<1, "mr",
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/* extended m using logic (pages 153, 154) */
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0, OP_RA_RS_RA_C, 31<<26 | 444<<1, "mr",
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0, OP, 24<<26, "nop",
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0, OP_RS_RA_RA_C, 31<<26 | 124<<1, "not",
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0, OP, 26<<26, "xnop",
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0, OP_RA_RS_RA_C, 31<<26 | 124<<1, "not",
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/* page 69 */
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0, OP_RA_RS_SH6_MB6_C, 30<<26 | 0<<2, "rldicl",
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@ -535,7 +538,7 @@
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0, OP_RA_RS_SH6_MB6_C, 30<<26 | 3<<2, "rldimi",
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0, OP_RA_RS_SH5_MB5_ME5_C, 20<<26, "rlwimi",
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/* extended m for doubleword rotation */
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/* extended m for doubleword rotation (page 151) */
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0, OP_clrlsldi, 30<<26 | 2<<2, "clrlsldi",
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0, OP_clrldi, 30<<26 | 0<<2, "clrldi",
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0, OP_clrrdi, 30<<26 | 1<<2, "clrrdi",
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@ -548,7 +551,7 @@
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0, OP_sldi, 30<<26 | 1<<2, "sldi",
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0, OP_srdi, 30<<26 | 0<<2, "srdi",
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/* extended m for word rotation */
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/* extended m for word rotation (page 152) */
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0, OP_clrlslwi, 21<<26, "clrlslwi",
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0, OP_clrlwi, 21<<26, "clrlwi",
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0, OP_clrrwi, 21<<26, "clrrwi",
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@ -575,19 +578,23 @@
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/* page 78 */
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0, OP_RS_SPR, 31<<26 | 467<<1, "mtspr",
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0, OP_RT_SPR, 31<<26 | 339<<1, "mfspr",
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0, OP_RS_FXM, 31<<26 | 0<<21 | 144<<1, "mtcrf",
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0, OP_RT, 31<<26 | 0<<21 | 19<<1, "mfcr",
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0, OP_RS_FXM, 31<<26 | 0<<20 | 144<<1, "mtcrf",
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0, OP_RT, 31<<26 | 0<<20 | 19<<1, "mfcr",
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/* extended m for special purpose registers */
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/* extended m for special purpose registers (page 153) */
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0, OP_RT, 31<<26 | 9<<16 | 0<<11 | 339<<1, "mfctr",
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0, OP_RT, 31<<26 | 8<<16 | 0<<11 | 339<<1, "mflr",
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0, OP_RT, 31<<26 | 1<<16 | 0<<11 | 339<<1, "mfxer",
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0, OP_RT, 31<<26 | 9<<16 | 0<<11 | 467<<1, "mtctr",
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0, OP_RT, 31<<26 | 8<<16 | 0<<11 | 467<<1, "mtlr",
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0, OP_RT, 31<<26 | 1<<16 | 0<<11 | 467<<1, "mtxer",
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0, OP_RS, 31<<26 | 9<<16 | 0<<11 | 467<<1, "mtctr",
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0, OP_RS, 31<<26 | 8<<16 | 0<<11 | 467<<1, "mtlr",
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0, OP_RS, 31<<26 | 1<<16 | 0<<11 | 467<<1, "mtxer",
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/* extended m for condition register (page 154) */
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0, OP_RS, 31<<26 | 0<<20 | 255<<12 | 144<<1, "mtcr",
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/* Floating point instructions (page 83) */
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/* page 98 */
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0, OP_FRT_RA_D, 48<<26, "lfs",
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0, OP_FRT_RA_RB, 31<<26 | 535<<1, "lfsx",
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0, OP_FRT_RA_D, 49<<26, "lfsu",
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@ -606,6 +613,7 @@
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0, OP_FRS_RA_RB, 31<<26 | 759<<1, "stfdux",
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0, OP_FRS_RA_RB, 31<<26 | 983<<1, "stfiwx",
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/* page 104 */
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0, OP_FRT_FRB_C, 63<<26 | 72<<1, "fmr",
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0, OP_FRT_FRB_C, 63<<26 | 40<<1, "fneg",
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0, OP_FRT_FRB_C, 63<<26 | 264<<1, "fabs",
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@ -629,6 +637,7 @@
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0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 30<<1, "fnmsub",
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0, OP_FRT_FRA_FRC_FRB_C, 59<<26 | 30<<1, "fnmsubs",
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/* page 109 */
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0, OP_FRT_FRB_C, 63<<26 | 12<<1, "frsp",
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0, OP_FRT_FRB_C, 63<<26 | 814<<1, "fctid",
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0, OP_FRT_FRB_C, 63<<26 | 815<<1, "fctidz",
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@ -652,4 +661,31 @@
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0, OP_FRT_FRB_C, 63<<26 | 26<<1, "frsqrte",
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0, OP_FRT_FRA_FRC_FRB_C, 63<<26 | 23<<1, "fsel",
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/* page 98 */
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/* Storage control instructions (Book II, page 15) */
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/* Book II, page 17 */
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0, OP_RA_RB, 31<<26 | 982<<1, "icbi",
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0, OP_RA_RB_TH /* page 35 */, 31<<26 | 278<<1, "dcbt",
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0, OP_RA_RB, 31<<26 | 246<<1, "dcbtst",
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0, OP_RA_RB, 31<<26 | 1014<<1, "dcbz",
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0, OP_RA_RB, 31<<26 | 54<<1, "dcbst",
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0, OP_RA_RB, 31<<26 | 86<<1, "dcbf",
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0, OP, 19<<26 | 150<<1, "isync",
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0, OP_RT_RA_RB, 31<<26 | 20<<1, "lwarx",
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0, OP_RT_RA_RB, 31<<26 | 84<<1, "ldarx",
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0, OP_RS_RA_RB_CC, 31<<26 | 150<<1 | 1<<0, "stwcx",
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0, OP_RS_RA_RB_CC, 31<<26 | 150<<1 | 1<<0, "stdcx",
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0, OP_L, 31<<26 | 598<<1, "sync",
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0, OP, 31<<26 | 1<<21 | 598<<1, "lwsync",
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0, OP, 31<<26 | 2<<21 | 598<<1, "ptesync",
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0, OP, 31<<26 | 854<<1, "eieio",
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/* Time base (Book II, page 30) */
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0, OP_RT_TBR, 31<<26 | 371<<1, "mftb",
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0, OP_RT, 31<<26 | 8<<11 | 13<<16 | 371<<1, "mftbu",
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/* External control (Book II, page 33) */
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0, OP_RT_RA_RB, 31<<26 | 310<<1, "eciwx",
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0, OP_RS_RA_RB, 31<<26 | 438<<1, "ecowx",
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@ -42,7 +42,23 @@ operation
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| OP_FRT_RA_D FPR ',' e16 '(' GPR ')' { emit_hl($1 | ($2<<21) | ($6<<16) | $4); }
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| OP_FRT_RA_RB FPR ',' GPR ',' GPR { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
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| OP_FRT_C c FPR { emit4($1 | $2 | ($3<<21)); }
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| OP_RA_RS_C c GPR ',' GPR { emit4($1 | $2 | ($5<<21) | ($3<<16)); }
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| OP_L { emit4($1); }
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| OP_L u2 { emit4($1 | ($2<<21)); }
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| OP_LEV { emit4($1); }
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| OP_LEV u7 { emit4($1 | ($2<<5)); }
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| OP_RA_RB GPR ',' GPR
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{ emit4($1 | ($2<<16) | ($4<<11)); }
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| OP_RA_RB_TH GPR ',' GPR opt_bh
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{ emit4($1 | $5 | ($2<<16) | ($4<<11)); }
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/*
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* For instructions with "mnemonic RS, RA, ..."
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* OP_RA_RS_... swaps RS and RA to (RA<<21) || (RS<<16)
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* OP_RS_RA_... keeps RS and RA as (RS<<21) || (RA<<16)
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*/
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| OP_RA_RS_C c GPR ',' GPR
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{ emit4($1 | $2 | ($5<<21) | ($3<<16)); }
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| OP_RA_RS_RA_C c GPR ',' GPR
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{ emit4($1 | $2 | ($5<<21) | ($3<<16) | ($5<<11)); }
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| OP_RA_RS_RB_C c GPR ',' GPR ',' GPR
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{ emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11)); }
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| OP_RA_RS_RB_MB5_ME5_C c GPR ',' GPR ',' GPR ',' u5 ',' u5
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@ -75,20 +91,19 @@ operation
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| OP_RT_RB_RA_C c GPR ',' GPR ',' GPR { emit4($1 | $2 | ($3<<21) | ($7<<16) | ($5<<11)); }
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| OP_RT_SI GPR ',' e16 { emit_hl($1 | ($2<<21) | $4); }
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| OP_RT_SPR GPR ',' spr_num { emit4($1 | ($2<<21) | ($4<<11)); }
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| OP_RT_TBR GPR opt_tbr { emit4($1 | ($2<<21) | ($3<<11)); }
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| OP_RS GPR { emit4($1 | ($2<<21)); }
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| OP_RS_FXM u7 ',' GPR { emit4($1 | ($4<<21) | ($2<<12)); }
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| OP_RS_RA_D GPR ',' e16 '(' GPR ')' { emit_hl($1 | ($2<<21) | ($6<<16) | $4); }
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| OP_RS_RA_DS GPR ',' ds '(' GPR ')' { emit_hl($1 | ($2<<21) | ($6<<16) | $4); }
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| OP_RS_RA_NB GPR ',' GPR ',' nb { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
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| OP_RS_RA_RB GPR ',' GPR ',' GPR { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
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| OP_RS_RA_RB_C c GPR ',' GPR ',' GPR { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($7<<11)); }
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| OP_RS_RA_RA_C c GPR ',' GPR { emit4($1 | $2 | ($5<<21) | ($3<<16) | ($5<<11)); }
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| OP_RS_RA_RB_CC C GPR ',' GPR ',' GPR { emit4($1 | ($3<<21) | ($5<<16) | ($7<<11)); }
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| OP_RS_SPR spr_num ',' GPR { emit4($1 | ($4<<21) | ($2<<11)); }
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| OP_TO_RA_RB u5 ',' GPR ',' GPR { emit4($1 | ($2<<21) | ($4<<16) | ($6<<11)); }
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| OP_TO_RA_SI u5 ',' GPR ',' e16 { emit_hl($1 | ($2<<21) | ($4<<16) | $6); }
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| OP_TOX_RA_RB GPR ',' GPR { emit4($1 | ($2<<16) | ($4<<11)); }
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| OP_TOX_RA_SI GPR ',' e16 { emit_hl($1 | ($2<<16) | $4); }
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| OP_LEV { emit4($1); }
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| OP_LEV u7 { emit4($1 | ($2<<5)); }
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| OP_LIA lia { emit4($1 | $2); }
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| OP_LIL lil { emit4($1 | $2); }
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| OP_LI32 li32 /* emitted in subrule */
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@ -298,7 +313,7 @@ u2
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}
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;
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/* Optional comma, branch hint. */
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/* Optional comma, branch hint (or touch hint). */
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opt_bh
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: /* nothing */ { $$ = 0; }
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| ',' u2 { $$ = ($2<<11); }
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@ -409,13 +424,28 @@ lia
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}
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;
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/*
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* Instructions "mfspr", "mtspr", and "mftb" encode the 10-bit special
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* purpose register (spr) or time base register (tbr) by swapping the
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* low 5 bits with the high 5 bits. The value from an SPR token has
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* already been swapped.
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*/
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spr_num
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: SPR { $$ = $1; }
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| absexp
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| tbr_num { $$ = $1; }
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;
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opt_tbr
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: /* nothing */ { $$ = 8 | (12<<5); }
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| ',' tbr_num { $$ = $2; }
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;
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tbr_num
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: absexp
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{
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if (($1 < 0) || ($1 > 0x3ff))
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serror("spr number out of range");
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/* mfspr, mtspr swap the low and high 5 bits */
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serror("10-bit unsigned value out of range");
|
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$$ = ($1 >> 5) | (($1 & 0x1f) << 5);
|
||||
}
|
||||
;
|
||||
|
|
|
|||
145
man/powerpc_as.6
145
man/powerpc_as.6
|
|
@ -1,33 +1,136 @@
|
|||
.TH POWERPC_AS 1
|
||||
.TH POWERPC_AS 1 2018-03-07
|
||||
.ad
|
||||
.SH NAME
|
||||
powerpc_as \- assembler for PowerPC
|
||||
|
||||
.SH SYNOPSIS
|
||||
as [options] argument ...
|
||||
|
||||
.SH DESCRIPTION
|
||||
This assembler is made with the general framework
|
||||
described in \fIuni_ass\fP(6).
|
||||
|
||||
.PP
|
||||
It can assemble the instructions from Book I and Book II of PowerPC
|
||||
version 2.01.
|
||||
This includes the branch, integer, and floating point instructions
|
||||
from Book I; and the cache, synchronization, and time base
|
||||
instructions from Book II.
|
||||
.PP
|
||||
There is no support for other instructions, such as supervisor-mode
|
||||
instructions or vector instructions.
|
||||
There is some support for 64-bit integer instructions, but the
|
||||
assembler only has 32-bit symbols.
|
||||
.SH SYNTAX
|
||||
Most 32-bit integer and floating point instructions are supported, but not many
|
||||
short form instructions. Instructions which take 16-bit operands can additionally
|
||||
use the following special functions:
|
||||
|
||||
.IP hi16[value], ha16[value]
|
||||
Returns the high half of the value of the expression; if the value is not absolute,
|
||||
also generates the appropriate fixup. Use of either of these \fImust\fR be followed,
|
||||
in the next instruction, by the corresponding use of \fBlo16[]\fR. Use \fBhi16[]\fR
|
||||
if the low half is going to interpret its payload as an unsigned value, and
|
||||
\fBha16[]\fR if it will be interpreted as a signed value (so that the high half can
|
||||
be adjusted to match).
|
||||
|
||||
.IP lo16[]
|
||||
Returns the low half of the value of the expression. No fixup is generated. Use of
|
||||
\fBlo16[]\fR must come in the instruction immediately after a use of \fBhi16[]\fR or
|
||||
\fBha16[]\fR.
|
||||
|
||||
.SS general purpose registers
|
||||
There are 32 GPRs from \fBr0\fP to \fBr31\fP.
|
||||
In this assembler, \fBsp\fP is an alias for \fBr1\fP, and \fBfp\fP is
|
||||
an alias for \fBr2\fP, because \fIack\fP uses r1 as the stack pointer
|
||||
and r2 as the frame pointer.
|
||||
Other compilers don't use r2 as the frame pointer.
|
||||
.PP
|
||||
GPR syntax requires a register name, not a number.
|
||||
For example, \(oqaddi\ r5,\ r4,\ 1\(cq works, but
|
||||
\(oqaddi\ 5,\ 4,\ 1\(cq is a syntax error.
|
||||
.PP
|
||||
Certain instructions ignore the contents of \fBr0\fP and use zero.
|
||||
This happens when using r0 as the second operand of \fIaddi\fP or
|
||||
\fIaddis\fP, or when addressing \(oqexpr(r0)\(cq or
|
||||
\(oqr0,\ gpr\(cq.
|
||||
The syntax is still the name r0, not the number 0.
|
||||
.SS floating point registers
|
||||
There are 32 FPRs from \fBf0\fP to \fBf31\fP.
|
||||
Each FPR has 64 bits and can hold a single-precision or
|
||||
double-precision number.
|
||||
FPR syntax requires a register name, not a number.
|
||||
.SS special purpose registers
|
||||
The three named SPRs are \fBctr\fP (count register), \fBlr\fP (link
|
||||
register), and \fBxer\fP (exception register).
|
||||
\(oqmfspr\(cq and \(oqmtspr\(cq allow these names or a number.
|
||||
.SS condition register
|
||||
There is a 32-bit condition register, where bit 0 is most significant,
|
||||
and bit 31 is least significant.
|
||||
This gets split into 8 registers of 4 bits each, from \fBcr0\fP (with
|
||||
bits 0 to 3) to \fBcr7\fP (with bits 28 to 31).
|
||||
Some instructions use the names cr0 to cr7, others use a bit numbered
|
||||
0 to 31, and others use all 32 bits.
|
||||
.SS addressing modes
|
||||
\(oqexpr(gpr)\(cq addresses \fIexpr\fP + the contents of \fIgpr\fP,
|
||||
except that \(oqexpr(r0)\(cq addresses \fIexpr\fP\ +\ 0.
|
||||
A few instructions, like \(oqstwu\(cq, also update \fIgpr\fP by
|
||||
setting it to the address.
|
||||
.PP
|
||||
\(oqgprA,\ gprB\(cq in certain instructions addresses the contents of
|
||||
\fIgprA\fP + the contents of \fIgprB\fP, except that \(oqr0,\ gprB\(cq
|
||||
addresses 0\ +\ the contents of \fIgprB\fP.
|
||||
.SS 16-bit operands
|
||||
Some instructions have a 16-bit operand.
|
||||
This can be a bare \fIexpr\fP (which must fit signed or unsigned
|
||||
16 bits), or it can be one of these special functions:
|
||||
.IP "hi16[expr], ha16[expr]"
|
||||
Returns the high half of the 32-bit value of the expression.
|
||||
If the low half is negative (from 0x8000 to 0xffff),
|
||||
then \fBha16[]\fP adjusts the high half by adding 1.
|
||||
Use \fBhi16[]\fP if the instruction with \fBlo16[]\fP is going to
|
||||
interpret its operand as an unsigned value, or \fBha16[]\fP if it will
|
||||
interpret it as signed.
|
||||
.IP
|
||||
If \fIexpr\fP is not absolute, then the assembler must generate a
|
||||
fixup for the linker.
|
||||
The fixup only works if the instruction is
|
||||
\(oqaddis gpr, r0, hx16[expr]\(cq or \(oqlis gpr, hx16[expr]\(cq.
|
||||
.IP lo16[expr]
|
||||
Returns the low half of the 32-bit value of the expression.
|
||||
.SS short forms
|
||||
Some instructions have short forms using extended mnemonics (or
|
||||
simplified mnemonics) like \fIli\fP, \fIsrwi\fP, and many others.
|
||||
.IP "li r6, 789"
|
||||
is short for: addi r6, r0, 789
|
||||
.IP "srwi r3, r4, 2"
|
||||
is short for: rlwinm r3, r4, 30, 2, 31
|
||||
.PP
|
||||
This assembler doesn't support extended mnemonics with branch
|
||||
prediction, such as \fIblt+\fP or \fIbne-\fP.
|
||||
It always parses \(oq+\(cq and \(oq-\(cq as operators,
|
||||
never as part of a mnemonic.
|
||||
.SH EXAMPLES
|
||||
There are two ways to load r3 with _symbol\ =\ 0x1234abcd.
|
||||
One way is
|
||||
.PP
|
||||
.nf
|
||||
lis r3, hi16[_symbol]
|
||||
ori r3, r3, lo16[_symbol] ! r3 = 0x12340000 | 0x0000abcd
|
||||
.fi
|
||||
.PP
|
||||
The other way is
|
||||
.PP
|
||||
.nf
|
||||
lis r3, ha16[_symbol]
|
||||
addi r3, r3, lo16[_symbol] ! r3 = 0x12350000 + 0xffffabcd
|
||||
.fi
|
||||
.PP
|
||||
The next code adds 1 to a global variable.
|
||||
.PP
|
||||
.nf
|
||||
lis r3, ha16[_var]
|
||||
lwz r4, lo16[_var](r3)
|
||||
addi r4, r4, 1
|
||||
stw r4, lo16[_var](r3)
|
||||
.fi
|
||||
.SH "SEE ALSO"
|
||||
uni_ass(6),
|
||||
ack(1)
|
||||
.PP
|
||||
Freescale Semiconductor, \fIProgramming Environments Manual for 32-Bit
|
||||
Implementations of the PowerPC Architecture\fP, Rev. 3, September 2005.
|
||||
.PP
|
||||
IBM, \fIPowerPC User Instruction Set Architecture, Book I\fP, Version
|
||||
2.01, September 2003.
|
||||
.PP
|
||||
IBM, \fIPowerPC Virtual Environment Architecture, Book II\fP, Version
|
||||
2.01, December 2003.
|
||||
.SH CAVEATS
|
||||
Beware that not every processor can run every instruction.
|
||||
The 32-bit processors can't run 64-bit instructions like \fIlwa\fP,
|
||||
\fIstd\fP, and \fIfctid\fP.
|
||||
The PowerPC 601 can't run \fIstfiwx\fP, nor \fIfres\fP, \fIfrsqrte\fP,
|
||||
\fIfsel\fP.
|
||||
Many models, like the PowerPC G4, can't run \fIfsqrt\fP nor
|
||||
\fIfsqrts\fP.
|
||||
|
|
|
|||
Loading…
Reference in a new issue