some more additions

This commit is contained in:
ceriel 1987-08-17 16:24:56 +00:00
parent 46589d5798
commit b3a30acb30

View file

@ -375,6 +375,7 @@ lol lal sti $1==$2 && $3<=2 | | | | |
#ifdef REGVARS
stl inreg($1)==2
| rmorconst |
remove(regvar($1))
move(%[1], regvar($1)) | | |
... | nocoercions : STACK |
"pop %(regvar($1)%)" samecc | | |(1,8)
@ -786,6 +787,7 @@ rmu !defined($1)| X_ACC |
"call .rmu" erase(%[1]) | | |
*/
slu | | | | sli $1 |
lol loc slu | | | | lol $1 loc $2 sli $3 |
loc sru $1==1 && $2==2 | X_REG |
"shr %[1],1"
setcc(%[1]) erase(%[1]) | %[1] | | (2,2)
@ -1045,6 +1047,7 @@ inc | X_REG |
setcc(%[1]) erase(%[1]) | %[1] | |(1,2)
#ifdef REGVARS
inl inreg($1)==2| |
remove(regvar($1))
"inc %(regvar($1)%)"
setcc(regvar($1)) | | |(1,2)
#endif
@ -1060,6 +1063,7 @@ dec | X_REG |
setcc(%[1]) erase(%[1]) | %[1] | |(1,2)
#ifdef REGVARS
del inreg($1)==2| |
remove(regvar($1))
"dec %(regvar($1)%)"
setcc(regvar($1)) | | |(1,2)
#endif
@ -1072,6 +1076,7 @@ dee | | remove(indirects)
setcc({EXTERN2,$1}) | | |(4,21)
#ifdef REGVARS
zrl inreg($1)==2| |
remove(regvar($1))
move({ANYCON,0},regvar($1)) | | |
#endif
zrl | | remove(indexed)
@ -1111,6 +1116,7 @@ zer !defined($1)| X_CXREG |
#ifdef REGVARS
lol adi stl $1==$3 && $2==2 && inreg($1)==2 | rmorconst |
remove(regvar($1))
"add %(regvar($1)%),%[1]"
setcc(regvar($1)) | | |
#endif
@ -1125,7 +1131,42 @@ ldl adi sdl $1==$3 && $2==4 | regorconst regorconst |
"add $1(bp),%[1]"
"adc %($1+2%)(bp),%[2]" | | |
#ifdef REGVARS
lol loc sbi stl $1==$4 && $3==2 | |
remove(regvar($1))
"sub %(regvar($1)%),$2"
setcc(regvar($1)) | | |
lol loc sli stl $1==$4 && $2==1 && $3==2 | |
remove(regvar($1))
"sal %(regvar($1)%),1"
setcc(regvar($1)) | | |
lol loc sli stl $1==$4 && $2==2 && $3==2 | |
remove(regvar($1))
"sal %(regvar($1)%),1"
"sal %(regvar($1)%),1"
setcc(regvar($1)) | | |
lol loc sli stl $1==$4 && $3==2 | |
remove(regvar($1))
allocate(CXREG = {ANYCON, $2})
"sar %(regvar($1)%),cl"
setcc(regvar($1)) | | |
lol loc sri stl $1==$4 && $2==1 && $3==2 | |
remove(regvar($1))
"sar %(regvar($1)%),1"
setcc(regvar($1)) | | |
lol loc sri stl $1==$4 && $2==2 && $3==2 | |
remove(regvar($1))
"sar %(regvar($1)%),1"
"sar %(regvar($1)%),1"
setcc(regvar($1)) | | |
lol loc sri stl $1==$4 && $3==2 | |
remove(regvar($1))
allocate(CXREG = {ANYCON, $2})
"sar %(regvar($1)%),cl"
setcc(regvar($1)) | | |
#endif
#ifdef REGVARS
lol ngi stl $1==$3 && $2==2 && inreg($1)==2 | |
remove(regvar($1))
"neg %(regvar($1)%)"
setcc(regvar($1)) | | |
#endif
@ -1157,6 +1198,7 @@ lol adp stl $1==$3 && $2==1 | | | | inl $1 |
lol adp stl $1==$3 && $2==0-1 | | | | del $1 |
#ifdef REGVARS
lol adp stl $1==$3 && inreg($1)==2 | |
remove(regvar($1))
"add %(regvar($1)%),$2"
setcc(regvar($1)) | | |
#endif
@ -1167,6 +1209,7 @@ lol adp stl $1==$3 | |
setcc({LOCAL2, $1, 2}) | | |
#ifdef REGVARS
lol and stl $1==$3 && $2==2 && inreg($1)==2 | rmorconst |
remove(regvar($1))
"and %(regvar($1)%),%[1]"
setcc(regvar($1)) | | |
#endif
@ -1177,6 +1220,7 @@ lol and stl $1==$3 && $2==2 | regorconst |
setcc({LOCAL2, $1, 2}) | | |
#ifdef REGVARS
lol ior stl $1==$3 && $2==2 && inreg($1)==2 | rmorconst |
remove(regvar($1))
"or %(regvar($1)%),%[1]"
setcc(regvar($1)) | | |
#endif
@ -1187,6 +1231,7 @@ lol ior stl $1==$3 && $2==2 | regorconst |
setcc({LOCAL2, $1, 2}) | | |
#ifdef REGVARS
lol com stl $1==$3 && $2==2 && inreg($1)==2 | |
remove(regvar($1))
"not %(regvar($1)%)"
samecc | | |
#endif