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fixes to additions

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This commit is contained in:
ceriel 1987-08-17 18:09:31 +00:00
parent ddecd62870
commit b3e649e463
1 changed files with 14 additions and 7 deletions
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21
mach/i86/cg/table
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@ -1132,34 +1132,41 @@ ldl adi sdl $1==$3 && $2==4 | regorconst regorconst |
"add $1(bp),%[1]" "add $1(bp),%[1]"
"adc %($1+2%)(bp),%[2]" | | | "adc %($1+2%)(bp),%[2]" | | |
#ifdef REGVARS #ifdef REGVARS
lol loc sbi stl $1==$4 && $3==2 | | lol loc sbi stl $1==$4 && $3==2 && inreg($1)==2 | |
remove(regvar($1)) remove(regvar($1))
"sub %(regvar($1)%),$2" "sub %(regvar($1)%),$2"
setcc(regvar($1)) | | | setcc(regvar($1)) | | |
lol loc sli stl $1==$4 && $2==1 && $3==2 | | #endif
lol loc sbi stl $1==$4 && $3==2 | |
remove(indexed)
remove(locals, %[ind]>=$1 && %[ind]<$1+2 )
"sub $1(bp),%[1]"
setcc({LOCAL2, $1, 2}) | | |
#ifdef REGVARS
lol loc sli stl $1==$4 && $2==1 && $3==2 && inreg($1)==2 | |
remove(regvar($1)) remove(regvar($1))
"sal %(regvar($1)%),1" "sal %(regvar($1)%),1"
setcc(regvar($1)) | | | setcc(regvar($1)) | | |
lol loc sli stl $1==$4 && $2==2 && $3==2 | | lol loc sli stl $1==$4 && $2==2 && $3==2 && inreg($1)==2 | |
remove(regvar($1)) remove(regvar($1))
"sal %(regvar($1)%),1" "sal %(regvar($1)%),1"
"sal %(regvar($1)%),1" "sal %(regvar($1)%),1"
setcc(regvar($1)) | | | setcc(regvar($1)) | | |
lol loc sli stl $1==$4 && $3==2 | | lol loc sli stl $1==$4 && $3==2 && inreg($1)==2 | |
remove(regvar($1)) remove(regvar($1))
allocate(CXREG = {ANYCON, $2}) allocate(CXREG = {ANYCON, $2})
"sar %(regvar($1)%),cl" "sar %(regvar($1)%),cl"
setcc(regvar($1)) | | | setcc(regvar($1)) | | |
lol loc sri stl $1==$4 && $2==1 && $3==2 | | lol loc sri stl $1==$4 && $2==1 && $3==2 && inreg($1)==2 | |
remove(regvar($1)) remove(regvar($1))
"sar %(regvar($1)%),1" "sar %(regvar($1)%),1"
setcc(regvar($1)) | | | setcc(regvar($1)) | | |
lol loc sri stl $1==$4 && $2==2 && $3==2 | | lol loc sri stl $1==$4 && $2==2 && $3==2 && inreg($1)==2 | |
remove(regvar($1)) remove(regvar($1))
"sar %(regvar($1)%),1" "sar %(regvar($1)%),1"
"sar %(regvar($1)%),1" "sar %(regvar($1)%),1"
setcc(regvar($1)) | | | setcc(regvar($1)) | | |
lol loc sri stl $1==$4 && $3==2 | | lol loc sri stl $1==$4 && $3==2 && inreg($1)==2 | |
remove(regvar($1)) remove(regvar($1))
allocate(CXREG = {ANYCON, $2}) allocate(CXREG = {ANYCON, $2})
"sar %(regvar($1)%),cl" "sar %(regvar($1)%),cl"