Replaced clr by the faster mov #0, (for d registers).
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@ -93,7 +93,7 @@ mli_2W:
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#else
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#else
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move.l (sp)+,d0 ; move.l (sp)+,d1
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move.l (sp)+,d0 ; move.l (sp)+,d1
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#endif
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#endif
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4: clr.w d5 ; tst.l d0 ; bpl 5f
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4: move.l #0,d5 ; tst.l d0 ; bpl 5f
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neg.l d0 ; not.w d5
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neg.l d0 ; not.w d5
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5: tst.l d1 ; bpl 6f
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5: tst.l d1 ; bpl 6f
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neg.l d1 ; not.w d5
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neg.l d1 ; not.w d5
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@ -189,6 +189,7 @@ rmi_2W:
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jmp (a4)
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jmp (a4)
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! 2byte division . In d1: quotient=low word ; remainder=high word
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! 2byte division . In d1: quotient=low word ; remainder=high word
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#ifndef lword
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dvi2: move.l (sp)+,d2
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dvi2: move.l (sp)+,d2
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move.w (sp)+,d0 !divisor
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move.w (sp)+,d0 !divisor
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move.w (sp)+,d1 ; ext.l d1 !dividend
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move.w (sp)+,d1 ; ext.l d1 !dividend
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@ -203,6 +204,7 @@ dvi2: move.l (sp)+,d2
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#endif
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#endif
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divs d0,d1
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divs d0,d1
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4: move.l d2,-(sp) ; rts
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4: move.l d2,-(sp) ; rts
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#endif
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! long signed division . quotient in d1 , remainder in d3
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! long signed division . quotient in d1 , remainder in d3
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dvi4: move.l (sp)+,d5
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dvi4: move.l (sp)+,d5
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@ -214,7 +216,7 @@ dvi4: move.l (sp)+,d5
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0: bsr e_iund
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0: bsr e_iund
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1:
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1:
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#endif
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#endif
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clr.l d4 !sign in d4
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move.l #0,d4 !sign in d4
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tst.l d0 ; bpl 1f
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tst.l d0 ; bpl 1f
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neg.l d0 ; not.w d4
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neg.l d0 ; not.w d4
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1: tst.l d1 ; bpl 2f
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1: tst.l d1 ; bpl 2f
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@ -238,7 +240,7 @@ dvu4:
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bsr e_idivz
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bsr e_idivz
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1:
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1:
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#endif
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#endif
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clr.l d3 ; move.l #32,d2
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move.l #0,d3 ; move.l #32,d2
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3: lsl.l #1,d1 ; roxl.l #1,d3
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3: lsl.l #1,d1 ; roxl.l #1,d3
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cmp.l d0,d3 ; blt 4f
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cmp.l d0,d3 ; blt 4f
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sub.l d0,d3 ; add.l #1,d1
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sub.l d0,d3 ; add.l #1,d1
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