Disable register variables. The code is a bit worse, but having two stackable registers makes things much easier to understand.
--HG-- branch : dtrg-videocore
This commit is contained in:
David Given
parent
d7efb0a32c
commit
b6680a48cc
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@ -1,5 +1,5 @@
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arch-libem-vc4 := \
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dummy.s
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csa.s
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arch-libend-vc4 = \
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edata.s \
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@ -21,12 +21,19 @@ PC_OFFSET = 4 /* Offset of saved PC relative to our FP */
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#define nicesize(x) ((x)==BYTE || (x)==WORD || (x)==QUAD)
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/* #define REGVARS */
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#ifndef REGVARS
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#define regvar
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#define return
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#endif
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PROPERTIES
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GPR /* any GPR */
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REG /* any allocatable GPR */
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STACKABLE /* a register than can be used with push/pop */
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GPR0 GPR1 GPR2 GPR3 GPR4 GPR5 GPR6 GPR7
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GPR8 GPR9 GPR10 GPR11 GPR12 GPR13 GPR14 GPR15
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@ -36,13 +43,17 @@ PROPERTIES
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REGISTERS
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R0("r0") : GPR, REG, GPR0.
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R0("r0") : GPR, REG, GPR0, STACKABLE.
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R1("r1") : GPR, REG, GPR1.
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R2("r2") : GPR, REG, GPR2.
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R3("r3") : GPR, REG, GPR3.
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R4("r4") : GPR, REG, GPR4.
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R5("r5") : GPR, REG, GPR5.
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R6("r6") : GPR, REG, GPR6 regvar.
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#if defined REGVARS
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R6("r6") : GPR, REG, GPR6, STACKABLE.
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#else
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R6("r6") : GPR, GPR6.
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#endif
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R7("r7") : GPR, REG, GPR7 regvar.
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R8("r8") : GPR, REG, GPR8 regvar.
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R9("r9") : GPR, REG, GPR9 regvar.
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@ -62,7 +73,11 @@ REGISTERS
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PC("pc") : GPR, GPRPC.
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/* r26 to r31 are special and the code generator doesn't touch them. */
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#define SCRATCH R16
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#if defined REGVARS
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#define SCRATCH R16
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#else
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#define SCRATCH R6
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#endif
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TOKENS
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@ -227,6 +242,12 @@ STACKINGRULES
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move %1, %a
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push %a
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from OP to STACK
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uses STACKABLE
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gen
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move %1, %a
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push %a
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from OP+GPRI to STACK
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gen
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comment {LABEL, "push via scratch"}
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@ -369,8 +390,10 @@ PATTERNS
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add %a, {CONST, $1}
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yields %a
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#if defined REGVARS
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pat lol inreg($1)>0 /* Load from local */
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yields {GPRE, regvar($1)}
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#endif
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pat lol /* Load quad from local */
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uses REG
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@ -383,11 +406,13 @@ PATTERNS
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lol $1 + QUAD*1
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lol $1 + QUAD*0
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#if defined REGVARS
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pat stl inreg($1)>0 /* Store to local */
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with CONST+GPRI
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kills regvar($1)
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gen
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move %1, {GPRE, regvar($1)}
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#endif
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pat stl /* Store to local */
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with GPRI
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@ -398,12 +423,14 @@ PATTERNS
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leaving
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stl $1 + QUAD*0
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stl $1 + QUAD*1
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#if defined REGVARS
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pat lil inreg($1)>0 /* Load from indirected local */
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uses REG
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gen
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ld %a, {GPROFFSET, regvar($1), 0}
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yields %a
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#endif
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pat lil /* Load from indirected local */
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leaving
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@ -424,19 +451,20 @@ PATTERNS
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leaving
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loc 0
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stl $1
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#if defined REGVARS
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pat inl inreg($1)>0 /* Increment local in register */
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kills regvar($1)
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gen
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add {GPRE, regvar($1)}, {CONST, 1}
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pat inl inreg($1)<=0 /* Increment local */
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leaving
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lol $1
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loc 1
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adi QUAD
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stl $1
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pat del inreg($1)>0 /* Decrement local in register */
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kills regvar($1)
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gen
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@ -448,6 +476,21 @@ PATTERNS
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loc 1
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sbi QUAD
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stl $1
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#else
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pat inl /* Increment local in register */
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leaving
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lol $1
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loc 1
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adi QUAD
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stl $1
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pat del /* Decrement local in register */
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leaving
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lol $1
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loc 1
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sbi QUAD
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stl $1
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#endif
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/* Global variables */
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@ -1288,7 +1331,7 @@ PATTERNS
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mov SP, FP
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pop FP, PC
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pat ret $1<=QUAD /* Return from procedure, word */
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pat ret $1==QUAD /* Return from procedure, word */
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with GPR0
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gen
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return
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@ -1316,10 +1359,10 @@ PATTERNS
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bl {LABEL, "_memmove"}
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pat csa /* Array-lookup switch */
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with STACK
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with GPR0 GPR1 STACK
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gen
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bl {LABEL, ".csa"}
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b {LABEL, ".csa"}
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pat csb /* Table-lookup switch */
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with STACK
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gen
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@ -1455,6 +1498,10 @@ PATTERNS
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gen
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add SP, %1
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pat asp $1==QUAD /* Adjust stack by constant amount */
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gen
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pop SCRATCH
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pat asp /* Adjust stack by constant amount */
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leaving
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loc $1
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